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1. 发明授权

US06764864B1 BST on low-loss substrates for frequency agile applications 失效
标题翻译： BST用于频率敏捷应用的低损耗衬底
公开(公告)号：US06764864B1
公开(公告)日：2004-07-20
申请号：US10418372
申请日：2003-04-17
申请人： Hao Li , Jeffrey M. Finder , Yong Liang , Corey Overgaard
发明人： Hao Li , Jeffrey M. Finder , Yong Liang , Corey Overgaard
IPC分类号： H01L2100
CPC分类号： H01L21/32105 , C30B25/18 , C30B29/32 , H01L21/31691 , H01L21/7624
摘要： An exemplary system and method for providing a microwave regime, frequency-agile device is disclosed as comprising inter alia: a low-loss, insulating substrate (200); a layer of SiO2 (210) over the surface of said substrate; and a layer of BST (220) deposited over the SiO2 layer (210). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize frequency response or other material characteristics. Exemplary embodiments of the present invention representatively provide for integrated high-efficiency, low-loss microwave components that may be readily incorporated with existing technologies for the improvement of frequency response, device package form factors, weights and/or other manufacturing, device or material performance metrics.
摘要翻译：公开了一种用于提供微波状态的频率敏捷装置的示例性系统和方法，其特别包括：低损耗绝缘基板（200）; 在所述衬底的表面上的SiO 2层（210）; 以及沉积在SiO 2层（210）上的BST（220）层。公开的特征和规范可以被不同地控制，配置，适配或以其他方式任意地修改，以进一步改进或以其它方式优化频率响应或其他材料特性。本发明的示例性实施例代表性地提供了集成的高效率低损耗微波部件，其可以容易地与用于改进频率响应，装置包装形状因子，重量和/或其他制造，装置或材料性能的现有技术结合指标

2. 发明授权

US06750067B2 Microelectronic piezoelectric structure and method of forming the same 失效
标题翻译：微电子压电结构及其形成方法
公开(公告)号：US06750067B2
公开(公告)日：2004-06-15
申请号：US10126772
申请日：2002-04-19
申请人： Ramoothy Ramesh , Yu Wang , Jeffrey M. Finder , Kurt Eisenbeiser , Zhiyi Yu , Ravindranath Droopad
发明人： Ramoothy Ramesh , Yu Wang , Jeffrey M. Finder , Kurt Eisenbeiser , Zhiyi Yu , Ravindranath Droopad
IPC分类号： H01L2100
CPC分类号： B32B9/00 , H01L21/31691 , H01L28/56 , H01L41/0478 , H01L41/0815 , H01L41/1876 , H01L41/319
摘要： A high quality epitaxial layer of monocrystalline Pb(Zr,Ti)O3 can be grown overlying large silicon wafers by first growing an strontium titanate layer on a silicon wafer. The strontium titanate layer is a monocrystalline layer spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide.
摘要翻译：通过首先在硅晶片上生长钛酸锶层，可以将大量的单晶Pb（Zr，Ti）O 3的高品质外延层生长在大的硅晶片上。钛酸锶层是通过硅氧化物的非晶界面层与硅晶片隔开的单晶层。

3. 发明授权

US06563118B2 Pyroelectric device on a monocrystalline semiconductor substrate and process for fabricating same 失效
公开(公告)号：US06563118B2
公开(公告)日：2003-05-13
申请号：US09733181
申请日：2000-12-08
申请人： William J. Ooms , Jeffrey M. Finder , Kurt W. Eisenbeiser , Jerald A. Hallmark
发明人： William J. Ooms , Jeffrey M. Finder , Kurt W. Eisenbeiser , Jerald A. Hallmark
IPC分类号： G01J500
CPC分类号： H01L37/02 , C30B23/02 , C30B25/02 , C30B25/18 , C30B29/32 , H01L21/02381 , H01L21/02488 , H01L21/02505 , H01L21/02521 , H01L27/16
摘要： High quality epitaxial layers of monocrystalline materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer (104) on a silicon wafer (102). The accommodating buffer layer (104) is a layer of monocrystalline material spaced apart from the silicon wafer (102) by an amorphous interface layer (108) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Utilizing this technique permits the fabrication of thin film pyroelectric devices (150) on a monocrystalline silicon substrate.

4. 发明授权

US06482538B2 Microelectronic piezoelectric structure and method of forming the same 失效
标题翻译：微电子压电结构及其形成方法
公开(公告)号：US06482538B2
公开(公告)日：2002-11-19
申请号：US09912994
申请日：2001-07-25
申请人： Ramamoorthy Ramesh , Yu Wang , Jeffrey M. Finder , Zhiyi Yu , Ravindranath Droopad , Kurt Eisenbeiser
发明人： Ramamoorthy Ramesh , Yu Wang , Jeffrey M. Finder , Zhiyi Yu , Ravindranath Droopad , Kurt Eisenbeiser
IPC分类号： B32B1900
CPC分类号： H01L21/02197 , B32B9/00 , H01L21/02293 , H01L21/31691 , H01L28/56 , H01L41/0478 , H01L41/1875 , H01L41/1876 , H01L41/29 , H01L41/319 , Y10T428/24917
摘要： A high quality epitaxial layer of monocrystalline Pb(Mg,Nb)O3—PbTiO3 or Pb(Mg1−xNbx)O3—PbTiO3 can be grown overlying large silicon wafers by first growing an strontium titanate layer on a silicon wafer. The strontium titanate layer is a monocrystalline layer spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide.
摘要翻译：首先在硅晶片上生长钛酸锶层，可以将大量的单晶Pb（Mg，Nb）O3-PbTiO3或Pb（Mg1-xNbx）O3-PbTiO3）的高质量外延层生长在大的硅晶片上。钛酸锶层是通过硅氧化物的非晶界面层与硅晶片隔开的单晶层。

5. 发明授权

US06432546B1 Microelectronic piezoelectric structure and method of forming the same 失效
标题翻译：微电子压电结构及其形成方法
公开(公告)号：US06432546B1
公开(公告)日：2002-08-13
申请号：US09624527
申请日：2000-07-24
申请人： Ramoothy Ramesh , Yu Wang , Jeffrey M. Finder , Kurt Eisenbeiser , Zhiyi Yu , Ravindranath Droopad
发明人： Ramoothy Ramesh , Yu Wang , Jeffrey M. Finder , Kurt Eisenbeiser , Zhiyi Yu , Ravindranath Droopad
IPC分类号： B32B900
CPC分类号： B32B9/00 , H01L21/31691 , H01L28/56 , H01L41/0478 , H01L41/0815 , H01L41/1876 , H01L41/319
摘要： A high quality epitaxial layer of monocrystalline Pb(Zr,Ti)O3 can be grown overlying large silicon wafers by first growing an strontium titanate layer on a silicon wafer. The strontium titanate layer is a monocrystalline layer spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide.
摘要翻译：通过首先在硅晶片上生长钛酸锶层，可以将大量的单晶Pb（Zr，Ti）O 3的高品质外延层生长在大的硅晶片上。钛酸锶层是通过硅氧化物的非晶界面层与硅晶片隔开的单晶层。

6. 发明授权

US06638838B1 Semiconductor structure including a partially annealed layer and method of forming the same 失效
标题翻译：包括部分退火层的半导体结构及其形成方法
公开(公告)号：US06638838B1
公开(公告)日：2003-10-28
申请号：US09678372
申请日：2000-10-02
申请人： Kurt Eisenbeiser , Barbara M. Foley , Jeffrey M. Finder , Danny L. Thompson
发明人： Kurt Eisenbeiser , Barbara M. Foley , Jeffrey M. Finder , Danny L. Thompson
IPC分类号： H01L2120
CPC分类号： H01L21/02521 , H01L21/02381 , H01L21/02439 , H01L21/02488 , H01L21/02505 , H01L21/0251
摘要： High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. To further relieve strain in the accommodating buffer layer, at least a portion of the accommodating buffer layer is exposed to a laser anneal process to cause the accommodating buffer layer to become amorphous, providing a true compliant substrate for subsequent layer growth.
摘要翻译：通过首先在硅晶片上生长容纳缓冲层，可以将复合半导体材料的高质量外延层生长在大的硅晶片上。容纳缓冲层是通过氧化硅的非晶界面层与硅晶片间隔开的单晶氧化物层。非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。容纳缓冲层与下面的硅晶片和上覆的单晶化合物半导体层晶格匹配。通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。为了进一步减轻容纳缓冲层中的应变，容纳缓冲层的至少一部分暴露于激光退火工艺，以使得容纳缓冲层变得非晶体，为随后的层生长提供真正的柔性衬底。

7. 发明授权

US06559471B2 Quantum well infrared photodetector and method for fabricating same 失效
标题翻译：量子阱红外光电探测器及其制造方法
公开(公告)号：US06559471B2
公开(公告)日：2003-05-06
申请号：US09733688
申请日：2000-12-08
申请人： Jeffrey M. Finder , William J. Ooms
发明人： Jeffrey M. Finder , William J. Ooms
IPC分类号： H01L2906
CPC分类号： H01L31/035245 , B82Y20/00 , H01L21/02381 , H01L21/02488 , H01L21/02505 , H01L21/02521 , H01L21/31691 , H01L31/0368 , H01L31/101 , Y02E10/50
摘要： High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer (204) on a silicon wafer (202). The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (206) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. Quantum well infrared photodetectors (200) can be grown on the high quality epitaxial monocrystalline material formed on such compliant substrates to create highly reliable devices having reduced costs.
摘要翻译：通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。实现顺应性衬底的形成的一种方法包括首先在硅晶片（202）上生长容纳缓冲层（204）。容纳缓冲层是通过氧化硅的非晶界面层（206）与硅晶片间隔开的单晶氧化物层。非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。容纳缓冲层与下面的硅晶片和上覆单晶层两者晶格匹配。通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。量子阱红外光电探测器（200）可以在形成于这种柔性衬底上的高质量外延单晶材料上生长，从而产生具有降低成本的高度可靠的器件。

8. 发明授权

US06555946B1 Acoustic wave device and process for forming the same 失效
标题翻译：声波装置及其形成方法
公开(公告)号：US06555946B1
公开(公告)日：2003-04-29
申请号：US09624803
申请日：2000-07-24
申请人： Jeffrey M. Finder , Kurt Eisenbeiser , Jamal Ramdani , Ravindranath Droopad , William Jay Ooms
发明人： Jeffrey M. Finder , Kurt Eisenbeiser , Jamal Ramdani , Ravindranath Droopad , William Jay Ooms
IPC分类号： H01L4108
CPC分类号： H03H9/174 , H01L27/20 , H01L41/319 , H03H3/02 , H03H3/08 , H03H9/02574 , H03H9/0542
摘要： High quality epitaxial layers of piezoelectric material materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.
摘要翻译：通过首先在硅晶片上生长一个容纳缓冲层，可以将高质量的压电材料外延层生长在大的硅晶片上。容纳缓冲层是通过氧化硅的非晶界面层与硅晶片间隔开的单晶氧化物层。非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。

9. 发明授权

US06365474B1 Method of fabricating an integrated circuit 有权
标题翻译：制造集成电路的方法
公开(公告)号：US06365474B1
公开(公告)日：2002-04-02
申请号：US09599697
申请日：2000-06-22
申请人： Jeffrey M. Finder , Kurt Eisenbeiser , Bich-Yen Nguyen
发明人： Jeffrey M. Finder , Kurt Eisenbeiser , Bich-Yen Nguyen
IPC分类号： H01L21336
CPC分类号： H01L29/66545
摘要： A transistor (12) and method of making an integrated circuit (10) uses a chromium based sacrificial gate (22A) to align, dope and activate source and drain portions (36, 38, 52, 53,) of the transistor. The transistor is subjected to a high temperature to activate the source and drain, which would damage a high permittivity gate dielectric. The sacrificial gate is removed by etching with ceric ammonia nitrate. A high permittivity gate dielectric (72) and a final gate electrode (74) are formed over a channel (30) of the transistor. Electrodes (76, 78) are formed for coupling to the source and drain.
摘要翻译：晶体管（12）和制造集成电路（10）的方法使用铬基牺牲栅极（22A）来对准，掺杂并激活晶体管的源极和漏极部分（36,38,52,53）。晶体管经受高温以激活源极和漏极，这将损坏高介电常数栅极电介质。通过用硝酸铈铵蚀刻除去牺牲栅极。在晶体管的沟道（30）上形成高介电常数栅极电介质（72）和最终栅电极（74）。电极（76,78）形成为用于耦合到源极和漏极。

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