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1. 发明授权

US06383920B1 Process of enclosing via for improved reliability in dual damascene interconnects 有权
标题翻译：封装通孔的过程可提高双镶嵌互连中的可靠性
公开(公告)号：US06383920B1
公开(公告)日：2002-05-07
申请号：US09757894
申请日：2001-01-10
申请人： Ping-Chuan Wang , Ronald G. Filippi , Robert D. Edwards , Edward W. Kiewra , Roy C. Iggulden
发明人： Ping-Chuan Wang , Ronald G. Filippi , Robert D. Edwards , Edward W. Kiewra , Roy C. Iggulden
IPC分类号： H01L214763
CPC分类号： H01L21/76847 , H01L21/76807 , H01L21/76811 , H01L21/76813 , H01L21/76843 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates generally to a method of enclosing a via in a dual damascene process. In one embodiment of the disclosed method, the via is etched first and a first barrier metal or liner is deposited in the via, the trench is then etched and a second barrier metal or liner is deposited in the trench, and finally the via and trench are filled or metallized in a dual damascene process, thereby forming a via or interconnect and a line. Alternatively, the trench may be etched first and a first barrier metal or liner deposited in the trench, then the via is etched and a second barrier metal or liner is deposited in the via, and finally the trench and via are filled or metallized in a dual damascene process. The barrier metal or liner encloses the via, thereby reducing void formation due to electromigration.
摘要翻译：本发明一般涉及在双镶嵌工艺中封闭通孔的方法。在所公开的方法的一个实施例中，首先蚀刻通孔，并且在通孔中沉积第一阻挡金属或衬垫，然后蚀刻沟槽，并且在沟槽中沉积第二阻挡金属或衬垫，最后沉积通孔和沟槽在双镶嵌工艺中填充或金属化，从而形成通孔或互连线。或者，可以首先蚀刻沟槽并且沉积在沟槽中的第一阻挡金属或衬垫，然后蚀刻通孔，并且在通孔中沉积第二阻挡金属或衬垫，最后将沟槽和通孔填充或金属化在双镶嵌工艺。阻挡金属或衬里封闭通孔，从而减少由于电迁移而导致的空隙形成。

2. 发明授权

US07287325B2 Method of forming interconnect structure or interconnect and via structures using post chemical mechanical polishing 失效
标题翻译：使用后化学机械抛光形成互连结构或互连和通孔结构的方法
公开(公告)号：US07287325B2
公开(公告)日：2007-10-30
申请号：US10908392
申请日：2005-05-10
申请人： Kaushik Chanda , James J. Demarest , Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Ping-Chuan Wang , Yun-Yu Wang
发明人： Kaushik Chanda , James J. Demarest , Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Ping-Chuan Wang , Yun-Yu Wang
IPC分类号： H01K3/10
CPC分类号： B24B37/042 , H01L21/31144 , H01L21/76834 , H01L21/7684 , H01L21/76849 , H01L21/76852 , H01L21/76885 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204
摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.
摘要翻译：公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。释放层沉积在电介质层上。释放层包括有机材料，电介质材料，金属或金属氮化物。沟槽蚀刻到电介质层中。沟槽内衬衬里，填充导体。导体和衬里材料从剥离层抛光。然而，痕量的剩余材料可能会残留。去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。

3. 发明授权

US07361584B2 Detection of residual liner materials after polishing in damascene process 失效
标题翻译：在镶嵌工艺中抛光后残留衬垫材料的检测
公开(公告)号：US07361584B2
公开(公告)日：2008-04-22
申请号：US10904329
申请日：2004-11-04
申请人： Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Stephen K. Loh , Ping-Chuan Wang
发明人： Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Stephen K. Loh , Ping-Chuan Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/7684 , H01L21/3212 , H01L21/7688 , H01L22/24 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer over the liner, wherein the marker layer comprises ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. Moreover, the marker layer comprises a separate layer from the dielectric layer. Additionally, the ultraviolet detectable material comprises fluorescent material or phosphorescent material.
摘要翻译：用于在镶嵌工艺中抛光之后检测残留衬垫材料的方法和结构包括：包括衬底的集成电路; 介电层; 电介质层上的标记层; 标记层和电介质层上的衬垫; 以及在所述衬里上的金属层，其中所述标记层包括紫外线可检测材料，其在通过紫外线激发时表示在所述标记层上不存在所述金属层和所述衬垫。此外，标记层包括与电介质层分离的层。另外，紫外线可检测材料包括荧光材料或磷光材料。

4. 发明授权

US07560375B2 Gas dielectric structure forming methods 失效
标题翻译：气体介电结构成型方法
公开(公告)号：US07560375B2
公开(公告)日：2009-07-14
申请号：US10711697
申请日：2004-09-30
申请人： Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Ping-Chuan Wang
发明人： Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Ping-Chuan Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76831 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a gas dielectric structure for a semiconductor structure by using a sacrificial layer. In particular, one embodiment of the invention includes forming an opening for semiconductor structure in a dielectric layer on a substrate; depositing a sacrificial layer over the opening; performing a directional etch on the sacrificial layer to form a sacrificial layer sidewall on the opening; depositing a conductive liner over the opening; depositing a metal in the opening; planarizing the metal and the conductive liner; removing the sacrificial layer sidewall to form a void; and depositing a cap layer over the void to form the gas dielectric structure. The invention is easily implemented in damascene wire formation processes, and improves structural stability.
摘要翻译：通过使用牺牲层形成用于半导体结构的气体电介质结构的方法。特别地，本发明的一个实施例包括在基板上的电介质层中形成用于半导体结构的开口; 在开口上沉积牺牲层; 在所述牺牲层上执行定向蚀刻以在所述开口上形成牺牲层侧壁; 在所述开口上沉积导电衬垫; 在开口中沉积金属; 平面化金属和导电衬垫; 去除牺牲层侧壁以形成空隙; 以及在所述空隙上沉积盖层以形成气体介电结构。本发明易于在镶嵌线形成过程中实现，并提高结构稳定性。

5. 发明授权

US07473636B2 Method to improve time dependent dielectric breakdown 失效
标题翻译：改善时间依赖介电击穿的方法
公开(公告)号：US07473636B2
公开(公告)日：2009-01-06
申请号：US11306825
申请日：2006-01-12
申请人： Kaushik Chanda , James J. Demarest , Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Vincent J. McGahay , Ping-Chuan Wang , Yun-Yu Wang
发明人： Kaushik Chanda , James J. Demarest , Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Vincent J. McGahay , Ping-Chuan Wang , Yun-Yu Wang
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , H01L21/76846 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level of the interconnect; and a conformal second liner that combines with the first liner to block diffusion of the metal fill material.
摘要翻译：在采用双镶嵌互连的集成电路的后端中，互连构件具有第一非保形衬套，其在互连的沟槽级的顶部具有较厚的部分; 以及与第一衬垫结合以阻挡金属填充材料的扩散的共形第二衬垫。

6. 发明授权

US08525169B1 Reliable physical unclonable function for device authentication 有权
标题翻译：用于设备认证的可靠的物理不可克隆功能
公开(公告)号：US08525169B1
公开(公告)日：2013-09-03
申请号：US13572289
申请日：2012-08-10
申请人： Daniel C. Edelstein , Stephen M. Gates , Edward W. Kiewra , Satyanarayana V. Nitta , Ramachandran Muralidhar , Dirk Pfeiffer
发明人： Daniel C. Edelstein , Stephen M. Gates , Edward W. Kiewra , Satyanarayana V. Nitta , Ramachandran Muralidhar , Dirk Pfeiffer
IPC分类号： H01L21/66 , H01L21/74
CPC分类号： H01L23/544 , H01L21/268 , H01L21/76894 , H01L22/14 , H01L23/5226 , H01L23/53271 , H01L23/573 , H01L2223/5444 , H01L2223/5448 , H01L2924/0002 , H04L9/3247 , H04L9/3278 , H01L2924/00
摘要： The present disclosure relates to a secure device having a physical unclonable function. The device includes an integrated circuit having a semiconducting material in at least one via in a backend of the integrated circuit. The present disclosure also relates to a method for manufacturing a secure device having a physical unclonable function. The method includes providing an integrated circuit and adding a semiconducting material to at least one via in a backend of the integrated circuit. In some instances a property of the semiconducting material in the at least one via is measured to derive a signature.
摘要翻译：本公开涉及具有物理不可克隆功能的安全装置。该器件包括在集成电路的后端中的至少一个通孔中具有半导体材料的集成电路。本公开还涉及一种用于制造具有物理不可克隆功能的安全装置的方法。该方法包括提供集成电路并将集成电路的后端中的至少一个通孔添加半导体材料。在一些情况下，测量至少一个通孔中的半导体材料的特性以导出签名。

7. 发明申请

US20120132913A1 III-V Compound Semiconductor Material Passivation With Crystalline Interlayer 有权
标题翻译： III-V复合半导体材料钝化与结晶中间层
公开(公告)号：US20120132913A1
公开(公告)日：2012-05-31
申请号：US12955203
申请日：2010-11-29
申请人： Kuen-Ting Shiu , Dechao Guo , Shu-Jen Han , Edward W. Kiewra , Masaharu Kobayashi
发明人： Kuen-Ting Shiu , Dechao Guo , Shu-Jen Han , Edward W. Kiewra , Masaharu Kobayashi
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/0603 , H01L21/28158 , H01L21/28264 , H01L29/517 , H01L29/66522 , H01L29/78 , H01L29/7833
摘要： The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure.
摘要翻译：本公开通过在单晶III-V化合物半导体材料层的上表面上提供薄的晶体中间层来减少并且在一些情况下消除III-V族化合物半导体材料中的界面态的密度，以保护单晶III-V化合物半导体材料层的结晶度单晶III-V化合物半导体材料层的表面原子在进一步处理结构之前。

8. 发明授权

US07964896B2 Buried channel MOSFET using III-V compound semiconductors and high k gate dielectrics 有权
标题翻译：使用III-V复合半导体和高k栅极电介质的掩埋沟道MOSFET
公开(公告)号：US07964896B2
公开(公告)日：2011-06-21
申请号：US12180927
申请日：2008-07-28
申请人： Edward W. Kiewra , Steven J. Koester , Devendra K. Sadana , Ghavam Shahidi , Yanning Sun
发明人： Edward W. Kiewra , Steven J. Koester , Devendra K. Sadana , Ghavam Shahidi , Yanning Sun
IPC分类号： H01L29/66
CPC分类号： H01L29/7787 , H01L29/66462
摘要： A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.
摘要翻译：一种含半导体的异质结构，包括III-V族化合物半导体缓冲层，III-V族化合物半导体沟道层，III-V族化合物半导体阻挡层和任选的，但优选的III-V族化合物提供半导体盖层。阻挡层可以是掺杂的，或者优选地是未掺杂的。 III-V族化合物半导体缓冲层和III-V族化合物半导体阻挡层由具有比III-V化合物半导体沟道层宽的带隙的材料构成。由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，所以载流子在特定栅极偏置范围内被限制在沟道层。本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。

9. 发明授权

US06486526B1 Crack stop between neighboring fuses for protection from fuse blow damage 有权
标题翻译：相邻保险丝之间的断裂停止保护熔断器损坏
公开(公告)号：US06486526B1
公开(公告)日：2002-11-26
申请号：US09223826
申请日：1999-01-04
申请人： Chandrasekhar Narayan , Edward W. Kiewra , Carl J. Radens , Axel C. Brintzinger
发明人： Chandrasekhar Narayan , Edward W. Kiewra , Carl J. Radens , Axel C. Brintzinger
IPC分类号： H01L2900
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A fuse structure in an integrated circuit chip is described that includes an insulated semiconductor substrate; a fuse bank integral to the insulated semiconductor substrate consisting of a plurality of parallel co-planar fuse links; and voids interspersed between each pair of the fuse links, the voids extending beyond a plane defined by the co-planar fuse links. The voids surrounding the spot to be hit by a laser beam during fuse blow operation act as a crack stop to prevent damage to adjacent circuit elements or other fuse links present. By suitably shaping and positioning the voids, a tighter pitch between fuses may be obtained.
摘要翻译：描述了集成电路芯片中的熔丝结构，其包括绝缘半导体衬底; 一个与多个并联的共面熔断体组成的绝缘半导体衬底整体的保险丝组; 并且散布在每对熔丝链之间的空隙，空隙延伸超过由共面熔丝链限定的平面。在保险丝熔断操作期间，由激光束击中的点周围的空隙作为裂纹停止，以防止对存在的相邻电路元件或其它熔断体的损坏。通过适当地定形和定位空隙，可以获得保险丝之间更紧密的间距。

10. 发明申请

US20120326212A1 HIGH k GATE STACK ON III-V COMPOUND SEMICONDUCTORS 有权
标题翻译： III-V复合半导体的高k栅极堆叠
公开(公告)号：US20120326212A1
公开(公告)日：2012-12-27
申请号：US13607741
申请日：2012-09-09
申请人： Jean Fompeyrine , Edward W. Kiewra , Steven J. Koester , Devendra K. Sadana , David J. Webb
发明人： Jean Fompeyrine , Edward W. Kiewra , Steven J. Koester , Devendra K. Sadana , David J. Webb
IPC分类号： H01L29/267 , H01L21/20 , H01L21/336 , H01L21/324
CPC分类号： H01L21/3205 , H01L21/02148 , H01L21/02181 , H01L21/02271 , H01L21/28158 , H01L21/3145 , H01L21/31645 , H01L21/32051 , H01L29/513 , H01L29/518 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a high k gate stack on a surface of a III-V compound semiconductor, such GaAs, is provided. The method includes subjecting a III-V compound semiconductor material to a precleaning process which removes native oxides from a surface of the III-V compound semiconductor material; forming a semiconductor, e.g., amorphous Si, layer in-situ on the cleaned surface of the III-V compound semiconductor material; and forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the semiconducting layer. In some embodiments, the semiconducting layer is partially or completely converted into a layer including at least a surface layer that is comprised of AOxNy prior to forming the dielectric material. In accordance with the present invention, A is a semiconducting material, preferably Si, x is 0 to 1, y is 0 to 1 and x and y are both not zero.
摘要翻译：提供了在III-V族化合物半导体的这种GaAs的表面上形成高k栅极堆叠的方法。该方法包括使III-V族化合物半导体材料进行从III-V族化合物半导体材料的表面除去天然氧化物的预清洗工艺; 在III-V族化合物半导体材料的清洁表面上原位形成半导体，例如非晶Si层; 以及在所述半导体层上形成介电常数大于二氧化硅的电介质材料。在一些实施例中，半导体层在形成电介质材料之前部分地或完全地转变成包括至少由AOxNy构成的表面层的层。根据本发明，A是半导体材料，优选Si，x为0至1，y为0至1，x和y都不为零。

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