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    • 2. 发明授权
    • Solder material lining a cover wafer attached to wafer substrate
    • 焊接材料衬在附着于晶片衬底的盖子晶片上
    • US08039950B2
    • 2011-10-18
    • US12092892
    • 2006-11-08
    • Marten OldsenWolfgang ReinertPeter Merz
    • Marten OldsenWolfgang ReinertPeter Merz
    • H01L23/48H01L21/30
    • B81C1/00269Y10T428/23
    • The invention relates to a cover wafer with a core and with an inside, whereby the inside has one or more annular outer areas, (an) annular area(s), which inwardly adjoin(s) the outer area(s), and has (a) inner area(s), and to a component cover with only one annular outer area on its inside. The invention is characterized in that at least area(s) has/have a buffer layer, which has a wetting angle of 265° C. to 450° C. The invention also relates to a component cover having one of the areas which has said buffer layer in a comparable manner. The invention additionally relates to a wafer component or to a component, which can be inserted using microsystem technology and which has a cover wafer or component cover applied with the aid of a solder material, and to a method for the production thereof.
    • 本发明涉及一种具有芯部并具有内部的覆盖晶片,由此内部具有一个或多个环形外部区域(一个)环形区域,该环形区域向内邻接外部区域,并具有 (a)内部区域和内部仅具有一个环形外部区域的部件盖。 本发明的特征在于,至少一个或多个区域具有缓冲层,其对于在> 265℃至450℃范围内熔化的金属共晶溶液具有<35°的润湿角度。 本发明还涉及具有可比较的方式具有所述缓冲层的区域之一的部件盖。 本发明还涉及可以使用微系统技术插入的晶片组件或组件,并且其具有借助于焊料材料应用的覆盖晶片或组件盖以及其制造方法。
    • 5. 发明申请
    • Cover Wafer or Component Cover, Wafer Part, or Component That Can Be Inserted Using Microsystems Technology, and Soldering Method for Connecting Corresponding Wafer or Component Parts
    • 可以使用微系统技术插入的盖板或组件盖,晶圆部件或组件,以及连接相应的晶片或组件部件的焊接方法
    • US20080317995A1
    • 2008-12-25
    • US12092892
    • 2006-11-08
    • Marten OldsenWolfgang ReinertPeter Merz
    • Marten OldsenWolfgang ReinertPeter Merz
    • B32B1/00B23K31/02
    • B81C1/00269Y10T428/23
    • The invention relates to a cover wafer with a core (1) and with an inside (7, 10, 11), whereby the inside has one or more annular outer areas (7), (an) annular area(s) (10), which inwardly adjoin(s) the outer area(s), and has (a) inner area(s) (11), and to a component cover with only one annular outer area on its inside. The invention is characterized in that at least area(s) (10) has/have a buffer layer, which has a wetting angle of 265° C. to 450° C. The invention also relates to a component cover having one of the areas (7), (10) and (11), which has said buffer layer in a comparable manner. The invention additionally relates to a wafer component or to a component, which can be inserted using microsystem technology and which has a cover wafer or component cover applied with the aid of the solder material, and to a method for the production thereof.
    • 本发明涉及一种具有芯体(1)并具有内部(7,10,11)的覆盖晶片,由此内部具有一个或多个环形外部区域(7),(a)环形区域(10) ,其内部邻接外部区域,并且具有(a)内部区域(11)以及在其内部仅具有一个环形外部区域的部件盖。 本发明的特征在于,至少一个或多个区域(10)具有缓冲层,对于在> 265℃至450℃范围内熔化的金属共晶溶液具有<35°的润湿角度 本发明还涉及具有区域(7),(10)和(11)中的一个的组件盖,其具有可比较的方式的所述缓冲层。 本发明还涉及可以使用微系统技术插入的晶片组件或组件,并且其具有借助于焊料材料应用的覆盖晶片或组件盖,以及其制造方法。
    • 8. 发明申请
    • Method for Testing the Leakage Rate of Vacuum Capsulated Devices
    • 真空包装设备泄漏率测试方法
    • US20080141759A1
    • 2008-06-19
    • US11792074
    • 2005-11-10
    • Wolfgang ReinertDirk KaehlerPeter Merz
    • Wolfgang ReinertDirk KaehlerPeter Merz
    • G01M3/02
    • G01M3/329G01M3/186G01M3/226
    • The present invention is directed to a method for testing the leakage rate of an encapsulated device comprising the step: bombing the device with a Neon and/or Argon atmosphere using a bombing pressure of at least more than environmental pressure and measuring the quality factor before and after bombing. Preferably, the bombing time is about 10 to 100 hours, and the bombing pressure is 1.5 to 100 bar, more preferably 1.5 to 5 bar and most preferably about 4 bar. With this test, the leakage rate of fine leaks of the device may be determined. This test is helpful in determining statistical surface contaminations or defects caused by wafer processing that affect the seal integrity just enough to cause shorter lifetimes. Further, dicing, die assembly and transfer molding may also introduce physical defects which may be detected with the present method. Finally, the inventive test method may be useful for process optimization: Hermeticity tests are a great help to optimize sealing processes.
    • 本发明涉及一种用于测试包封装置的泄漏率的方法,包括以下步骤:使用至少大于环境压力的轰炸压力,用氖气和/或氩气气氛轰炸该装置,并测量先前的质量因子, 轰炸后 优选地,轰炸时间为约10至100小时,轰炸压力为1.5至100巴,更优选为1.5至5巴,最优选为约4巴。 通过该测试,可以确定装置的微小泄漏的泄漏率。 该测试有助于确定影响密封完整性的晶片处理造成的统计表面污染或缺陷,足以导致更短的寿命。 此外,切割,模具组装和传递模塑也可能引入可用本方法检测的物理缺陷。 最后,本发明的测试方法可能对于工艺优化是有用的:密封性测试对于优化密封过程是非常有帮助的。