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1. 发明授权

US08012823B2 Methods of fabricating stack type capacitors of semiconductor devices 有权
标题翻译：制造半导体器件堆叠型电容器的方法
公开(公告)号：US08012823B2
公开(公告)日：2011-09-06
申请号：US12453582
申请日：2009-05-15
申请人： Han-jin Lim , Jae-young Park , Young-jin Kim , Seok-woo Nam , Bong-hyun Kim , Kyoung-ryul Yoon , Jae-hyoung Choi , Beom-jong Kim
发明人： Han-jin Lim , Jae-young Park , Young-jin Kim , Seok-woo Nam , Bong-hyun Kim , Kyoung-ryul Yoon , Jae-hyoung Choi , Beom-jong Kim
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L28/91 , H01L21/02189 , H01L21/0228 , H01L21/3141 , H01L21/31641
摘要： Provided are methods of fabricating capacitors of semiconductor devices, the methods including: forming a lower electrode on a semiconductor substrate, performing a pre-process operation on the lower electrode for suppressing deterioration of the lower electrode during a process, forming a dielectric layer on the lower electrode using a source gas and an ozone gas, and forming an upper electrode on the dielectric layer, wherein the pre-process operation and the forming of the dielectric layer may be performed in one device capable of atomic layer deposition.
摘要翻译：提供制造半导体器件的电容器的方法，其方法包括：在半导体衬底上形成下电极，在下电极上执行预处理操作，以抑制在工艺期间下电极的劣化，在电极上形成电介质层使用源气体和臭氧气体的下电极，以及在所述电介质层上形成上电极，其中所述电介质层的预处理操作和形成可以在能够进行原子层沉积的一个器件中进行。

2. 发明申请

US20100009508A1 Methods of fabricating stack type capacitors of semiconductor devices 有权
标题翻译：制造半导体器件堆叠型电容器的方法
公开(公告)号：US20100009508A1
公开(公告)日：2010-01-14
申请号：US12453582
申请日：2009-05-15
申请人： Han-jin Lim , Jae-young Park , Young-jin Kim , Seok-woo Nam , Bong-hyun Kim , Kyoung-ryul Yoon , Jae-hyoung Chol , Beom-jong Kim
发明人： Han-jin Lim , Jae-young Park , Young-jin Kim , Seok-woo Nam , Bong-hyun Kim , Kyoung-ryul Yoon , Jae-hyoung Chol , Beom-jong Kim
IPC分类号： H01L21/02
CPC分类号： H01L28/91 , H01L21/02189 , H01L21/0228 , H01L21/3141 , H01L21/31641
摘要： Provided are methods of fabricating capacitors of semiconductor devices, the methods including: forming a lower electrode on a semiconductor substrate, performing a pre-process operation on the lower electrode for suppressing deterioration of the lower electrode during a process, forming a dielectric layer on the lower electrode using a source gas and an ozone gas, and forming an upper electrode on the dielectric layer, wherein the pre-process operation and the forming of the dielectric layer may be performed in one device capable of atomic layer deposition.
摘要翻译：提供制造半导体器件的电容器的方法，其方法包括：在半导体衬底上形成下电极，在下电极上执行预处理操作，以抑制在工艺期间下电极的劣化，在电极上形成电介质层使用源气体和臭氧气体的下电极，以及在所述电介质层上形成上电极，其中所述电介质层的预处理操作和形成可以在能够进行原子层沉积的一个器件中进行。

3. 发明申请

US20050059206A1 Integrated circuit devices having barrier layers between upper electrodes and dielectric layers and methods of fabricating the same 审中-公开
标题翻译：在上电极和电介质层之间具有阻挡层的集成电路器件及其制造方法
公开(公告)号：US20050059206A1
公开(公告)日：2005-03-17
申请号：US10803640
申请日：2004-03-18
申请人： Jung-hee Chung , Jae-hyoung Choi , Yun-jung Lee , Han-jin Lim
发明人： Jung-hee Chung , Jae-hyoung Choi , Yun-jung Lee , Han-jin Lim
IPC分类号： H01L27/108 , H01L21/02 , H01L21/316 , H01L21/3205 , H01L23/522 , H01L21/8242 , H01L29/76
CPC分类号： H01L28/40 , H01L21/31604 , H01L21/31645 , H01L21/32051 , H01L23/5223 , H01L28/56 , H01L28/65 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit devices are provided including an integrated circuit substrate and a capacitor on the integrated circuit substrate. The capacitor includes a lower electrode on the integrated circuit substrate, a dielectric layer on the lower electrode and an upper electrode on the dielectric layer. A barrier layer is provided between the dielectric layer and the upper electrode. The barrier layer includes titanium oxide. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译：提供集成电路器件，其包括集成电路衬底和集成电路衬底上的电容器。电容器包括集成电路基板上的下电极，下电极上的电介质层和电介质层上的上电极。在电介质层和上电极之间设置阻挡层。阻挡层包括氧化钛。还提供了制造集成电路器件的相关方法。

4. 发明授权

US07034350B2 Capacitors including a cavity containing a buried layer 有权
标题翻译：电容器包括一个包含掩埋层的空腔
公开(公告)号：US07034350B2
公开(公告)日：2006-04-25
申请号：US10795020
申请日：2004-03-05
申请人： Suk-jin Chung , Wan-don Kim , Cha-young Yoo , Kwang-hee Lee , Han-jin Lim , Jin-il Lee
发明人： Suk-jin Chung , Wan-don Kim , Cha-young Yoo , Kwang-hee Lee , Han-jin Lim , Jin-il Lee
IPC分类号： H01L27/108
CPC分类号： H01L28/65 , H01L27/10852 , H01L28/91
摘要： Capacitors include an integrated circuit (semiconductor) substrate and an interlayer dielectric disposed on the integrated circuit substrate and including a metal plug therein. A lower electrode is disposed on the interlayer dielectric and contacting the metal plug. The lower electrode includes a cavity therein and a buried layer in the cavity. The buried layer is an oxygen absorbing material. A dielectric layer disposed on the lower electrode and an upper electrode is disposed on the dielectric layer. The lower electrode may be a noble metal layer. The buried layer may fill in the cavity and may not contain oxygen (O2) when initially formed.
摘要翻译：电容器包括集成电路（半导体）基板和布置在集成电路基板上并且在其中包括金属插塞的层间电介质。下部电极设置在层间电介质上并接触金属插塞。下电极在其中包括空腔，并且在腔中包括掩埋层。掩埋层是吸氧材料。设置在下电极上的电介质层和上电极设置在电介质层上。下电极可以是贵金属层。当初始形成时，掩埋层可以填充空腔并且可以不含有氧（O 2 2 N）。

5. 发明授权

US07049232B2 Methods for forming ruthenium films with β-diketone containing ruthenium complexes and method for manufacturing metal-insulator-metal capacitor using the same 有权
公开(公告)号：US07049232B2
公开(公告)日：2006-05-23
申请号：US10657596
申请日：2003-09-08
申请人： Kwang-hee Lee , Cha-young Yoo , Han-jin Lim , Sung-tae Kim , Suk-jin Chung , Wan-don Kim , Jung-hee Chung , Jin-il Lee
发明人： Kwang-hee Lee , Cha-young Yoo , Han-jin Lim , Sung-tae Kim , Suk-jin Chung , Wan-don Kim , Jung-hee Chung , Jin-il Lee
IPC分类号： H01L21/44
CPC分类号： C23C16/18 , H01L21/28556 , H01L27/10852 , H01L27/11502 , H01L27/11507 , H01L28/65
摘要： Provided are 1) a method for forming a ruthenium film under a single process condition, whereby high adhesion of the ruthenium film to a lower layer is maintained, and 2) a method for manufacturing an metal-insulator-metal (MIM) capacitor using the ruthenium film forming method. The method for forming a ruthenium film includes supplying bis(isoheptane-2,4-dionato)norbornadiene ruthenium at a flow rate of 0.2–1 ccm and oxygen at a flow rate of 20–60 sccm, and depositing the ruthenium film at a temperature of 330–430° C. under a pressure of 0.5–5 Torr using chemical vapor deposition (CVD).

6. 发明授权

US06284589B1 Method of fabricating concave capacitor including adhesion spacer 有权
标题翻译：制造包含粘合间隔物的凹电容器的方法
公开(公告)号：US06284589B1
公开(公告)日：2001-09-04
申请号：US09392906
申请日：1999-09-09
申请人： Han-jin Lim , Byoung-taek Lee
发明人： Han-jin Lim , Byoung-taek Lee
IPC分类号： H01L218242
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/76844 , H01L27/10855 , H01L28/55 , H01L28/91
摘要： In accordance with the present invention, a method of fabricating a concave capacitor is provided. The concave capacitor of the present invention includes an adhesion spacer is formed between a concave pattern comprising an interlayer dielectric film and a lower electrode is provided. In the concave capacitor fabricating method, an interlayer dielectric film is formal semiconductor substrate. A concave pattern having a storage node e exposing part of the upper surface of the semiconductor substrate is form by patterning the interlayer dielectric film. An adhesion spacer is formed on t sidewall of the concave pattern exposed by the storage node hole. A lower electrode to cover the adhesion spacer and the upper surface of the semiconductor substrate exposed by the storage node hole is formed in the storage node hole
摘要翻译：根据本发明，提供一种制造凹电容器的方法。本发明的凹电容器包括在包括层间绝缘膜和下电极的凹形图案之间形成粘合间隔物。在凹电容器制造方法中，层间电介质膜是正式的半导体衬底。具有露出半导体衬底的上表面的部分的存储节点e的凹形图案是通过图案化层间绝缘膜而形成的。在由存储节点孔露出的凹形图案的t侧壁上形成粘合间隔物。在存储节点孔中形成有用于覆盖粘合间隔物的下电极和由存储节点孔露出的半导体衬底的上表面

7. 发明授权

US06649502B2 Methods of forming multilayer dielectric regions using varied deposition parameters 失效
公开(公告)号：US06649502B2
公开(公告)日：2003-11-18
申请号：US09859168
申请日：2001-05-16
申请人： Cha-young Yoo , Han-jin Lim , Wan-don Kim , Se-jin Lee , Soon-yeon Park , Yong-kuk Jeong , Han-mei Choi , Gyung-hoon Hong , Seok-jun Won
发明人： Cha-young Yoo , Han-jin Lim , Wan-don Kim , Se-jin Lee , Soon-yeon Park , Yong-kuk Jeong , Han-mei Choi , Gyung-hoon Hong , Seok-jun Won
IPC分类号： H01L213205
CPC分类号： H01L21/02183 , C23C16/405 , C23C16/45557 , H01L21/02337 , H01L21/02348 , H01L21/31604 , H01L28/40 , H01L28/56
摘要： A dielectric region for a device such as a memory cell capacitor is formed by depositing a metal oxide, such as tantalum oxide, on a substrate at a first deposition rate in a first atmosphere maintained within a first temperature range and a first pressure range that produce a first tantalum oxide layer with a desirable step coverage. Metal oxide is subsequently deposited on the first metal oxide layer in a second atmosphere maintained within a second temperature range and a second pressure range that produce a second deposition rate greater than the first deposition rate to form a second tantalum oxide layer on the first tantalum oxide layer. For example, the first atmosphere may be maintained at a temperature in a range from about 350° C. to about 460° C. and a pressure in a range from about 0.01 Torr to about 2.0 Torr during formation of a first tantalum oxide layer, and the second atmosphere may be maintained at a temperature in a range from about 400° C. to about 500° C. and a pressure in a range from about 0.1 Torr to about 10.0 Torr during formation of a second tantalum oxide layer.

8. 发明授权

US07091102B2 Methods of forming integrated circuit devices having a capacitor with a hydrogen barrier spacer on a sidewall thereof and integrated circuit devices formed thereby 有权
标题翻译：在其侧壁上形成具有氢阻挡间隔物的电容器的集成电路器件的方法和由此形成的集成电路器件
公开(公告)号：US07091102B2
公开(公告)日：2006-08-15
申请号：US10742727
申请日：2003-12-19
申请人： Han-jin Lim , Kwang-hee Lee , Suk-jin Chung , Cha-young Yoo , Wan-don Kim , Jin-il Lee
发明人： Han-jin Lim , Kwang-hee Lee , Suk-jin Chung , Cha-young Yoo , Wan-don Kim , Jin-il Lee
IPC分类号： H01L21/20 , H01L27/108
CPC分类号： H01L28/40 , H01L21/3141 , H01L27/10814 , H01L27/10852 , H01L27/11502 , H01L27/11507 , H01L28/57 , H01L28/65 , H01L28/91 , H01L28/92
摘要： An integrated circuit device is formed by providing a substrate and forming a capacitor on the substrate. The capacitor includes a lower electrode disposed on the substrate, a dielectric layer on the lower electrode, and an upper electrode on the dielectric. A hydrogen barrier insulation layer is formed on the upper electrode and a hydrogen barrier spacer is formed on a sidewall of the capacitor.
摘要翻译：通过提供衬底并在衬底上形成电容器形成集成电路器件。电容器包括设置在基板上的下电极，下电极上的电介质层和电介质上的上电极。在上电极上形成氢阻隔绝缘层，在电容器的侧壁上形成氢阻挡隔离层。

9. 发明申请

US20060138511A1 Methods of manufacturing a capacitor including a cavity containing a buried layer 审中-公开
标题翻译：制造包括埋藏层的空腔的电容器的方法
公开(公告)号：US20060138511A1
公开(公告)日：2006-06-29
申请号：US11360070
申请日：2006-02-23
申请人： Suk-jin Chung , Wan-don Kim , Cha-young Yoo , Kwang-hee Lee , Han-jin Lim , Jin-il Lee
发明人： Suk-jin Chung , Wan-don Kim , Cha-young Yoo , Kwang-hee Lee , Han-jin Lim , Jin-il Lee
IPC分类号： H01L29/94
CPC分类号： H01L28/65 , H01L27/10852 , H01L28/91
摘要： Capacitors include an integrated circuit (semiconductor) substrate and an interlayer dielectric disposed on the integrated circuit substrate and including a metal plug therein. A lower electrode is disposed on the interlayer dielectric and contacting the metal plug. The lower electrode includes a cavity therein and a buried layer in the cavity. The buried layer is an oxygen absorbing material. A dielectric layer disposed on the lower electrode and an upper electrode is disposed on the dielectric layer. The lower electrode may be a noble metal layer. The buried layer may fill in the cavity and may not contain oxygen (O2) when initially formed.
摘要翻译：电容器包括集成电路（半导体）基板和布置在集成电路基板上并且在其中包括金属插塞的层间电介质。下部电极设置在层间电介质上并接触金属插塞。下电极在其中包括空腔，并且在腔中包括掩埋层。掩埋层是吸氧材料。设置在下电极上的电介质层和上电极设置在电介质层上。下电极可以是贵金属层。当初始形成时，掩埋层可以填充空腔并且可以不含有氧（O 2 2 N）。

10. 发明授权

US06743678B2 Methods for manufacturing semiconductor memory devices 有权
标题翻译：制造半导体存储器件的方法
公开(公告)号：US06743678B2
公开(公告)日：2004-06-01
申请号：US10424959
申请日：2003-04-28
申请人： Kwang-hee Lee , Sung-tae Kim , Cha-young Yoo , Han-jin Lim , Wan-don Kim , Se-hoon Oh
发明人： Kwang-hee Lee , Sung-tae Kim , Cha-young Yoo , Han-jin Lim , Wan-don Kim , Se-hoon Oh
IPC分类号： H01L21336
CPC分类号： H01L28/75 , H01L28/65
摘要： A lower electrode is formed from a first metal on a semiconductor substrate. Atoms of a second metal, that is different than the first metal, are diffused into the lower electrode. A dielectric layer is formed on the lower electrode, and an upper electrode is formed on the dielectric layer. Diffusion of second metal atoms into the lower electrode may reduce or prevent crystal grain growth and agglomeration on a surface of the lower electrode during a subsequent high temperature process.
摘要翻译：下电极由半导体衬底上的第一金属形成。与第一金属不同的第二金属的原子被扩散到下电极中。在下电极上形成介电层，在电介质层上形成上电极。在随后的高温过程中，第二金属原子向下电极的扩散可以减少或防止下电极表面上的晶粒生长和结块。

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