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1. 发明申请

US20090047791A1 SEMICONDUCTOR ETCHING METHODS 审中-公开
标题翻译：半导体蚀刻方法
公开(公告)号：US20090047791A1
公开(公告)日：2009-02-19
申请号：US11839681
申请日：2007-08-16
申请人： David M. Dobuzinsky , Johnathan E. Faltermeier , Munir D. Naeem , William C. Wille , Richard S. Wise
发明人： David M. Dobuzinsky , Johnathan E. Faltermeier , Munir D. Naeem , William C. Wille , Richard S. Wise
IPC分类号： H01L21/302
CPC分类号： H01L21/3081 , H01L27/10844 , H01L27/11
摘要： A method of etching semiconductor structures is disclosed. The method may include etching an SRAM portion of a semiconductor device, the method comprising: providing a silicon substrate layer, a nitride layer thereover, an optical dispersive layer over the nitride layer, and a silicon anti-reflective coating layer thereover; etching the silicon anti-reflective coating layer using an image layer; removing the image layer; etching the optical dispersive layer while removing the silicon anti-reflective coating layer; etching the optical dispersive layer and the nitride layer simultaneously; and etching the optical dispersive layer, the nitride layer, and the silicon substrate simultaneously.
摘要翻译：公开了蚀刻半导体结构的方法。该方法可以包括蚀刻半导体器件的SRAM部分，该方法包括：提供硅衬底层，其上的氮化物层，氮化物层上的光学色散层和其上的硅抗反射涂层; 使用图像层蚀刻硅抗反射涂层; 去除图像层; 在去除硅抗反射涂层的同时蚀刻光学色散层; 同时蚀刻光学色散层和氮化物层; 并同时蚀刻光学色散层，氮化物层和硅衬底。

2. 发明申请

US20090104776A1 METHODS FOR FORMING NESTED AND ISOLATED LINES IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：在半导体器件中形成嵌套和隔离线的方法
公开(公告)号：US20090104776A1
公开(公告)日：2009-04-23
申请号：US11874392
申请日：2007-10-18
申请人： David M. Dobuzinsky , Johnathan E. Faltermeier , Naoyoshi Kusaba , Joyce C. Liu , Munir D. Naeem , Siddhartha Panda , Richard S. Wise , Hongwen Yan
发明人： David M. Dobuzinsky , Johnathan E. Faltermeier , Naoyoshi Kusaba , Joyce C. Liu , Munir D. Naeem , Siddhartha Panda , Richard S. Wise , Hongwen Yan
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/0337 , H01L21/0338 , H01L21/32137 , H01L21/32139
摘要： A method for forming lines for semiconductor devices including, depositing a shallow trench isolation (STI) film stack on a silicon substrate, depositing a layer of polysilicon on the STI film stack, depositing a layer of antireflective coating on the layer of polysilicon, developing a phototoresist on the antireflective coating, wherein the photoresist defines a line, etching the layer of antireflective coating and the layer of polysilicon using RIE with a low bias power, removing the photoresist, removing the layer of antireflective coating, etching the STI film stack to form the line, wherein the layer of polysilicon further defines the line.
摘要翻译：一种用于形成用于半导体器件的线的方法，包括：在硅衬底上沉积浅沟槽隔离（STI）膜堆叠，在所述STI膜堆叠上沉积多晶硅层，在所述多晶硅层上沉积一层抗反射涂层，在抗反射涂层上光致抗蚀剂，其中光致抗蚀剂限定线，使用具有低偏压功率的RIE蚀刻抗反射涂层和多晶硅层，去除光致抗蚀剂，去除抗反射涂层，蚀刻STI膜叠层以形成所述线，其中所述多晶硅层进一步限定所述线。

3. 发明授权

US6093281A Baffle plate design for decreasing conductance lost during precipitation of polymer precursors in plasma etching chambers 失效
标题翻译：挡板设计，用于降低等离子体蚀刻室中聚合物前体沉淀过程中的电导损失
公开(公告)号：US6093281A
公开(公告)日：2000-07-25
申请号：US31232
申请日：1998-02-26
申请人： Richard S. Wise , David M. Dobuzinsky , William C. Wille
发明人： Richard S. Wise , David M. Dobuzinsky , William C. Wille
IPC分类号： C23C16/44 , H01J37/32 , C23C16/00
CPC分类号： H01J37/32834 , C23C16/4412 , H01J37/3244
摘要： A baffle plate for semiconductor processing apparatus. The baffle plate includes a plurality of slits. A plurality of fins are located between adjacent slits. The fins have varying heights and a supporting portion interconnects the fins.
摘要翻译：一种用于半导体处理装置的挡板。挡板包括多个狭缝。多个翅片位于相邻狭缝之间。翅片具有不同的高度，并且支撑部分互连翅片。

4. 发明授权

US06656375B1 Selective nitride: oxide anisotropic etch process 失效
标题翻译：选择性氮化物：氧化物各向异性蚀刻工艺
公开(公告)号：US06656375B1
公开(公告)日：2003-12-02
申请号：US09014806
申请日：1998-01-28
申请人： Michael D. Armacost , David M. Dobuzinsky , John C. Malinowski , Hung Y. Ng , Richard S. Wise , Chienfan Yu
发明人： Michael D. Armacost , David M. Dobuzinsky , John C. Malinowski , Hung Y. Ng , Richard S. Wise , Chienfan Yu
IPC分类号： C23F100
CPC分类号： H01L21/31116
摘要： An anisotropic etching process for a nitride layer of a substrate, the process comprising using an etchant gas which comprises a hydrogen-rich fluorohydrocarbon, an oxidant and a carbon source. The hydrogen-rich fluorohydrocarbon is preferably one of CH3F or CH2F2, the carbon source is preferably one of CO2 or CO, and the oxidant is preferably O2. The fluorohydrocarbon is preferably present in the gas at approximately 7%-35% by volume, the oxidant is preferably present in the gas at approximately 1%-35% by volume, and the carbon source is preferably present in the gas at approximately 30%-92%.
摘要翻译：用于衬底的氮化物层的各向异性蚀刻工艺，该方法包括使用包含富氢氟代烃，氧化剂和碳源的蚀刻剂气体。富氢氟烃优选为CH 3 F或CH 2 F 2之一，碳源优选为CO 2或CO之一，氧化剂优选为O 2。氟烃优选以约7％-35体积％存在于气体中，氧化剂优选以约1％-35％体积的比例存在于气体中，并且碳源优选以约30％的比例存在于气体中， -92％。

5. 发明申请

US20130200471A1 ALIGNMENT TOLERANT SEMICONDUCTOR CONTACT AND METHOD 有权
标题翻译：对准耐磨半导体接触和方法
公开(公告)号：US20130200471A1
公开(公告)日：2013-08-08
申请号：US13364976
申请日：2012-02-02
申请人： André P. Labonté , Richard S. Wise
发明人： André P. Labonté , Richard S. Wise
IPC分类号： H01L29/78 , H01L21/768
CPC分类号： H01L21/28247 , H01L21/76814 , H01L21/76888 , H01L21/76897 , H01L29/66545
摘要： An alignment tolerant electrical contact is formed by providing a substrate on which is a first electrically conductive region (e.g., a MOSFET gate) having an upper surface, the first electrically conductive region being laterally bounded by a first dielectric region, applying a mask having an opening extending partly over a contact region (e.g., for the MOSFET source or drain) on the substrate and over a part of the upper surface, forming a passage through the first dielectric region extending to the contact region and the part of the upper surface, thereby exposing the contact region and the part of the upper surface, converting the part of the upper surface to a second dielectric region and filling the opening with a conductor making electrical contact with the contact region but electrically insulated from the electrically conductive region by the second dielectric region.
摘要翻译：通过提供其上具有上表面的第一导电区域（例如，MOSFET栅极）的衬底来形成对准容限的电接触，所述第一导电区域被第一介电区域横向界定，施加具有部分地覆盖在衬底上并在上表面的一部分上的接触区域（例如，用于MOSFET源极或漏极）上的开口，形成通过延伸到接触区域和上表面的部分的第一介电区域的通道，从而暴露接触区域和上表面的一部分，将上表面的一部分转换成第二电介质区域，并且用与接触区域电接触但与导电区域电绝缘的导体填充开口电介质区域。

6. 发明授权

US08492280B1 Method for simultaneously forming features of different depths in a semiconductor substrate 失效
标题翻译：同时形成半导体衬底中不同深度的特征的方法
公开(公告)号：US08492280B1
公开(公告)日：2013-07-23
申请号：US13465050
申请日：2012-05-07
申请人： Habib Hichri , Xi Li , Richard S. Wise
发明人： Habib Hichri , Xi Li , Richard S. Wise
IPC分类号： H01L21/311
CPC分类号： H01L21/3065 , H01L21/76229 , H01L21/84 , H01L27/1087 , H01L29/66181
摘要： Embodiments of the invention may include first providing a stack of layers including a semiconductor substrate, a buried oxide layer on the semiconductor substrate, a semiconductor-on-insulator layer on the buried-oxide layer, a nitride layer on the semiconductor-on-insulator layer, and a silicon oxide layer on the nitride layer. A first opening and second opening with a smaller cross-sectional area than the first opening are then formed in the silicon oxide layer, the nitride layer, the semiconductor-on-insulator layer, and the buried-oxide layer. The first opening and the second opening are then etched with a first etching gas. The first opening and the second opening are then etched with a second etching gas, which includes the first etching gas and a halogenated silicon compound, for example, silicon tetrafluoride or silicon tetrachloride. In one embodiment, the first etching gas includes hydrogen bromide, nitrogen trifluoride, and oxygen.
摘要翻译：本发明的实施例可以包括首先提供包括半导体衬底，半导体衬底上的掩埋氧化物层，掩埋氧化物层上的绝缘体上半导体层，绝缘体上半导体上的氮化物层层和氮化物层上的氧化硅层。然后在氧化硅层，氮化物层，绝缘体上半导体层和掩埋氧化物层上形成具有比第一开口更小的横截面面积的第一开口和第二开口。然后用第一蚀刻气体蚀刻第一开口和第二开口。然后用第二蚀刻气体蚀刻第一开口和第二开口，第二蚀刻气体包括第一蚀刻气体和卤化硅化合物，例如四氟化硅或四氯化硅。在一个实施方案中，第一蚀刻气体包括溴化氢，三氟化氮和氧。

7. 发明申请

US20120139061A1 Self-Aligned Contact For Replacement Gate Devices 有权
标题翻译：用于替代门装置的自对准触点
公开(公告)号：US20120139061A1
公开(公告)日：2012-06-07
申请号：US12958607
申请日：2010-12-02
申请人： Ravikumar Ramachandran , Ying Li , Richard S. Wise
发明人： Ravikumar Ramachandran , Ying Li , Richard S. Wise
IPC分类号： H01L29/772 , H01L21/283
CPC分类号： H01L29/78 , H01L21/76895 , H01L21/76897 , H01L21/823842 , H01L21/823871 , H01L29/49 , H01L29/51 , H01L29/66545 , H01L29/66606 , H01L29/7833 , H01L29/7843
摘要： A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure.
摘要翻译：替代栅极堆叠的导电顶表面通过至少一个蚀刻相对于平坦化介电层的顶表面凹陷。介电覆盖层沉积在平坦化电介质层和替代栅极堆叠的顶表面上，使得替代栅极堆叠上的介电顶盖层的一部分的顶表面相对于上述电介质层的另一部分垂直凹陷平坦化介电层。电介质覆盖层的垂直偏移可以与选择性通孔蚀刻工艺结合使用以形成自对准接触结构。

8. 发明授权

US07943457B2 Dual metal and dual dielectric integration for metal high-k FETs 有权
标题翻译：金属高k FET的双金属和双电介质集成
公开(公告)号：US07943457B2
公开(公告)日：2011-05-17
申请号：US12423236
申请日：2009-04-14
申请人： Michael P. Chudzik , Wiliam K. Henson , Rashmi Jha , Yue Liang , Ravikumar Ramachandran , Richard S. Wise
发明人： Michael P. Chudzik , Wiliam K. Henson , Rashmi Jha , Yue Liang , Ravikumar Ramachandran , Richard S. Wise
IPC分类号： H01L21/336
CPC分类号： H01L29/517 , H01L21/28185 , H01L21/823842 , H01L21/823857 , H01L29/49 , H01L29/7833
摘要： The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.
摘要翻译：在一个实施例中，本发明提供一种形成半导体器件的方法，该半导体器件包括提供包括第一导电类型区域和第二导电类型区域的衬底; 在所述基板的第一导电类型区域和所述第二导电类型区域之上形成包括栅极电介质的栅极堆叠和覆盖所述高k栅极电介质的第一金属栅极导体; 去除存在于第一导电类型区域中的第一金属栅极导体的一部分以暴露存在于第一导电类型区域中的栅极电介质; 将氮基等离子体施加到所述基板，其中所述氮基等离子体氮化存在于所述第一导电类型区域中的所述栅极电介质，并且氮化所述第二导电类型区域中存在的所述第一金属栅极导体; 以及形成覆盖存在于第一导电类型区域中的至少栅极电介质的第二金属栅极导体。

9. 发明申请

US20110104426A1 EDGE PROTECTION SEAL FOR BONDED SUBSTRATES 失效
标题翻译：贴边基板的边缘保护密封
公开(公告)号：US20110104426A1
公开(公告)日：2011-05-05
申请号：US12608363
申请日：2009-10-29
申请人： Mukta G. Farooq , Emily Kinser , Richard S. Wise , Hakeem B.S. Akinmade-Yusuff
发明人： Mukta G. Farooq , Emily Kinser , Richard S. Wise , Hakeem B.S. Akinmade-Yusuff
IPC分类号： B32B1/04 , B32B38/00
CPC分类号： H01L21/02263 , H01L21/187 , H01L21/76898 , H01L25/074 , H01L25/50 , H01L2924/0002 , H01L2924/00
摘要： A dielectric material layer is deposited on exposed surfaces of a bonded structure that includes a first substrate and a second substrate. The dielectric material layer is formed on an exposed planar surface of a second substrate and the entirety of peripheral sidewalls of the first and second substrates. The dielectric material layer can be formed by chemical vapor deposition, atomic layer deposition, or plasma induced deposition. Further, the dielectric material layer seals the entire periphery of the interface between the first and second substrates. If a planar portion of the dielectric material layer can be removed by planarization to facilitate thinning of the bonded structure, the remaining portion of the dielectric material layer can form a dielectric ring.
摘要翻译：介电材料层沉积在包括第一基板和第二基板的接合结构的暴露表面上。介电材料层形成在第二基板的暴露的平坦表面和第一和第二基板的整个周边侧壁上。介电材料层可以通过化学气相沉积，原子层沉积或等离子体诱导沉积形成。此外，介电材料层密封第一和第二基板之间的界面的整个周边。如果可以通过平坦化去除电介质材料层的平面部分以便于键合结构的薄化，则介电材料层的剩余部分可以形成介电环。

10. 发明申请

US20100029082A1 METHOD AND APPARATUS FOR ANGULAR HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION 有权
标题翻译：用于高密度等离子体化学蒸气沉积的方法和装置
公开(公告)号：US20100029082A1
公开(公告)日：2010-02-04
申请号：US12185339
申请日：2008-08-04
申请人： Daewon Yang , Kangguo Cheng , Pavel Smetana , Richard S. Wise , Keith Kwong Hon Wong
发明人： Daewon Yang , Kangguo Cheng , Pavel Smetana , Richard S. Wise , Keith Kwong Hon Wong
IPC分类号： H01L21/311 , C23C16/00
CPC分类号： C23C16/507 , C23C16/345 , C23C16/402 , C23C16/45578 , C23C16/4586 , C23C16/56 , H01J37/20 , H01J37/321 , H01J2237/20207 , H01J2237/3323 , H01L21/31608 , H01L21/3185 , H01L27/10867
摘要： Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.
摘要翻译：通过形成多个STI沟槽与FET结合形成浅沟槽电容器; 对于FET，在第一和第二STI沟槽之间注入具有第一极性的第一单元阱; 对于电容器，在第三个STI沟槽的区域中注入具有第二极性的第二单元阱; 从第三STI沟槽去除电介质材料; 形成具有位于所述STI沟槽的所述第一和第二STI沟槽之间的第一部分和位于所述第三沟槽中并延伸到所述第三沟槽中的第二部分的栅极堆叠; 并且执行与第二单元阱相同极性的源极/漏极注入，从而在第一单元阱中形成FET，以及在第二单元阱中形成电容器。第二极性可以与第一极性相反。额外的植入物可以减少第二细胞中的ESR。

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