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1. 发明申请

US20090038548A1 SUBSTRATE TREATING APPARATUS AND TREATING GAS EMITTING MECHANISM 审中-公开
标题翻译：基板处理装置和处理排气机理
公开(公告)号：US20090038548A1
公开(公告)日：2009-02-12
申请号：US12162132
申请日：2007-03-30
申请人： Hachishiro Iizuka , Tomoyuki Sakoda , Naofumi Oda , Norihiko Tsuji , Masayuki Moroi
发明人： Hachishiro Iizuka , Tomoyuki Sakoda , Naofumi Oda , Norihiko Tsuji , Masayuki Moroi
IPC分类号： C23C16/455
CPC分类号： C23C16/4557 , C23C16/409 , C23C16/45565 , C23C16/45574 , H01L21/31691
摘要： A film forming apparatus includes a process chamber 2 configured to accommodate a semiconductor wafer W; a worktable 5 disposed inside the process chamber 2 and configured to place the semiconductor wafer W thereon; a showerhead 40 used as a process gas delivery mechanism disposed to face the worktable 5 and configured to delivery a process gas into the process chamber 2; and an exhaust unit 101 configured to exhaust gas from inside the process chamber 2, wherein the showerhead 40 has a gas passage formed therein for supplying the process gas, and an annular temperature adjusting cell 400 formed therein around the gas passage.
摘要翻译：成膜装置包括：配置成容纳半导体晶片W的处理室2; 设置在处理室2内并被配置为将半导体晶片W放置在其上的工作台5; 用作处理气体输送机构的喷头40，其布置成面对工作台5并且构造成将处理气体输送到处理室2中; 以及排气单元101，被配置为从处理室2内部排出气体，其中喷头40具有形成在其中的用于供给处理气体的气体通道，以及围绕气体通道形成的环形温度调节单元400。

2. 发明申请

US20070022954A1 Gas treatment device and heat readiting method 审中-公开
标题翻译：气体处理装置和热读取方法
公开(公告)号：US20070022954A1
公开(公告)日：2007-02-01
申请号：US10570603
申请日：2004-08-30
申请人： Hachishiro Iizuka , Koichiro Kimura , Kyoko Ikeda , Tomoyuki Sakoda , Akira Yasumuro
发明人： Hachishiro Iizuka , Koichiro Kimura , Kyoko Ikeda , Tomoyuki Sakoda , Akira Yasumuro
IPC分类号： C23F1/00 , C23C16/00
CPC分类号： C23C16/45565 , C23C16/455
摘要： A shower head formed by stacking a shower base, a gas diffusion plate, and a shower plate and supplying material gas and oxidizer gas to a wafer on a loading table through a first gas diffusion part and a second gas diffusion part formed in both faces of the gas diffusion plate, first gas outlets formed in the shower plate and communicating with a first gas diffusion space, and second gas outlets formed in the shower plate and communicating with a second gas diffusion space. A plurality of heat transfer columns fitted closely to the lower surface of the shower base are installed in the first gas diffusion part so that portions therebetween can form the first gas diffusion space, and radiant heat from the loading table is transmitted by the heat transfer columns in the thickness direction of the shower head.
摘要翻译：喷淋头，其通过堆叠淋浴器基座，气体扩散板和喷淋板而形成，并且通过第一气体扩散部和第二气体扩散部将第二气体扩散部和第二气体扩散部供给到装载台上的晶片，所述气体扩散板，形成在所述喷淋板中并与第一气体扩散空间连通的第一气体出口和形成在所述喷淋板中并与第二气体扩散空间连通的第二气体出口。在第一气体扩散部中安装有与淋浴器基座的下表面紧密配合的多个传热塔，使得它们之间的部分可以形成第一气体扩散空间，并且来自装载台的辐射热量通过传热塔在淋浴头的厚度方向上。

3. 发明授权

US07629183B2 Method for manufacturing semiconductor device and computer storage medium 失效
标题翻译：半导体器件和计算机存储介质的制造方法
公开(公告)号：US07629183B2
公开(公告)日：2009-12-08
申请号：US11815868
申请日：2006-06-12
申请人： Kenji Matsumoto , Masayuki Nasu , Tomoyuki Sakoda
发明人： Kenji Matsumoto , Masayuki Nasu , Tomoyuki Sakoda
IPC分类号： H01L21/00 , H01L21/44 , H01L21/8242 , H01L21/8246 , H01L29/76 , H01L29/94 , H01L31/113 , H01L31/119 , H01L31/062
CPC分类号： H01L21/31691 , C23C16/0272 , C23C16/40 , C23C16/409 , C30B25/02 , C30B29/32 , H01L21/02197 , H01L21/02271 , H01L27/11507 , H01L28/55
摘要： A method for fabricating a semiconductor device includes the steps of forming a PbTiOx film having a predominantly (111) orientation on a lower electrode as a nucleation layer by an MOCVD process with a film thickness exceeding 2 nm, and forming a PZT film having a predominantly (111) orientation on the nucleation layer, wherein the step of forming the PbTiOx film is conducted under an oxygen partial pressure of less than 340 Pa.
摘要翻译：一种制造半导体器件的方法包括以下步骤：通过膜厚超过2nm的MOCVD法在下电极上形成主要为（111）取向的PbTiOx膜作为成核层，并形成主要为（111）取向，其中形成PbTiOx膜的步骤在小于340Pa的氧分压下进行。

4. 发明授权

US06485988B2 Hydrogen-free contact etch for ferroelectric capacitor formation 有权
标题翻译：用于铁电电容器形成的无氢接触蚀刻
公开(公告)号：US06485988B2
公开(公告)日：2002-11-26
申请号：US09741650
申请日：2000-12-19
申请人： Shawming Ma , Guoqiang Xing , Rahim Kavari , Scott R. Summerfelt , Tomoyuki Sakoda
发明人： Shawming Ma , Guoqiang Xing , Rahim Kavari , Scott R. Summerfelt , Tomoyuki Sakoda
IPC分类号： H01L2100
CPC分类号： H01L21/31122 , H01L21/32136 , H01L21/76838 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/57 , H01L28/60
摘要： An embodiment of the instant invention is a method of forming a conductive contact to a top electrode (308 and 310 of FIG. 4d) of a ferroelectric capacitor comprised of a bottom electrode (304 of FIG. 4d) situated under the top electrode and a ferroelectric material (306 of FIG. 4d) situated between the top electrode and the bottom electrode, the method comprising the steps of: forming a layer (408 or 312 of FIG. 4) over the top electrode; forming an opening (414 of FIG. 4d) in the layer to expose a portion of the top electrode by etching the opening into the layer using a hydrogen-free etchant; and depositing conductive material (432 of FIG. 4d) in the opening to form an electrical connection with the top electrode.
摘要翻译：本发明的一个实施方案是一种形成导电接触的方法，该导电接触由位于顶部电极下方的底部电极（图4d的304）构成的铁电电容器的顶部电极（图4d的308和310）和铁电材料（图4d的306）位于顶部电极和底部电极之间，该方法包括以下步骤：在顶部电极上形成层（图4的408或312）; 在所述层中形成开口（图4d的414），以通过使用无氢蚀刻剂将所述开口蚀刻到所述层中来暴露所述顶部电极的一部分; 以及将导电材料（图4d的432）沉积在开口中以与顶部电极形成电连接。

5. 发明授权

US06275408B1 Ferroelectric memory and method 有权
标题翻译：铁电记忆和方法
公开(公告)号：US06275408B1
公开(公告)日：2001-08-14
申请号：US09605933
申请日：2000-06-28
申请人： Katsuhiro Aoki , Tomoyuki Sakoda
发明人： Katsuhiro Aoki , Tomoyuki Sakoda
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： Ferroelectric memory with one-capacitor/one-transistor cells and a reference cell with double the capacitance plus a sense amplifier for comparing transient currents in resistors at the sense amplifier inputs. The reference cell includes a diode to prevent reference capacitor polarization switching.
摘要翻译：具有单电容/单晶体管单元的铁电存储器和具有两倍电容的参考电池，以及用于比较读出放大器输入端的电阻中的瞬态电流的读出放大器。参考单元包括用于防止参考电容器偏振切换的二极管。

6. 发明授权

US07674710B2 Method of integrating metal-containing films into semiconductor devices 失效
标题翻译：将含金属膜整合到半导体器件中的方法
公开(公告)号：US07674710B2
公开(公告)日：2010-03-09
申请号：US11561810
申请日：2006-11-20
申请人： Shigeo Ashigaki , Hideaki Yamasaki , Tomoyuki Sakoda , Mikio Suzuki , Genji Nakamura , Gert Leusink
发明人： Shigeo Ashigaki , Hideaki Yamasaki , Tomoyuki Sakoda , Mikio Suzuki , Genji Nakamura , Gert Leusink
IPC分类号： H01L21/4763
CPC分类号： H01L21/28079 , H01L29/4958 , H01L29/513 , H01L29/518
摘要： A method for integrating a metal-containing film in a semiconductor device, for example a gate stack. In one embodiment, the method includes providing a substrate in a process chamber, depositing the tungsten-containing film on the substrate at a first substrate temperature by exposing the substrate to a deposition gas containing a tungsten carbonyl precursor, heat treating the tungsten-containing film at a second substrate temperature greater than the first substrate temperature to remove carbon monoxide gas from the tungsten-containing film, and forming a barrier layer on the heat treated tungsten-containing film. Examples of tungsten-containing films include W, WN, WSi, and WC. Additional embodiments include depositing metal-containing films containing Ni, Mo, Co, Rh, Re, Cr, or Ru from the corresponding metal carbonyl precursors.
摘要翻译：一种用于将含金属膜整合在半导体器件例如栅极堆叠中的方法。在一个实施例中，该方法包括在处理室中提供衬底，通过将衬底暴露于含有羰基钨前体的沉积气体，在第一衬底温度下将含钨膜沉积在衬底上，热处理含钨膜在大于第一衬底温度的第二衬底温度下从含钨膜中除去一氧化碳气体，并在热处理的含钨膜上形成阻挡层。含钨膜的实例包括W，WN，WSi和WC。另外的实施方案包括从相应的金属羰基前体沉积含有Ni，Mo，Co，Rh，Re，Cr或Ru的含金属膜。

7. 发明授权

US06713342B2 FeRAM sidewall diffusion barrier etch 有权
标题翻译： FeRAM侧壁扩散阻挡蚀刻
公开(公告)号：US06713342B2
公开(公告)日：2004-03-30
申请号：US10282759
申请日：2002-10-29
申请人： Francis G. Celii , Scott R. Summerfelt , Tomoyuki Sakoda , Chiu Chi
发明人： Francis G. Celii , Scott R. Summerfelt , Tomoyuki Sakoda , Chiu Chi
IPC分类号： H01L218242
CPC分类号： H01L21/31122 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/75
摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a sidewall diffusion barrier prior to etching the bottom electrode diffusion barrier layer. The sidewall diffusion barrier layer is then etched prior to the bottom electrode diffusion barrier layer. In patterning an AlOx sidewall diffusion barrier layer prior to etching the underlying bottom electrode diffusion barrier layer, the etch chemistry comprises BCl3+Ar. The BCl3 is effective in etching the AlOx with a good selectivity to the underlying nitride hard mask on top of the capacitor stack (e.g., TiAlN) and nitride bottom electrode diffusion barrier (e.g., TiAlON with small oxygen content) between the neighboring capacitor stacks. The Ar may be added to the etch chemistry because the resulting surface (of a top portion of the hard mask and the bottom electrode diffusion barrier) is smoother.
摘要翻译：本发明涉及一种形成FeRAM集成电路的方法，其包括在蚀刻底部电极扩散阻挡层之前形成侧壁扩散阻挡层。然后在底部电极扩散阻挡层之前蚀刻侧壁扩散阻挡层。在蚀刻下面的底部电极扩散阻挡层之前，在构图AlOx侧壁扩散阻挡层之前，蚀刻化学性质包括BCl 3 + Ar。 BCl3在相邻的电容器堆叠之间的电容器堆叠（例如TiAlN）和氮化物底部电极扩散阻挡层（例如，具有小的氧含量的TiAlON）的顶部上对下面的氮化物硬掩模具有良好的选择性是有效的。可以将Ar添加到蚀刻化学品中，因为所得到的表面（硬掩模和底部电极扩散屏障的顶部）更平滑。

8. 发明授权

US06238932B1 Method for fabricating reliable multilayer bottom electrode for ferroelectric capacitors 有权
标题翻译：制造可靠的铁电电容器多层底电极的方法
公开(公告)号：US06238932B1
公开(公告)日：2001-05-29
申请号：US09231023
申请日：1999-01-14
申请人： Katsuhiro Aoki , Tomoyuki Sakoda , Yukio Fukuda
发明人： Katsuhiro Aoki , Tomoyuki Sakoda , Yukio Fukuda
IPC分类号： H01E706
CPC分类号： H01L27/11502 , H01L21/28568 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： A ferroelectric capacitor electrode contact structure comprising an insulator (4) placed over a substrate (2) and containing a transistor source (6) and transistor drain (8) between the substrate (2) and the insulator (4). The insulator (4) contains a source plug (10) and a conductive drain plug (12). The transistor source (6) is electrically connected to the source plug (10). The transistor drain (8) is electrically connected to the conductive drain plug (12). A transistor gate (14) is between the source plug (10) and a conductive drain plug (12) and is contained by the insulator (4). Metal wiring (16) is electrically connected to the source plug (10). A barrier film (18) is placed over the insulator (4) and the conductive drain plug (12). The bottom electrode (20) is placed over the barrier film (18). The ferroelectric layer (22) is placed over the bottom electrode (20). The top electrode (24) is placed over the ferroelectric layer (22).
摘要翻译：一种强电介质电容器电极接触结构，包括放置在衬底（2）上并且在衬底（2）和绝缘体（4）之间包含晶体管源（6）和晶体管漏极（8）的绝缘体（4）。绝缘体（4）包含源极插头（10）和导电排放塞（12）。晶体管源（6）电连接到源极（10）。晶体管漏极（8）电连接到导电排放塞（12）。晶体管栅极（14）位于源极插头（10）和导电排放塞（12）之间，并被绝缘体（4）容纳。金属布线（16）电连接到源插头（10）。隔离膜（18）放置在绝缘体（4）和导电排放塞（12）之上。底部电极（20）放置在阻挡膜（18）上方。铁电层（22）放置在底部电极（20）上。顶部电极（24）被放置在铁电层（22）上方。

9. 发明申请

US20080248595A1 Method for Manufacturing Semiconductor Device and Computer Storage Medium 失效
标题翻译：半导体器件和计算机存储介质的制造方法
公开(公告)号：US20080248595A1
公开(公告)日：2008-10-09
申请号：US11815868
申请日：2006-06-12
申请人： Kenji Matsumoto , Masayuki Nasu , Tomoyuki Sakoda
发明人： Kenji Matsumoto , Masayuki Nasu , Tomoyuki Sakoda
IPC分类号： G06F19/00 , H01L21/285
CPC分类号： H01L21/31691 , C23C16/0272 , C23C16/40 , C23C16/409 , C30B25/02 , C30B29/32 , H01L21/02197 , H01L21/02271 , H01L27/11507 , H01L28/55
摘要： A method for fabricating a semiconductor device includes the steps of forming a PbTiOx film having a predominantly (111) orientation on a lower electrode as a nucleation layer by an MOCVD process with a film thickness exceeding 2 nm, and forming a PZT film having a predominantly (111) orientation on the nucleation layer, wherein the step of forming the PbTiOx film is conducted under an oxygen partial pressure of less than 340 Pa.
摘要翻译：一种制造半导体器件的方法包括以下步骤：通过膜厚超过2nm的MOCVD法在下电极上形成主要为（111）取向的PbTiOx膜作为成核层，并形成主要为（111）取向，其中形成PbTiOx膜的步骤在小于340Pa的氧分压下进行。

10. 发明申请

US20080119033A1 METHOD OF INTEGRATING METAL-CONTAINING FILMS INTO SEMICONDUCTOR DEVICES 失效
标题翻译：将含金属膜整合到半导体器件中的方法
公开(公告)号：US20080119033A1
公开(公告)日：2008-05-22
申请号：US11561810
申请日：2006-11-20
申请人： Shigeo Ashigaki , Hideaki Yamasaki , Tomoyuki Sakoda , Mikio Suzuki , Genji Nakamura , Gert Leusink
发明人： Shigeo Ashigaki , Hideaki Yamasaki , Tomoyuki Sakoda , Mikio Suzuki , Genji Nakamura , Gert Leusink
IPC分类号： H01L21/28
CPC分类号： H01L21/28079 , H01L29/4958 , H01L29/513 , H01L29/518
摘要： A method for integrating a metal-containing film in a semiconductor device, for example a gate stack. In one embodiment, the method includes providing a substrate in a process chamber, depositing the tungsten-containing film on the substrate at a first substrate temperature by exposing the substrate to a deposition gas containing a tungsten carbonyl precursor, heat treating the tungsten-containing film at a second substrate temperature greater than the first substrate temperature to remove carbon monoxide gas from the tungsten-containing film, and forming a barrier layer on the heat treated tungsten-containing film. Examples of tungsten-containing films include W, WN, WSi, and WC. Additional embodiments include depositing metal-containing films containing Ni, Mo, Co, Rh, Re, Cr, or Ru from the corresponding metal carbonyl precursors.
摘要翻译：一种用于将含金属膜整合在半导体器件例如栅极堆叠中的方法。在一个实施例中，该方法包括在处理室中提供衬底，通过将衬底暴露于含有羰基钨前体的沉积气体，在第一衬底温度下将含钨膜沉积在衬底上，热处理含钨膜在大于第一衬底温度的第二衬底温度下从含钨膜中除去一氧化碳气体，并在热处理的含钨膜上形成阻挡层。含钨膜的实例包括W，WN，WSi和WC。另外的实施方案包括从相应的金属羰基前体沉积含有Ni，Mo，Co，Rh，Re，Cr或Ru的含金属膜。

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