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1. 发明授权

US09478284B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US09478284B2
公开(公告)日：2016-10-25
申请号：US14783846
申请日：2013-05-20
申请人： Hitachi, Ltd.
发明人： Yoshitaka Sasago , Hiroyuki Minemura , Kenzo Kurotsuchi , Seiji Miura , Satoru Hanzawa
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/1226 , H01L45/1233
摘要： An object of this invention is to provide a semiconductor memory device capable of increasing the read transfer rate by performing the read operation in parallel while suppressing the voltage drop when a large current is passed to a memory chain and reducing a chip area by reducing the number of peripheral circuits to feed power. A semiconductor memory device according to this invention includes upper and lower electrodes in a flat plate shape, first and second select transistors extending in first and second directions respectively, and a wire arranged between the first select transistor and the second select transistor and the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor (see FIG. 2).
摘要翻译：本发明的目的是提供一种半导体存储器件，其能够通过在大电流通过存储器链的同时抑制电压降并行执行读取操作并且通过减少数字来减小芯片面积来增加读取传送速率的外围电路供电。根据本发明的半导体存储器件包括平板形状的上电极和下电极，分别在第一和第二方向上延伸的第一和第二选择晶体管，以及布置在第一选择晶体管和第二选择晶体管之间的布线，通过关闭第一选择晶体管（参见图2），下电极被配置为彼此电绝缘。

2. 发明申请

US20180247240A1 JUDGMENT SUPPORT SYSTEM AND JUDGMENT SUPPORT METHOD 审中-公开
公开(公告)号：US20180247240A1
公开(公告)日：2018-08-30
申请号：US15839385
申请日：2017-12-12
申请人： HITACHI, LTD.
发明人： Kenzo Kurotsuchi , Kohsuke Yanai , Toshihiko Yanase , Misa Sato , Yuta Koreeda , Yoshiki Niwa , Kazuo Yano
IPC分类号： G06Q10/06 , G06F17/30
CPC分类号： G06Q10/0637 , G06F16/3329 , G06F16/338 , G06F16/34
摘要： Information appropriate for supporting various judgments in organization activities is provided. A judgment support system for supporting a user's judgment, includes: a processor that executes a program; a storage section that can be accessed by the processor; and an output section that outputs data for displaying an execution result of the program. The judgment support system further includes: an extraction section that searches a predetermined sentence expression from data stored in the storage section, and extracts an issue of an organization using text having a predetermined relationship with the searched sentence expression; and a first selection section that selects a second organization confronted with an issue similar to an issue of a first organization to be analyzed, and that selects measures against the issue of the second organization from the data stored in the storage section. The output section outputs data for displaying the selected issue and the selected measures.

3. 发明授权

US11341425B2 Computing apparatus incorporating quantum effects that performs high-speed computation on inverse problems or computational optimization problems requiring exhaustive search 有权
公开(公告)号：US11341425B2
公开(公告)日：2022-05-24
申请号：US15578812
申请日：2015-06-05
申请人： HITACHI, LTD.
发明人： Tatsuya Tomaru , Kenzo Kurotsuchi
IPC分类号： G06N10/00 , G06N5/00 , G06F9/38 , G06F17/12
摘要： A computing apparatus that does not need quantum coherence or a cryogenic cooling apparatus is provided for assignments that need an exhaustive search. A system is led to the ground state of the system where a problem is set, wherein spin sjz that is a variable follows a local effective magnetic field Bjz. The spin state at t=0 is initialized with a transverse field (in the x-direction). This corresponds to sjz=0. With time t, the magnetic field in the z-axis direction and the inter-spin interactions are gradually added, and finally the spin is directed to the +z- or −z-direction. The z component of the spin sj is sjz=+1 or −1. Here, in the process where the orientation of the spin sjz follows that of the effective magnetic field Bjz, correction parameters originating in quantum-mechanical effects are introduced and ground-state-maintaining performance is improved.

4. 发明授权

US09378131B2 Non-volatile storage addressing using multiple tables 有权
标题翻译：使用多个表的非易失性存储寻址
公开(公告)号：US09378131B2
公开(公告)日：2016-06-28
申请号：US13745292
申请日：2013-01-18
申请人： Hitachi, Ltd.
发明人： Kenzo Kurotsuchi , Seiji Miura
IPC分类号： G06F12/00 , G06F9/26 , G06F9/34 , G06F12/02 , G06F12/10 , G06F12/08
CPC分类号： G06F12/0246 , G06F12/08 , G06F12/0802 , G06F12/1009 , G06F2212/7201
摘要： The non-volatile storage solid state drive (SSD) has non-volatile memory (NVM), random access memory (RAM) capable of being accessed at a higher speed than this NVM, and a control unit for controlling accesses to the NVM and to the RAM. The control unit stores in the NVM an address translation table that translates a logical address given to access this NVM to a physical address after dividing it into multiple tables, and stores in the RAM the multiple address translation tables-sub on RAM that have been divided into multiple tables.
摘要翻译：非易失性存储固态驱动器（SSD）具有能够以比该NVM更高的速度访问的非易失性存储器（NVM），随机存取存储器（RAM）以及用于控制对NVM的访问的控制单元， RAM。控制单元将NVM中的地址转换表存储在地址转换表中，该地址转换表将将该NVM访问的逻辑地址转换为物理地址，并将其分割成多个表，并将RAM中分配的多个地址转换表分成多个表。

5. 发明授权

US10338046B2 Artificial olfactory sensing system 有权
公开(公告)号：US10338046B2
公开(公告)日：2019-07-02
申请号：US15760777
申请日：2016-01-15
申请人： HITACHI, LTD.
发明人： Masahiko Ando , Sanato Nagata , Shirun Ho , Yuji Suwa , Mitsuharu Tai , Kenzo Kurotsuchi , Hiromasa Takahashi , Norifumi Kameshiro , Seiichi Suzuki
IPC分类号： C12M1/34 , G01N27/27 , G01N33/00 , G01N27/414
摘要： An object of the present invention is to provide an artificial olfactory sensing system capable of sniffing out various odors highly sensitively.The artificial olfactory sensing system includes: plural sensor cells on a lipid membrane of each of which olfactory receptors have developed; and plural ion-sensitive field-effect transistors (ISFETs) that correspondingly exist to the sensor cells on a one-on-one basis. A response signal showing that each of the olfactory receptors of each of the sensor cells has recognized an odor molecule is converted into an electric signal by an ISFET corresponding to each of the sensor cells.

6. 发明授权

US09099171B2 Information processor 有权
标题翻译：信息处理器
公开(公告)号：US09099171B2
公开(公告)日：2015-08-04
申请号：US13875448
申请日：2013-05-02
申请人： HITACHI, LTD.
发明人： Hiroshi Uchigaito , Kenzo Kurotsuchi , Seiji Miura
IPC分类号： G06F9/26 , G11C7/10 , G06F12/08
CPC分类号： G06F3/0611 , G06F3/0647 , G06F3/0683 , G06F12/08 , G06F17/30318 , G06F17/30958 , G11C7/1072
摘要： An information processor includes an information processing sub-system having information processing circuits and a memory sub-system performing data communication with the information processing sub-systems, wherein the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a memory controller for controlling data transfer among the first memory, the second memory and the third memory; graph data is stored in the third memory; the memory controller analyzes data blocks serving as part of the graph data, and performs preloading operation repeatedly to transfer the data blocks to be required next for the execution of the processing from the third memory to the first memory or the second memory on the basis of the result of the analysis.
摘要翻译：信息处理器包括具有信息处理电路的信息处理子系统和与信息处理子系统执行数据通信的存储器子系统，其中存储子系统具有第一存储器，第二存储器，第三存储器，读取和写入延迟比第一存储器和第二存储器的延迟更长;以及存储器控制器，用于控制第一存储器，第二存储器和第三存储器之间的数据传送; 图形数据存储在第三存储器中; 存储器控制器分析作为图形数据的一部分的数据块，并且重复执行预加载操作，以基于第三存储器或第二存储器从第三存储器向第一存储器或第二存储器传送要执行的处理所需的下一个数据块分析结果。

7. 发明授权

US10783184B2 Data generation method and computer system 有权
公开(公告)号：US10783184B2
公开(公告)日：2020-09-22
申请号：US15593428
申请日：2017-05-12
申请人： Hitachi, Ltd.
发明人： Junichi Miyakoshi , Masanao Yamaoka , Hiromasa Takahashi , Shirun Ho , Kenzo Kurotsuchi , Sanato Nagata
IPC分类号： G06N20/00 , G06F16/901 , G06F16/25 , G06F16/23 , G06N3/04
摘要： A computer includes a data generation unit and a storage unit which retains graph information for managing a graph configured from a plurality of vertexes and sides. The data generation unit performs acquiring a plurality of data and graph information and assuring storage regions in number equal to the number of vertexes, converting each data into an input value and setting at least one input value to a storage region corresponding to at least one vertex, executing an updating process for updating a value set to a storage region corresponding to a first vertex using the value set to the storage region corresponding to the first vertex and a value set to a storage region corresponding to a different vertex directly connected to the first vertex, and outputting a set of values set to the storage regions corresponding to the vertexes as the feature value.

8. 发明申请

US20180373995A1 COMPUTER 审中-公开
公开(公告)号：US20180373995A1
公开(公告)日：2018-12-27
申请号：US15578812
申请日：2015-06-05
申请人： HITACHI, LTD.
发明人： Tatsuya Tomaru , Kenzo Kurotsuchi
IPC分类号： G06N99/00 , G06F17/12 , G06F9/38
摘要： A computing apparatus that does not need quantum coherence or a cryogenic cooling apparatus is provided for assignments that need an exhaustive search.A system is led to the ground state of the system where a problem is set, wherein spin sjz that is a variable follows a local effective magnetic field Bjz. The spin state at t=0 is initialized with a transverse field (in the x-direction). This corresponds to sjz=0. With time t, the magnetic field in the z-axis direction and the inter-spin interactions are gradually added, and finally the spin is directed to the +z- or −z-direction. The z component of the spin sj is sjz=+1 or −1. Here, in the process where the orientation of the spin sjz follows that of the effective magnetic field Bjz, correction parameters originating in quantum-mechanical effects are introduced and ground-state-maintaining performance is improved.

9. 发明授权

US09905756B2 Semiconductor storage device 有权
公开(公告)号：US09905756B2
公开(公告)日：2018-02-27
申请号：US15115966
申请日：2014-02-03
申请人： HITACHI, LTD.
发明人： Yoshitaka Sasago , Kenzo Kurotsuchi
IPC分类号： H01L27/24 , H01L45/00 , H01L21/02 , G11C13/00
CPC分类号： H01L45/06 , G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/1226 , H01L45/1233 , H01L45/16
摘要： In a semiconductor storage device that is formed on a semiconductor substrate, flows a current to a recording material formed between electrodes to change a resistance value of the recording material and store information, and flows currents of different magnitudes in a high resistance change operation and a low resistance change operation, electrodes of a plurality of memory cells are electrically connected directly or via transistors to form large electrodes, the large electrodes are connected to a feeding terminal from a power source circuit, and the large electrodes are connected to large electrodes connected to a feeding terminal from a power source connected between a plurality of memory cells different from the plurality of memory cells via inter-large electrode connection transistors. By using the semiconductor storage device, a connection pattern of a feeding electrode for the memory cells can be configured according to the magnitude of a consumption current, power consumption by a voltage drop by a parasitic resistance of the feeding electrode and power consumption by charge/discharge of a parasitic capacitance around the feeding electrode can be suppressed, and performance per consumption power in read/set/reset operations can be improved.

10. 发明授权

US09490429B2 Nonvolatile memory device and method for manufacturing same 有权
公开(公告)号：US09490429B2
公开(公告)日：2016-11-08
申请号：US14860349
申请日：2015-09-21
申请人： Hitachi, Ltd.
发明人： Yoshitaka Sasago , Masaharu Kinoshita , Mitsuharu Tai , Akio Shima , Kenzo Kurotsuchi , Takashi Kobayashi
IPC分类号： H01L45/00 , H01L27/06 , H01L27/102 , H01L29/792 , H01L27/24 , H01L27/115 , G11C13/00
CPC分类号： H01L45/1608 , G11C13/0004 , G11C2213/75 , H01L27/0688 , H01L27/1021 , H01L27/11578 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/7926 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/144 , H01L45/16 , H01L45/1675
摘要： When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.

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