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1. 发明授权

US10037168B2 Memory module and information processing system 有权
公开(公告)号：US10037168B2
公开(公告)日：2018-07-31
申请号：US15318498
申请日：2014-07-09
申请人： HITACHI, LTD.
发明人： Seiji Miura
IPC分类号： G06F12/1009 , G06F3/06
CPC分类号： G06F3/0659 , G06F3/0616 , G06F3/0631 , G06F3/0679 , G06F3/0685 , G06F12/0246 , G06F12/1009 , G06F12/16 , G06F2212/1036 , G06F2212/205 , G06F2212/651 , G06F2212/7201 , G06F2212/7203 , G06F2212/7204 , G06F2212/7208 , G06F2212/7211
摘要： A memory module includes: a first memory device that is volatile or non-volatile; a second memory device that is non-volatile; a third memory device that is non-volatile; and a controller that controls the first to third memory devices, wherein a capacity of the second memory device is larger than a capacity of the first memory device, and a capacity of the third memory device is larger than the capacity of the second memory device, a second upper limit value of the number of rewritings of the second memory device is larger than a third upper limit value of the number of rewritings of the third memory device, and a first upper limit value of the number of rewritings of the first memory device is larger than the second upper limit value of the number of rewritings of the second memory device, and the controller accesses the second memory device with reference to a first address translation table related to the second memory device stored in the first memory device, and accesses the third memory device with reference to a second address translation table related to the third memory device stored in the second memory device.

2. 发明授权

US09378131B2 Non-volatile storage addressing using multiple tables 有权
标题翻译：使用多个表的非易失性存储寻址
公开(公告)号：US09378131B2
公开(公告)日：2016-06-28
申请号：US13745292
申请日：2013-01-18
申请人： Hitachi, Ltd.
发明人： Kenzo Kurotsuchi , Seiji Miura
IPC分类号： G06F12/00 , G06F9/26 , G06F9/34 , G06F12/02 , G06F12/10 , G06F12/08
CPC分类号： G06F12/0246 , G06F12/08 , G06F12/0802 , G06F12/1009 , G06F2212/7201
摘要： The non-volatile storage solid state drive (SSD) has non-volatile memory (NVM), random access memory (RAM) capable of being accessed at a higher speed than this NVM, and a control unit for controlling accesses to the NVM and to the RAM. The control unit stores in the NVM an address translation table that translates a logical address given to access this NVM to a physical address after dividing it into multiple tables, and stores in the RAM the multiple address translation tables-sub on RAM that have been divided into multiple tables.
摘要翻译：非易失性存储固态驱动器（SSD）具有能够以比该NVM更高的速度访问的非易失性存储器（NVM），随机存取存储器（RAM）以及用于控制对NVM的访问的控制单元， RAM。控制单元将NVM中的地址转换表存储在地址转换表中，该地址转换表将将该NVM访问的逻辑地址转换为物理地址，并将其分割成多个表，并将RAM中分配的多个地址转换表分成多个表。

3. 发明授权

US09286212B2 Semiconductor device and method of controlling non-volatile memory device 有权
公开(公告)号：US09286212B2
公开(公告)日：2016-03-15
申请号：US14725273
申请日：2015-05-29
申请人： Hitachi, Ltd.
发明人： Seiji Miura
IPC分类号： G06F12/02 , G06F13/00 , G11C13/00
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7202 , G06F2212/7209 , G06F2212/7211 , G11C13/0004
摘要： A control circuit of a semiconductor device (memory module) realizes long life and others by a mechanism that suppresses and smoothes variations in use of a memory by equalizing the sizes of data write and data erase with respect to a data write request and sequentially allocating and using addresses of the memory in data write to an overwritable non-volatile memory device without carrying out an overwriting operation even in the case of an overwrite request. The control circuit realizes data write by a set of two types of operations of (a) an operation of erasing data of a first address or an operation of setting a flag value to an invalid state and (b) an operation of writing data to a second address different from the first address or an operation of setting a flag value to a valid state.

4. 发明授权

US09069662B2 Semiconductor device and method of controlling non-volatile memory device 有权
公开(公告)号：US09069662B2
公开(公告)日：2015-06-30
申请号：US14514178
申请日：2014-10-14
申请人： Hitachi, Ltd.
发明人： Seiji Miura
IPC分类号： G06F12/02 , G11C13/00
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7202 , G06F2212/7209 , G06F2212/7211 , G11C13/0004
摘要： A control circuit of a semiconductor device (memory module) realizes long life and others by a mechanism that suppresses and smoothes variations in use of a memory by equalizing the sizes of data write and data erase with respect to a data write request and sequentially allocating and using addresses of the memory in data write to an overwritable non-volatile memory device without carrying out an overwriting operation even in the case of an overwrite request. The control circuit realizes data write by a set of two types of operations of (a) an operation of erasing data of a first address or an operation of setting a flag value to an invalid state and (b) an operation of writing data to a second address different from the first address or an operation of setting a flag value to a valid state.

5. 发明授权

US08949516B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08949516B2
公开(公告)日：2015-02-03
申请号：US13632465
申请日：2012-10-01
申请人： Hitachi, Ltd.
发明人： Seiji Miura
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C14/009 , G06F11/1072 , G06F12/0246 , G11C29/52
摘要： An object of the present invention is to realize a highly reliable long-life information processor capable of high-speed operation and easy to handle. The processor includes a semiconductor device comprising a nonvolatile memory device including a plurality of overwritable memory cells, and a control circuit device for controlling access to the nonvolatile memory device. The control circuit device sets assignments of second addresses to the nonvolatile memory device independently of first addresses externally supplied, such that the physical disposition of part of the memory cells used for writing of first data to be written externally supplied is one of the first to (N+1)th of every (N+1) memory cells (N: a natural number) at least in one direction.
摘要翻译：本发明的目的是实现能够高速操作并且易于处理的高可靠性的长寿命信息处理器。该处理器包括一个包括一个非易失性存储器件的半导体器件，该非易失性存储器件包括多个可重写存储器单元，以及用于控制对非易失性存储器件的访问的控制电路器件。控制电路装置独立于外部提供的第一地址，将第二地址的分配设置到非易失性存储装置，使得用于写入外部提供的第一数据的部分存储单元的物理布置是第一到第每个（N + 1）个存储单元（N：自然数）的N + 1）个（至少一个方向）。

6. 发明申请

US20150032949A1 Semiconductor Device and Method of Controlling Non-Volatile Memory Device 审中-公开
公开(公告)号：US20150032949A1
公开(公告)日：2015-01-29
申请号：US14514178
申请日：2014-10-14
申请人： Hitachi, Ltd.
发明人： Seiji Miura
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7202 , G06F2212/7209 , G06F2212/7211 , G11C13/0004
摘要： A control circuit of a semiconductor device (memory module) realizes long life and others by a mechanism that suppresses and smoothes variations in use of a memory by equalizing the sizes of data write and data erase with respect to a data write request and sequentially allocating and using addresses of the memory in data write to an overwritable non-volatile memory device without carrying out an overwriting operation even in the case of an overwrite request. The control circuit realizes data write by a set of two types of operations of (a) an operation of erasing data of a first address or an operation of setting a flag value to an invalid state and (b) an operation of writing data to a second address different from the first address or an operation of setting a flag value to a valid state.

7. 发明授权

US11574165B2 Optimization system and optimization method 有权
公开(公告)号：US11574165B2
公开(公告)日：2023-02-07
申请号：US16410217
申请日：2019-05-13
申请人： Hitachi, Ltd.
发明人： Seiji Miura , Junichi Miyakoshi
IPC分类号： G06N3/00 , G06F17/00 , G06N3/04 , G06F17/11 , G06N3/08
摘要： An optimization system has a plurality of nodes, each including: a calculation processing unit that calculates an optimum value of a determination variable representing a parameter that controls the nodes by using the ADMM; and a function value calculation unit that receives an input of a value of the determination variable and calculates the value of the objective function based on a calculation model constructed by a learning processing. An arbitrary value of the determination variable is input to the function value calculation unit, and the calculation processing unit substitutes the value of the objective function calculated by the function value calculation unit and the arbitrary value of the determination variable into a second optimization problem by dual transformation of the first optimization problem, thereby repeatedly executing a processing of calculating a value of the dual variable until the value of the dual variable satisfies a predetermined condition.

8. 发明授权

US10237159B2 Computer system and method of controlling computer system 有权
公开(公告)号：US10237159B2
公开(公告)日：2019-03-19
申请号：US15593731
申请日：2017-05-12
申请人： Hitachi, Ltd.
发明人： Seiji Miura , Junichi Miyakoshi
IPC分类号： H04L12/26 , H04L29/08
摘要： A large-scale computer system including a plurality of nodes is controlled to improve its system performance without aggregating data in a single site. There is provided a computer system including a plurality of computers, wherein a processor: detects a trigger to calculate a control value for controlling a process to be performed by the computer; identifies a target computer for which an evaluation value is obtained; calculates the evaluation value of its own computer; obtains the evaluation value from the target computer; calculates a first point using at least one of the evaluation value of its own computer and the evaluation value of the target computer; obtains a second point from the target computer; calculates the control value using the first point and the second point; and controls the process performed by the computer based on the control value.

9. 发明授权

US09268486B2 Information processor 有权
公开(公告)号：US09268486B2
公开(公告)日：2016-02-23
申请号：US14799795
申请日：2015-07-15
申请人： HITACHI, LTD.
发明人： Hiroshi Uchigaito , Kenzo Kurotsuchi , Seiji Miura
IPC分类号： G06F9/26 , G06F3/06 , G06F17/30
CPC分类号： G06F3/0611 , G06F3/0647 , G06F3/0683 , G06F12/08 , G06F17/30318 , G06F17/30958 , G11C7/1072
摘要： An information processor includes an information processing sub-system having information processing circuits and a memory sub-system performing data communication with the information processing sub-systems, wherein the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a memory controller for controlling data transfer among the first memory, the second memory and the third memory; graph data is stored in the third memory; the memory controller analyzes data blocks serving as part of the graph data, and performs preloading operation repeatedly to transfer the data blocks to be required next for the execution of the processing from the third memory to the first memory or the second memory on the basis of the result of the analysis.

10. 发明授权

US10388369B2 Nonvolatile memory control method, control device, and semiconductor storage device 有权
公开(公告)号：US10388369B2
公开(公告)日：2019-08-20
申请号：US15566854
申请日：2015-04-28
申请人： HITACHI, LTD.
发明人： Seiji Miura
IPC分类号： G06F12/00 , G11C13/00 , G06F12/02
摘要： Disclosed is a nonvolatile memory control method in which a unit of erase and a unit of read are different from each other. The control method includes: allocating a physical address of the nonvolatile memory to a logical address in a predetermined unit; and controlling a size of the unit of erase in which a physical address allocated to a logical address is included according to a write access state with respect to the logical address in the predetermined unit.

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