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1. 发明授权

US09478284B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US09478284B2
公开(公告)日：2016-10-25
申请号：US14783846
申请日：2013-05-20
申请人： Hitachi, Ltd.
发明人： Yoshitaka Sasago , Hiroyuki Minemura , Kenzo Kurotsuchi , Seiji Miura , Satoru Hanzawa
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/1226 , H01L45/1233
摘要： An object of this invention is to provide a semiconductor memory device capable of increasing the read transfer rate by performing the read operation in parallel while suppressing the voltage drop when a large current is passed to a memory chain and reducing a chip area by reducing the number of peripheral circuits to feed power. A semiconductor memory device according to this invention includes upper and lower electrodes in a flat plate shape, first and second select transistors extending in first and second directions respectively, and a wire arranged between the first select transistor and the second select transistor and the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor (see FIG. 2).
摘要翻译：本发明的目的是提供一种半导体存储器件，其能够通过在大电流通过存储器链的同时抑制电压降并行执行读取操作并且通过减少数字来减小芯片面积来增加读取传送速率的外围电路供电。根据本发明的半导体存储器件包括平板形状的上电极和下电极，分别在第一和第二方向上延伸的第一和第二选择晶体管，以及布置在第一选择晶体管和第二选择晶体管之间的布线，通过关闭第一选择晶体管（参见图2），下电极被配置为彼此电绝缘。

2. 发明申请

US20140361241A1 SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20140361241A1
公开(公告)日：2014-12-11
申请号：US14468513
申请日：2014-08-26
申请人： Hitachi, Ltd.
发明人： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikatsu Takaura
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/1666 , H01L27/224 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1206 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.
摘要翻译：公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。半导体存储装置具有：基板; 设置在基板上方的第一字线（2）第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N≥1）个第一栅极间绝缘层（11-15）和N个第一半导体层（21p-24p）在基板的高度方向上交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧面上的第一可变电阻材料层（7）。第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。此外，使用多晶硅二极管（PD）作为选择元件。

3. 发明授权

US09905756B2 Semiconductor storage device 有权
公开(公告)号：US09905756B2
公开(公告)日：2018-02-27
申请号：US15115966
申请日：2014-02-03
申请人： HITACHI, LTD.
发明人： Yoshitaka Sasago , Kenzo Kurotsuchi
IPC分类号： H01L27/24 , H01L45/00 , H01L21/02 , G11C13/00
CPC分类号： H01L45/06 , G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/1226 , H01L45/1233 , H01L45/16
摘要： In a semiconductor storage device that is formed on a semiconductor substrate, flows a current to a recording material formed between electrodes to change a resistance value of the recording material and store information, and flows currents of different magnitudes in a high resistance change operation and a low resistance change operation, electrodes of a plurality of memory cells are electrically connected directly or via transistors to form large electrodes, the large electrodes are connected to a feeding terminal from a power source circuit, and the large electrodes are connected to large electrodes connected to a feeding terminal from a power source connected between a plurality of memory cells different from the plurality of memory cells via inter-large electrode connection transistors. By using the semiconductor storage device, a connection pattern of a feeding electrode for the memory cells can be configured according to the magnitude of a consumption current, power consumption by a voltage drop by a parasitic resistance of the feeding electrode and power consumption by charge/discharge of a parasitic capacitance around the feeding electrode can be suppressed, and performance per consumption power in read/set/reset operations can be improved.

4. 发明授权

US09490429B2 Nonvolatile memory device and method for manufacturing same 有权
公开(公告)号：US09490429B2
公开(公告)日：2016-11-08
申请号：US14860349
申请日：2015-09-21
申请人： Hitachi, Ltd.
发明人： Yoshitaka Sasago , Masaharu Kinoshita , Mitsuharu Tai , Akio Shima , Kenzo Kurotsuchi , Takashi Kobayashi
IPC分类号： H01L45/00 , H01L27/06 , H01L27/102 , H01L29/792 , H01L27/24 , H01L27/115 , G11C13/00
CPC分类号： H01L45/1608 , G11C13/0004 , G11C2213/75 , H01L27/0688 , H01L27/1021 , H01L27/11578 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/7926 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/144 , H01L45/16 , H01L45/1675
摘要： When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.

5. 发明申请

US20140103287A1 SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20140103287A1
公开(公告)日：2014-04-17
申请号：US14046984
申请日：2013-10-06
申请人： Hitachi, Ltd.
发明人： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikatsu Takaura
IPC分类号： H01L45/00
CPC分类号： H01L45/1666 , H01L27/224 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1206 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Disclosed are a semiconductor storage device and a manufacturing method. The storage device has: a substrate; a first word line above the substrate; a first laminated body above the first word line and having N+1 first inter-gate insulating layers and N first semiconductor layers alternately laminated; a first bit line above the laminated body and extending in a direction that intersects the first word line; a first gate insulating layer on side surfaces of the first inter-gate insulating layers and the first semiconductor layers; a first channel layer on the side surface of the first gate insulating layer; and a first variable resistance material layer on the side surface of the first channel layer. The first variable resistance material layer is in a region where the first word line and the first bit line intersect. A polysilicon diode is used as a selection element.
摘要翻译：公开了一种半导体存储装置及其制造方法。存储装置具有：基板; 衬底上的第一个字线; 第一层叠体，位于第一字线上方，并且具有N + 1个第一栅极间绝缘层和N个第一半导体层交替层叠; 位于所述层叠体上方并沿与所述第一字线相交的方向延伸的第一位线; 在所述第一栅极绝缘层和所述第一半导体层的侧表面上的第一栅极绝缘层; 在所述第一栅极绝缘层的侧表面上的第一沟道层; 以及在第一沟道层的侧表面上的第一可变电阻材料层。第一可变电阻材料层在第一字线和第一位线相交的区域中。多晶硅二极管用作选择元件。

6. 发明申请

US20130292630A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20130292630A1
公开(公告)日：2013-11-07
申请号：US13798534
申请日：2013-03-13
申请人： HITACHI, LTD.
发明人： Yoshitaka Sasago , Akira Kotabe
IPC分类号： H01L27/24
CPC分类号： H01L27/2463 , G11C13/0004 , G11C13/0007 , G11C2213/71 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/1226 , H01L45/144
摘要： The technical problem to be solved is to achieve high density with simple manufacturing process to decrease bit costs of memory.A semiconductor memory device according to a first aspect of the present invention includes a variable resistance material layer and a channel layer that are connected in series between a first diffusion layer and a metal wire, thereby separating the metal wire and a channel semiconductor layer.A semiconductor memory device according to a second aspect of the present invention includes a variable resistance material layer electrically connecting channel semiconductor layers opposed to each other in a first direction and electrically connecting channel semiconductor layers adjacent to each other in a second direction, wherein a plurality of the channel semiconductor layers is disposed in the second direction.
摘要翻译：要解决的技术问题是通过简单的制造过程实现高密度，降低存储器的位成本。根据本发明的第一方面的半导体存储器件包括串联连接在第一扩散层和金属线之间的可变电阻材料层和沟道层，从而分离金属线和沟道半导体层。根据本发明的第二方面的半导体存储器件包括：可变电阻材料层，电连接在第一方向上彼此相对的沟道半导体层，并且在第二方向上电连接彼此相邻的沟道半导体层，其中多个的沟道半导体层设置在第二方向上。

7. 发明授权

US10466198B2 Gas sensor 有权
公开(公告)号：US10466198B2
公开(公告)日：2019-11-05
申请号：US15788308
申请日：2017-10-19
申请人： HITACHI, LTD.
发明人： Yoshitaka Sasago , Toshiyuki Usagawa , Hitoshi Nakamura
IPC分类号： G01N27/414 , H01L29/78 , H01L29/49 , H01L23/34 , H01L29/08 , H01L29/10
摘要： In a gas sensor using a first FET-type sensor for a sensor unit, a gas density measurement unit measures a gas density of gas to be detected at a predetermined time on the basis of a first threshold change as a difference between a first threshold voltage applied to a first gate layer when a first source-drain current is a first threshold current while the gas to be detected is not present in the atmosphere and a second threshold voltage applied to the first gate layer when the first source-drain current is the first threshold current at the predetermined time while the gas to be detected is present in the atmosphere, and a temporal differentiation of the first threshold change.

8. 发明授权

US09857610B2 Optical modulator and method for manufacturing same 有权
公开(公告)号：US09857610B2
公开(公告)日：2018-01-02
申请号：US15311434
申请日：2014-06-19
申请人： HITACHI, LTD.
发明人： Hideo Arimoto , Kazuki Tani , Takashi Takahama , Daisuke Ryuzaki , Yoshitaka Sasago
IPC分类号： G02F1/025 , G02F1/225 , G02F1/015 , G02F1/21
CPC分类号： G02F1/025 , G02F1/2257 , G02F2001/0151 , G02F2001/212 , G02F2202/104
摘要： In an optical modulator 115 of an embodiment, an optical waveguide core 121 is configured from an n− type semiconductor region 134, a gate insulating film 136 on the n− type semiconductor region 134, and a p− type semiconductor region 137 on the gate insulating film 136. Further, a width W1 of the n− type semiconductor region 134 and a width W1 of the p− type semiconductor region 137 are equally formed and are layered without being shifted. Therefore, an optical modulator having stable optical characteristics can be provided.

9. 发明申请

US20160005969A1 SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20160005969A1
公开(公告)日：2016-01-07
申请号：US14857217
申请日：2015-09-17
申请人： Hitachi, Ltd.
发明人： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikatsu Takaura
IPC分类号： H01L45/00
CPC分类号： H01L45/1666 , H01L27/224 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1206 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.
摘要翻译：公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。半导体存储装置具有：基板; 设置在基板上方的第一字线（2）第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N≥1）个第一栅极间绝缘层（11-15）和N个第一半导体层（21p-24p）在基板的高度方向上交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧表面上的第一可变电阻材料层（7）。第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。此外，使用多晶硅二极管（PD）作为选择元件。

10. 发明授权

US09070621B2 Nonvolatile semiconductor memory device and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US09070621B2
公开(公告)日：2015-06-30
申请号：US14076261
申请日：2013-11-10
申请人： Hitachi, Ltd.
发明人： Yoshitaka Sasago , Masaharu Kinoshita , Mitsuharu Tai , Takashi Kobayashi
IPC分类号： H01L27/24 , H01L27/102
CPC分类号： H01L27/2481 , H01L27/1021 , H01L27/2409 , H01L27/2436 , H01L27/2472
摘要： In a nonvolatile semiconductor memory device, there is provided a technique which promotes microfabrication by reducing a thickness of the device as suppressing an OFF current of a polysilicon diode which is a selective element. A polysilicon layer to which an impurity is doped at low concentration and which becomes an electric-field relaxation layer of the polysilicon diode which is a selective element of a resistance variable memory is formed so as to be divided into two or more layers such as polysilicon layers. In this manner, it is suppressed to form the crystal grain boundaries thoroughly penetrating between an n-type polysilicon layer and a p-type polysilicon layer in the electric-field relaxation layer, and therefore, it is prevented to generate a leakage current flowing through the crystal grain boundaries in application of a reverse-bias voltage without increasing a height of the polysilicon diode.
摘要翻译：在非易失性半导体存储器件中，提供了一种通过减小作为选择元件的多晶硅二极管的截止电流来减小器件厚度来促进微细加工的技术。形成以低浓度掺杂有杂质并作为电阻可变存储器的选择元件的多晶硅二极管的电场弛豫层的多晶硅层，以被分成两层或多层，例如多晶硅层。以这种方式抑制电场弛豫层中的n型多晶硅层和p型多晶硅层之间的晶粒边界完全透过，从而防止产生流过的漏电流在不增加多晶硅二极管的高度的情况下施加反偏压的晶界。

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