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1. 发明授权

US5434385A Dual channel D.C. low noise measurement system and test methodology 失效
标题翻译：双通道D.C.低噪声测量系统和测试方法
公开(公告)号：US5434385A
公开(公告)日：1995-07-18
申请号：US970370
申请日：1992-11-02
申请人： Glenn A. Biery , Daniel M. Boyne , Kenneth P. Rodbell , Richard G. Smith , Michael H. Wood
发明人： Glenn A. Biery , Daniel M. Boyne , Kenneth P. Rodbell , Richard G. Smith , Michael H. Wood
IPC分类号： G01R31/26 , G01R29/26 , H01L21/66 , F27D11/02 , H02H7/04 , H05B11/00
CPC分类号： G01R29/26
摘要： A test system having an improved physical layout and electrical design allows the 1/f noise of metal interconnects to be measured at levels close to that of Johnson or thermal noise. A detailed description of examples of operation of the test system provides evidence of the effectiveness of the test system in minimizing system noise to a level significantly lower than Johnson noise. This permits quantitative measurment of the noise contribution attributable to variations in cross-sectional area of connections for various applications and for qualitative prediction of electromigration lifetimes of metal films, particularly aluminum, having different microstructures. The test system includes an enclosure which includes several nested groups of housings including a sample oven within a device under test box which is, in turn, contained within the system enclosure. Wire wound resistors powered by a DC power supply are used to provide heating without interfering with measurement of 1/f noise of a device under test (D.U.T.). A biasing circuit and a bank of batteries are also provided with separate enclosures within the system enclosure.
摘要翻译：具有改进的物理布局和电气设计的测试系统允许以接近Johnson或热噪声的水平测量金属互连的1 / f噪声。测试系统操作示例的详细描述提供了测试系统在将系统噪声降至明显低于约翰逊噪声水平的有效性的证据。这允许由于各种应用的连接的横截面积的变化以及用于定性预测具有不同微结构的金属膜，特别是铝的电迁移寿命的噪声贡献的定量测量。该测试系统包括一个外壳，该外壳包括若干嵌套的外壳组，其中包括在被测箱的设备内的样品烘箱，该烘箱也被包含在系统外壳内。由直流电源供电的绕线电阻器用于提供加热，而不会干扰被测器件（D.U.T.）的1 / f噪声的测量。偏置电路和电池组还在系统外壳内设置有单独的外壳。

2. 发明授权

US5563517A Dual channel d.c. low noise measurement system and test methodology 失效
标题翻译：双通道直流低噪声测量系统和测试方法
公开(公告)号：US5563517A
公开(公告)日：1996-10-08
申请号：US442556
申请日：1995-05-16
申请人： Glenn A. Biery , Daniel M. Boyne , Kenneth P. Rodbell , Richard G. Smith , Michael H. Wood
发明人： Glenn A. Biery , Daniel M. Boyne , Kenneth P. Rodbell , Richard G. Smith , Michael H. Wood
IPC分类号： G01R31/26 , G01R29/26 , H01L21/66
CPC分类号： G01R29/26
摘要： A test system having an improved physical layout and electrical design allows the 1/f noise of metal interconnects to be measured at levels close to that of Johnson or thermal noise. A detailed description of examples of operation of the test system provides evidence of the effectiveness of the test system in minimizing system noise to a level significantly lower than Johnson noise. This permits quantitative measurment of the noise contribution attributable to variations in cross-sectional area of connections for various applications and for qualitative prediction of electromigration lifetimes of metal films, particularly aluminum, having different microstructures. The test system includes an enclosure which includes several nested groups of housings including a sample oven within a device under test box which is, in turn, contained within the system enclosure. Wire wound resistors powered by a DC power supply are used to provide heating without interfering with measurement of 1/f noise of a device under test (D.U.T.). A biasing circuit and a bank of batteries are also provided with separate enclosures within the system enclosure.
摘要翻译：具有改进的物理布局和电气设计的测试系统允许以接近Johnson或热噪声的水平测量金属互连的1 / f噪声。测试系统操作示例的详细描述提供了测试系统在将系统噪声降至明显低于约翰逊噪声水平的有效性的证据。这允许由于各种应用的连接的横截面积的变化以及用于定性预测具有不同微结构的金属膜，特别是铝的电迁移寿命的噪声贡献的定量测量。该测试系统包括一个外壳，该外壳包括若干嵌套的外壳组，其中包括在被测箱的设备内的样品烘箱，该烘箱也被包含在系统外壳内。由直流电源供电的绕线电阻器用于提供加热，而不会干扰被测器件（D.U.T.）的1 / f噪声的测量。偏置电路和电池组还在系统外壳内设置有单独的外壳。

3. 发明授权

US06037795A Multiple device test layout 失效
标题翻译：多设备测试布局
公开(公告)号：US06037795A
公开(公告)日：2000-03-14
申请号：US938871
申请日：1997-09-26
申请人： Ronald G. Filippi , James J. Poulin , Robert D. Raviart , Kenneth P. Rodbell , Richard G. Smith , Timothy D. Sullivan , Alexander J. Swinton
发明人： Ronald G. Filippi , James J. Poulin , Robert D. Raviart , Kenneth P. Rodbell , Richard G. Smith , Timothy D. Sullivan , Alexander J. Swinton
IPC分类号： G01R31/28 , H01L23/544
CPC分类号： G01R31/2858 , G01R31/2853 , H01L22/34 , H01L2924/0002
摘要： A test layout increases the sample size of electromigration experiments. Through pad sharing, the number of structures tested can be increased, allowing hundreds of identical structures to be tested in a single high temperature oven door.
摘要翻译：测试布局增加了电迁移实验的样本量。通过垫共享，可以增加测试结构的数量，允许在单个高温烤箱门中测试数百个相同的结构。

4. 发明授权

US08999764B2 Ionizing radiation blocking in IC chip to reduce soft errors 有权
标题翻译： IC芯片中的电离辐射阻断减少软错误
公开(公告)号：US08999764B2
公开(公告)日：2015-04-07
申请号：US11836819
申请日：2007-08-10
申请人： Mukta G. Farooq , Ian D. Melville , Kevin S. Petrarca , Kenneth P. Rodbell
发明人： Mukta G. Farooq , Ian D. Melville , Kevin S. Petrarca , Kenneth P. Rodbell
IPC分类号： H01L21/00 , H01L23/532 , H01L23/556
CPC分类号： H01L23/5329 , H01L23/556 , H01L2924/0002 , Y10S438/958 , Y10S438/967 , H01L2924/00
摘要： Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.
摘要翻译：公开了阻止电离辐射以减少软错误的方法和产生的IC芯片。一个实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及在其中形成包括其中的电离辐射阻挡材料的至少一个后端线（BEOL）电介质层。另一实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及形成位于IC芯片的后端（BEOL）的电离辐射阻挡层。电离辐射阻挡材料或层吸收电离辐射并减少IC芯片内的软误差。

5. 发明授权

US08785217B2 Tunable radiation source 有权
标题翻译：可调辐射源
公开(公告)号：US08785217B2
公开(公告)日：2014-07-22
申请号：US13230798
申请日：2011-09-12
申请人： Michael A. Gaynes , Michael S. Gordon , Nancy C. LaBianca , Kenneth P. Rodbell
发明人： Michael A. Gaynes , Michael S. Gordon , Nancy C. LaBianca , Kenneth P. Rodbell
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： H01L23/556 , G01R31/2881 , G06F17/5036 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00
摘要： An energy distribution of soft error-inducing radiation likely to be encountered by an electronic circuit during operation is determined. A tuned radiation source having a source energy distribution similar to the determined energy distribution is prepared. The electronic circuit is tested using the tuned radiation source.
摘要翻译：确定在操作期间可能由电子电路遇到的软误差诱发辐射的能量分布。制备具有与所确定的能量分布相似的源能分布的调谐辐射源。使用调谐的辐射源测试电子电路。

6. 发明授权

US08293643B2 Method and structure of forming silicide and diffusion barrier layer with direct deposited film on silicon 有权
标题翻译：在硅上直接沉积薄膜形成硅化物和扩散阻挡层的方法和结构
公开(公告)号：US08293643B2
公开(公告)日：2012-10-23
申请号：US12819634
申请日：2010-06-21
申请人： Cyril Cabral, Jr. , John M. Cotte , Kathryn C. Fisher , Laura L. Kosbar , Christian Lavoie , Zhu Liu , Kenneth P. Rodbell , Xiaoyan Shao
发明人： Cyril Cabral, Jr. , John M. Cotte , Kathryn C. Fisher , Laura L. Kosbar , Christian Lavoie , Zhu Liu , Kenneth P. Rodbell , Xiaoyan Shao
IPC分类号： H01L21/477
CPC分类号： H01L21/28518 , H01L21/76841 , H01L23/53238 , H01L31/022408 , H01L31/022425 , H01L2924/0002 , Y02E10/50 , H01L2924/00
摘要： A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers.
摘要翻译：具有接触结构的半导体器件或光电池，其包括硅（Si）衬底; 沉积在硅衬底上的金属合金层; 金属硅化物层和由金属合金层热退火同时形成的扩散层; 以及沉积在金属硅化物和阻挡层上的金属层。

7. 发明授权

US07877716B2 Computer program products for determining stopping powers of design structures with respect to a traveling particle 有权
标题翻译：用于确定相对于旅行颗粒的设计结构的停止力的计算机程序产品
公开(公告)号：US07877716B2
公开(公告)日：2011-01-25
申请号：US12111529
申请日：2008-04-29
申请人： Giovanni Fiorenza , Conal E. Murray , Kenneth P. Rodbell , Henry Tang
发明人： Giovanni Fiorenza , Conal E. Murray , Kenneth P. Rodbell , Henry Tang
IPC分类号： G06F17/50 , G06F19/00 , G06G7/62
CPC分类号： G06F17/5009 , G06F2217/16
摘要： A computer program product, comprising a computer readable storage device having a computer readable program code stored therein, said program code including an algorithm adapted to be executed by a computer to implement a method. First, design information of a design structure is provided including a back-end-of-line layer of an integrated circuit which includes N interconnect layers, wherein N is a positive integer. Next, each interconnect layer is divided into multiple pixels. Next, a first path of a traveling particle in a first interconnect layer of the N interconnect layers is determined. Next, M path pixels of the multiple pixels of the first interconnect layer on the first path of the traveling particle are identified, wherein M is a positive integer. Next, a first loss energy lost by the traveling particle due to its completely passing through a first pixel of the M path pixels is determined.
摘要翻译：一种计算机程序产品，包括具有存储在其中的计算机可读程序代码的计算机可读存储设备，所述程序代码包括适于由计算机执行以实现方法的算法。首先，提供一种设计结构的设计信息，其包括包括N个互连层的集成电路的后端行层，其中N是正整数。接下来，每个互连层被分成多个像素。接下来，确定N个互连层的第一互连层中的行进粒子的第一路径。接下来，识别行进粒子的第一路径上的第一互连层的多个像素的M个路径像素，其中M是正整数。接下来，确定由于行进粒子完全通过M路径像素的第一像素而损失的第一损失能量。

8. 发明授权

US07649257B2 Discrete placement of radiation sources on integrated circuit devices 有权
标题翻译：辐射源在集成电路设备上的离散放置
公开(公告)号：US07649257B2
公开(公告)日：2010-01-19
申请号：US12051881
申请日：2008-03-20
申请人： Michael S. Gordon , Nancy C. LaBianca , Kenneth P. Rodbell
发明人： Michael S. Gordon , Nancy C. LaBianca , Kenneth P. Rodbell
IPC分类号： H01L23/48
CPC分类号： H01L22/20 , G01R31/2856 , G01R31/2881 , G01R31/31816 , H01L23/556 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/014 , H01L2924/1305 , H01L2924/00
摘要： An integrated circuit and methods of forming and using the integrated circuit. The circuit includes: a radiation-emitting layer over a selected region of a top surface of an integrated circuit chip, the radiation emitting layer comprising a first polymer or resin and a first radioactive material, the region smaller than a whole of the top surface of the integrated circuit chip, the region including a circuit that is liable to temporary failure when struck by radiation generated by the first radioactive material.
摘要翻译：集成电路和集成电路的形成和使用方法。该电路包括：在集成电路芯片的顶表面的选定区域上的辐射发射层，辐射发射层包括第一聚合物或树脂和第一放射性材料，该区域小于整个顶表面的整个面积集成电路芯片，该区域包括当被第一放射性物质产生的辐射撞击时易于暂时失效的电路。

9. 发明申请

US20090236699A1 DISCREET PLACEMENT OF RADIATION SOURCES ON INTEGRATED CIRCUIT DEVICES 有权
标题翻译：集成电路设备上放射源的放置
公开(公告)号：US20090236699A1
公开(公告)日：2009-09-24
申请号：US12051881
申请日：2008-03-20
申请人： Michael S. Gordon , Nancy C. LaBianca , Kenneth P. Rodbell
发明人： Michael S. Gordon , Nancy C. LaBianca , Kenneth P. Rodbell
IPC分类号： H01L23/58 , H01L21/00 , H01L21/66
CPC分类号： H01L22/20 , G01R31/2856 , G01R31/2881 , G01R31/31816 , H01L23/556 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/014 , H01L2924/1305 , H01L2924/00
摘要： An integrated circuit and methods of forming and using the integrated circuit. The circuit includes: a radiation-emitting layer over a selected region of a top surface of an integrated circuit chip, the radiation emitting layer comprising a first polymer or resin and a first radioactive material, the region smaller than a whole of the top surface of the integrated circuit chip, the region including a circuit that is liable to temporary failure when struck by radiation generated by the first radioactive material.
摘要翻译：集成电路和集成电路的形成和使用方法。该电路包括：在集成电路芯片的顶表面的选定区域上的辐射发射层，辐射发射层包括第一聚合物或树脂和第一放射性材料，该区域小于整个顶表面的整个面积集成电路芯片，该区域包括当被第一放射性物质产生的辐射撞击时易于暂时失效的电路。

10. 发明申请

US20090065955A1 METHOD AND STRUCTURES FOR ACCELERATED SOFT-ERROR TESTING 有权
标题翻译：用于加速软错误测试的方法和结构
公开(公告)号：US20090065955A1
公开(公告)日：2009-03-12
申请号：US11852353
申请日：2007-09-10
申请人： Michael S. Gordon , Kenneth P. Rodbell , Henry H. K. Tang
发明人： Michael S. Gordon , Kenneth P. Rodbell , Henry H. K. Tang
IPC分类号： H01L23/48 , G01R31/26 , H01L21/4763
CPC分类号： G01R31/2881 , G01R31/2858 , G01R31/31816 , H01L21/76825 , H01L21/84 , H01L23/53233 , H01L23/53238 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit, method of forming the integrated circuit and a method of testing the integrated circuit for soft-error fails. The integrated circuit includes: a silicon substrate; a dielectric layer formed over the substrate; electrically conductive wires formed in the dielectric layer, the wires interconnecting semiconductor devices formed in the substrate into circuits; and an alpha particle emitting region in the integrated circuit chip proximate to one or more of the semiconductor devices. The method includes exposing the integrated circuit to an artificial flux of thermal neutrons to cause fission of atoms in the alpha particle emitting region into alpha particles and other atoms.
摘要翻译：一种集成电路，形成集成电路的方法以及用于软错误的集成电路测试的方法失败。集成电路包括：硅衬底; 形成在所述基板上的电介质层; 形成在电介质层中的导电线，将形成在基板中的半导体器件互连成电路的导线; 以及靠近一个或多个半导体器件的集成电路芯片中的α粒子发射区域。该方法包括将集成电路暴露于热中子的人造通量，以使α粒子发射区中的原子裂变为α粒子和其它原子。

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