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1. 发明授权

US07116737B2 Apparatus for signaling that a predetermined time value has elapsed 有权
标题翻译：用于发信号通知预定时间值已经过去的装置
公开(公告)号：US07116737B2
公开(公告)日：2006-10-03
申请号：US10253793
申请日：2002-09-24
申请人： Georg Erhard Eggers , Jorg Kliewer , Ralf Schneider , Norbert Wirth
发明人： Georg Erhard Eggers , Jorg Kliewer , Ralf Schneider , Norbert Wirth
IPC分类号： H04L7/00
CPC分类号： G04F1/005 , G11C27/024 , H03K5/08 , H03K5/13 , H03K2005/00247
摘要： The present invention provides an apparatus for signaling that a predetermined time value has elapsed, having a device for acquiring and storing the amplitude value of a clock signal at an acquisition instant in the temporal profile of the clock signal. A device is provided for continuously comparing the acquired and stored amplitude value of the clock signal with an instantaneous amplitude value of the clock signal and for outputting a comparison signal which has a first logic state if the instantaneous amplitude value of the clock signal is less than the stored amplitude value and has a second logic state if the instantaneous amplitude value of the clock signal is greater than the stored amplitude value. A device is also provided for counting the number of logic states of the comparison signal which occur after the acquisition instant, and for signaling that the predetermined time value has elapsed if the counted number of logic states is equal to a predetermined number of logic states which corresponds temporally to the predetermined time value.
摘要翻译：本发明提供了一种信号通知预定时间值已经过去的装置，具有用于在时钟信号的时间分布中获取和存储时钟信号的振幅值的装置。提供一种装置，用于连续地将获取和存储的时钟信号的振幅值与时钟信号的瞬时振幅值进行比较，并且用于输出具有第一逻辑状态的比较信号，如果时钟信号的瞬时振幅值小于存储的振幅值，并且如果时钟信号的瞬时振幅值大于存储的振幅值，则具有第二逻辑状态。还提供了一种装置，用于对在获取时刻之后发生的比较信号的逻辑状态数进行计数，并且用于发出指示如果计数的逻辑状态数等于预定数量的逻辑状态，则预定时间值已经过去在时间上对应于预定时间值。

2. 发明授权

US06940775B2 Integrated dynamic memory having a control circuit for controlling a refresh mode for memory cells 失效
标题翻译：具有用于控制存储器单元的刷新模式的控制电路的集成动态存储器
公开(公告)号：US06940775B2
公开(公告)日：2005-09-06
申请号：US10823608
申请日：2004-04-14
申请人： Ralf Schneider , Manfred Pröll , Georg Erhard Eggers , Jörg Kliewer
发明人： Ralf Schneider , Manfred Pröll , Georg Erhard Eggers , Jörg Kliewer
IPC分类号： G11C8/02 , G11C11/406 , G11C7/00
CPC分类号： G11C11/40626 , G11C11/406 , G11C2211/4061
摘要： An integrated dynamic memory includes memory cells which are combined to form individual independently addressable units, and a control circuit for controlling a refresh mode for the memory cells. The memory cells can have their memory cell content refreshed. The control circuit is designed such that one or more units of memory cells can be subject to a refresh mode in parallel in a refresh cycle. The control circuit sets a number of memory cell units, which are to be refreshed in parallel in a refresh cycle based on a temperature reference value. A maximum possible operating temperature for a memory chip can be increased without additional restrictions on memory access.
摘要翻译：集成动态存储器包括被组合以形成单独的可独立寻址单元的存储单元，以及用于控制存储器单元的刷新模式的控制电路。存储单元可以刷新其存储单元格内容。控制电路被设计成使得一个或多个单元的存储单元可以在更新周期中并行进行刷新模式。控制电路基于温度参考值设置要在刷新周期中并行刷新的多个存储单元单元。可以增加存储器芯片的最大可能工作温度，而不需要对存储器访问的额外限制。

3. 发明申请

US20050248996A1 Integrated circuit for stabilizing a voltage 有权
标题翻译：用于稳定电压的集成电路
公开(公告)号：US20050248996A1
公开(公告)日：2005-11-10
申请号：US11123226
申请日：2005-05-06
申请人： Ralf Schneider , Stephan Schroder , Manfred Proll , Jorg Kliewer
发明人： Ralf Schneider , Stephan Schroder , Manfred Proll , Jorg Kliewer
IPC分类号： G05F1/595 , G11C5/14 , G11C7/00 , G11C11/4074
CPC分类号： G11C11/4074 , G11C5/145
摘要： An integrated circuit includes an input terminal (IN) for application of a supply voltage (Vext) and an output terminal (A) for generation of an output voltage (Vout). A first branch including a first controllable resistance (T1) and a second branch including a charge pump (10) and a second controllable resistance (T2) are connected between the input terminal (IN) and the output terminal (A). A control circuit (20) alters the resistance values of the first and second controllable resistances (T1, T2) in a manner dependent on a ratio of an actual value (Vout) of the output voltage to a desired value (VSout) of the output voltage and a ratio of an actual value (Vext) of the supply voltage to a desired value (VSext) of the supply voltage. As a result, the output voltage (Vout) can be stabilized to the desired value (VSout) virtually independently of fluctuations of the supply voltage.
摘要翻译：集成电路包括用于施加电源电压（Vext）的输入端（IN）和用于产生输出电压（Vout）的输出端子（A）。包括第一可控电阻（T 1）和包括电荷泵（10）和第二可控电阻（T 2）的第二分支的第一分支连接在输入端（IN）和输出端（A）之间。控制电路（20）以取决于输出电压的实际值（Vout）与期望值（VSout）的比值的方式改变第一和第二可控电阻（T 1，T 2）的电阻值输出电压和电源电压的实际值（Vext）与电源电压的期望值（VSext）的比率。结果，输出电压（Vout）可以实际上独立于电源电压的波动而稳定到期望值（VSout）。

4. 发明授权

US06826111B2 On chip scrambling 有权
标题翻译：片上乱码
公开(公告)号：US06826111B2
公开(公告)日：2004-11-30
申请号：US10186327
申请日：2002-06-28
申请人： Ralf Schneider , Evangelos Stavrou , Tobias Hartner , Norbert Wirth
发明人： Ralf Schneider , Evangelos Stavrou , Tobias Hartner , Norbert Wirth
IPC分类号： G11C800
CPC分类号： G11C29/36 , G11C29/18
摘要： A method includes providing a semiconductor memory device having at least one memory cell array. The memory cell array has a multiplicity of memory cells arranged in a matrix-like manner. Each of the memory cells is assigned a physical address and an electrical address. The method also includes inputting a physical address of a memory cell that is to be addressed into an address input device of the semiconductor memory device, decoding the input physical address into the assigned electrical address of the memory cell to be addressed by an address decoder device of the semiconductor memory device, and outputting the electrical address to the memory cell array in order to address the memory cell.
摘要翻译：一种方法包括提供具有至少一个存储单元阵列的半导体存储器件。存储单元阵列具有以矩阵状排列的多个存储单元。每个存储单元被分配一个物理地址和一个电子地址。该方法还包括将要寻址的存储器单元的物理地址输入到半导体存储器件的地址输入设备中，将输入物理地址解码为由地址解码器器件寻址的存储器单元的分配电地址并且将电地址输出到存储单元阵列以便寻址存储单元。

5. 发明授权

US06618303B2 Integrated circuit, test structure and method for testing integrated circuits 有权
公开(公告)号：US06618303B2
公开(公告)日：2003-09-09
申请号：US09929303
申请日：2001-08-13
申请人： Arndt Gruber , Ralf Schneider , Bernhard Ruf , Norbert Wirth
发明人： Arndt Gruber , Ralf Schneider , Bernhard Ruf , Norbert Wirth
IPC分类号： G11C700
CPC分类号： G11C29/006 , G11C2029/2602
摘要： An electronic circuit in an integrated circuit having memory cells is described. The circuit permits information to be written to particular memory cells only once, so that subsequent writing to the particular memory cells is blocked. The circuit is used in a test structure for integrated circuits on a wafer. A method for testing integrated circuits on a wafer that are connected to a test apparatus is also described. Once the supply voltage to a first circuit to be tested has been turned on, a preliminary test is carried out to ascertain parameters that need to be set. The supply voltage is then applied to a next circuit to be tested, a preliminary test is carried out, and memory cells have information written to them, until the parameters have been set for all the connected circuits to be tested. The test apparatus then carries out the actual operational test in parallel for all the connected circuits to be tested.

6. 发明授权

US06556486B2 Circuit configuration and method for synchronization 有权
公开(公告)号：US06556486B2
公开(公告)日：2003-04-29
申请号：US09998725
申请日：2001-11-30
申请人： Herbert Benzinger , Norbert Wirth , Ralf Schneider
发明人： Herbert Benzinger , Norbert Wirth , Ralf Schneider
IPC分类号： G11O1604
CPC分类号： G11C7/1006 , G11C7/22
摘要： A circuit configuration and a method for the synchronization of signals include transmitting signals in parallel through data lines and buffer-storing the signals in a synchronizing unit. A clock signal is determined from the signals of a data line and is used for synchronizing the outputting of the signals. The signals are output in the order in which the signals were read. The signals are likewise output through a plurality of data lines, the signals being output temporally synchronously. Propagation time differences are compensated due to the buffer-storage. Moreover, the clock signal is determined from the signals themselves. Consequently, the use of an additional clock signal is not necessary.

7. 发明授权

US07992426B2 Apparatus and method for increasing the selectivity of FET-based gas sensors 有权
标题翻译：提高基于FET的气体传感器选择性的装置和方法
公开(公告)号：US07992426B2
公开(公告)日：2011-08-09
申请号：US11587171
申请日：2005-04-21
申请人： Maximilian Fleischer , Uwe Lampe , Hans Meixner , Roland Pohle , Ralf Schneider , Elfriede Simon
发明人： Maximilian Fleischer , Uwe Lampe , Hans Meixner , Roland Pohle , Ralf Schneider , Elfriede Simon
IPC分类号： G01N33/00 , G01N27/414
CPC分类号： G01N33/0014 , G01N27/4143
摘要： A FET gas sensor having a relatively low operating temperature, for example, room temperature, is free from cross sensitivities from interfering gases by a preceding in-line filter. The sensor's service life is substantially stabilizable by using fabric-like activated charcoal filters which can be regenerated by a moderate temperature increase, and by limiting the diffusion of the analyte gas, which is made possible by the relatively small amount of gas detectable on the sensitive layer of the sensor. This substantially increases the service life of the filters. The gas sensor eliminates cross sensitivities to thereby increase the detection reliability thereof. Also, the gas sensor has relative long term stability and is economical to build. The gas sensor can read relatively weak signals generated by gas-sensitive layers, for example, without other stronger gas signals interfering with the weak signals.
摘要翻译：具有较低工作温度（例如室温）的FET气体传感器不受前面的在线过滤器的干扰气体的交叉敏感性。传感器的使用寿命通过使用织物样的活性炭过滤器可以基本上稳定，该过滤器可以通过适度的温度升高再生，并且通过限制分析物气体的扩散，这是通过敏感的可检测的相对少量的气体传感器层。这大大增加了过滤器的使用寿命。气体传感器消除了交叉敏感度，从而提高了其检测可靠性。此外，气体传感器具有相对的长期稳定性并且构建经济。气体传感器可以读取由气体敏感层产生的相对较弱的信号，例如，没有其他较强气体信号干扰弱信号。

8. 发明授权

US07772617B2 Gas sensitive field-effect-transistor 有权
标题翻译：气体敏感场效应晶体管
公开(公告)号：US07772617B2
公开(公告)日：2010-08-10
申请号：US11393371
申请日：2006-03-30
申请人： Maximilian Fleischer , Hans Meixner , Uwe Lampe , Roland Pohle , Ralf Schneider , Elfriede Simon
发明人： Maximilian Fleischer , Hans Meixner , Uwe Lampe , Roland Pohle , Ralf Schneider , Elfriede Simon
IPC分类号： G01N27/414
CPC分类号： G01N27/4143
摘要： A gas sensitive field effect transistor comprises a semiconductor substrate that includes a capacitance well, and source and drain regions of a field effect transistor. A gate of the field effect transistor is separated from the semiconductor substrate by an insulator, and a gas sensitive layer separated from the gate by an air gap. The field effect transistor provides an output signal indicative of the presence of a target gas within the air gap to an amplifier, which provides an amplified output signal that is electrically coupled to the capacitance well.
摘要翻译：气体敏感场效应晶体管包括包括电容阱的半导体衬底以及场效应晶体管的源极和漏极区。场效应晶体管的栅极通过绝缘体与半导体衬底分离，气敏层由气隙与栅极分离。场效应晶体管提供指示空气间隙内存在目标气体到放大器的输出信号，放大器提供与电容阱电耦合的放大输出信号。

9. 发明授权

US07224627B2 Integrated semiconductor circuit and method for testing the same 有权
标题翻译：集成半导体电路及其测试方法
公开(公告)号：US07224627B2
公开(公告)日：2007-05-29
申请号：US11100617
申请日：2005-04-07
申请人： Marcin Gnat , Aurel von Campenhausen , Joerg Vollrath , Ralf Schneider
发明人： Marcin Gnat , Aurel von Campenhausen , Joerg Vollrath , Ralf Schneider
IPC分类号： G11C7/00
CPC分类号： G11C29/12005 , G11C29/12
摘要： Integrated semiconductor circuits, in particular, dynamic random access memories include a multiplicity of generator circuits for generating internal voltage levels from an externally applied supply voltage. During testing, the internal voltage levels are altered by the output voltage generated at the output of the generator circuit being adapted to an externally applied test voltage. If the test voltage is outside a tolerance range, the semiconductor circuit maybe destroyed. A protection circuit connected in parallel with the generator circuit limits the output voltage.
摘要翻译：集成半导体电路，特别是动态随机存取存储器包括用于从外部施加的电源电压产生内部电压电平的多个发生器电路。在测试期间，内部电压电平由发生器电路输出端产生的输出电压改变为外部施加的测试电压。如果测试电压超出公差范围，则半导体电路可能被破坏。与发生器电路并联连接的保护电路限制输出电压。

10. 发明申请

US20060120176A1 Integrated semiconductor memory with test circuit 有权
标题翻译：具有测试电路的集成半导体存储器
公开(公告)号：US20060120176A1
公开(公告)日：2006-06-08
申请号：US11235540
申请日：2005-09-27
申请人： Ralf Schneider , Stephan Schroder , Manfred Proll , Herbert Benzinger
发明人： Ralf Schneider , Stephan Schroder , Manfred Proll , Herbert Benzinger
IPC分类号： G11C7/06
CPC分类号： G11C29/025 , G11C8/08 , G11C11/401 , G11C29/02 , G11C2029/1202
摘要： An integrated semiconductor memory includes word lines connected to a first voltage potential via a respective first controllable switch and a respective third controllable switch and to a second voltage potential via a respective second controllable switch. In order to test whether one of the word lines is connected to the first voltage potential via its respective first and third controllable switches, the one of the word lines is connected to a comparator circuit via the respective second controllable switch and a driver line. After the respective first and third controllable switches have been controlled into the on state, in a test operating state of the integrated semiconductor memory, the respective second controllable switch is controlled into the on state and a potential state on the word line is evaluated by the comparator circuit. The result of the evaluation is fed to an external data terminal by an evaluation signal.
摘要翻译：集成半导体存储器包括通过相应的第一可控开关和相应的第三可控开关连接到第一电压电位的字线，以及经由相应的第二可控开关连接到第二电压电位的字线。为了测试字线之一是否经由其相应的第一和第三可控开关连接到第一电压电位，所述字线之一经由相应的第二可控开关和驱动器线连接到比较器电路。在相应的第一和第三可控开关已经被控制为导通状态之后，在集成半导体存储器的测试操作状态下，将相应的第二可控开关控制在导通状态，并且字线上的电位状态由比较器电路。评估结果通过评估信号馈送到外部数据终端。

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