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1. 发明申请

US20060120176A1 Integrated semiconductor memory with test circuit 有权
标题翻译：具有测试电路的集成半导体存储器
公开(公告)号：US20060120176A1
公开(公告)日：2006-06-08
申请号：US11235540
申请日：2005-09-27
申请人： Ralf Schneider , Stephan Schroder , Manfred Proll , Herbert Benzinger
发明人： Ralf Schneider , Stephan Schroder , Manfred Proll , Herbert Benzinger
IPC分类号： G11C7/06
CPC分类号： G11C29/025 , G11C8/08 , G11C11/401 , G11C29/02 , G11C2029/1202
摘要： An integrated semiconductor memory includes word lines connected to a first voltage potential via a respective first controllable switch and a respective third controllable switch and to a second voltage potential via a respective second controllable switch. In order to test whether one of the word lines is connected to the first voltage potential via its respective first and third controllable switches, the one of the word lines is connected to a comparator circuit via the respective second controllable switch and a driver line. After the respective first and third controllable switches have been controlled into the on state, in a test operating state of the integrated semiconductor memory, the respective second controllable switch is controlled into the on state and a potential state on the word line is evaluated by the comparator circuit. The result of the evaluation is fed to an external data terminal by an evaluation signal.
摘要翻译：集成半导体存储器包括通过相应的第一可控开关和相应的第三可控开关连接到第一电压电位的字线，以及经由相应的第二可控开关连接到第二电压电位的字线。为了测试字线之一是否经由其相应的第一和第三可控开关连接到第一电压电位，所述字线之一经由相应的第二可控开关和驱动器线连接到比较器电路。在相应的第一和第三可控开关已经被控制为导通状态之后，在集成半导体存储器的测试操作状态下，将相应的第二可控开关控制在导通状态，并且字线上的电位状态由比较器电路。评估结果通过评估信号馈送到外部数据终端。

2. 发明申请

US20050249002A1 Integrated semiconductor memory 有权
标题翻译：集成半导体存储器
公开(公告)号：US20050249002A1
公开(公告)日：2005-11-10
申请号：US11123221
申请日：2005-05-06
申请人： Jurgen Auge , Manfred Proll , Jorg Kliewer , Frank Schroeppel
发明人： Jurgen Auge , Manfred Proll , Jorg Kliewer , Frank Schroeppel
IPC分类号： G11C7/00 , G11C29/00 , G11C29/48
CPC分类号： G11C29/48
摘要： An integrated semiconductor memory includes a memory cell array with at least one memory cell, in which a data value is stored, and an evaluation circuit with a counter. During a test of the integrated semiconductor memory, a counter reading of the counter is altered if the data value stored in the memory cell deviates from a desired value. A threshold value is predefined by a control circuit. A programming circuit compares the threshold value on the input side with the instantaneous counter reading of the counter. If the counter reading of the counter exceeds the threshold value, a programming element changes from a first programming state to a second programming state. After the conclusion of the test, the state of the programming element is read out via an output terminal. This scheme makes it possible to deduce a possible cause of failure of the integrated semiconductor memory.
摘要翻译：集成半导体存储器包括具有存储有数据值的至少一个存储单元的存储单元阵列和具有计数器的评估电路。在集成半导体存储器的测试期间，如果存储在存储单元中的数据值偏离期望值，则计数器的计数器读数被改变。阈值由控制电路预先定义。编程电路将输入侧的阈值与计数器的瞬时计数器读数进行比较。如果计数器的计数器读数超过阈值，则编程元件从第一编程状态变为第二编程状态。在测试结束之后，通过输出端读出编程元件的状态。该方案可以推断集成半导体存储器的可能的故障原因。

3. 发明申请

US20050041519A1 Integrated clock supply chip for a memory module, memory module comprising the integrated clock supply chip, and method for operating the memory module under test conditions 有权
标题翻译：用于存储器模块的集成时钟供应芯片，包括集成时钟供应芯片的存储器模块以及用于在测试条件下操作存储器模块的方法
公开(公告)号：US20050041519A1
公开(公告)日：2005-02-24
申请号：US10886523
申请日：2004-07-07
申请人： Nazif Taskin , Manfred Proll , Manfred Dobler , Gerald Resch
发明人： Nazif Taskin , Manfred Proll , Manfred Dobler , Gerald Resch
IPC分类号： G11C7/22 , G11C11/4076 , G11C29/14 , G11C8/18
CPC分类号： G11C29/12015 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C29/14
摘要： The integrated chip according to the invention has a clock signal input (1.1) for application of a first clock signal (clk1) and a clock signal output (1.2-1.5). Moreover, it has a phase locked loop (2), which, on the input side, is connected to the clock signal input (1.1) and serves for generating a second clock signal (clk2). Furthermore, the chip has a multiplexer (MUX), via which the first clock signal (clk1) or the second clock signal (clk2) can optionally be switched to the clock signal output (1.2-1.5), and a unit for frequency monitoring (3), which, on the input side, is connected to the clock signal input (1.1) and is designed and can be operated in such a way that, in the event of a limiting frequency (fmin) being undershot, the multiplexer (MUX) is caused to switch the first clock signal (clk1) to the clock signal output (1.2-1.5).
摘要翻译：根据本发明的集成芯片具有用于施加第一时钟信号（clk1）和时钟信号输出（1.2-1.5）的时钟信号输入（1.1）。此外，它具有锁相环（2），其在输入侧连接到时钟信号输入端（1.1）并用于产生第二时钟信号（clk2）。此外，芯片具有多路复用器（MUX），第一时钟信号（clk1）或第二时钟信号（clk2）可以选择地切换到时钟信号输出（1.2-1.5），以及用于频率监视的单元 3），其在输入侧连接到时钟信号输入（1.1），并且被设计并且可以以这样的方式操作，使得在频率（fmin）不足的情况下，多路复用器（MUX ）将第一个时钟信号（clk1）切换到时钟信号输出（1.2-1.5）。

4. 发明申请

US20060193168A1 Integrated semiconductor memory and method for operating a semiconductor memory 失效
标题翻译：用于操作半导体存储器的集成半导体存储器和方法
公开(公告)号：US20060193168A1
公开(公告)日：2006-08-31
申请号：US11331365
申请日：2006-01-13
申请人： Stephan Schroder , Herbert Benzinger , Georg Eggers , Manfred Proll , Jorg Kliewer
发明人： Stephan Schroder , Herbert Benzinger , Georg Eggers , Manfred Proll , Jorg Kliewer
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/404 , H01L27/10885
摘要： An integrated semiconductor memory device includes memory cells each with a selection transistor and a storage capacitor. Memory cells of this type are usually read by the potential of the bit line to which the memory cell is connected being compared in a sense amplifier with the potential of a complementary, second bit line and a voltage difference identified being amplified. The semiconductor memory according to the invention provides for that capacitor electrode which is not connected to the selection transistor to be connected to the complementary, second bit line. As a result, for an operating voltage with the same magnitude, larger quantities of charge can be stored in the storage capacitor since now the two mutually spread potentials output by the sense amplifier are used for biasing the storage capacitor. The resultant increase in the signal strength makes the semiconductor memory insensitive toward signal corruptions which arise for example in the case of operating voltages at different levels for selection transistors and for transistors in the signal amplifier.
摘要翻译：集成半导体存储器件包括各自具有选择晶体管和存储电容器的存储单元。这种类型的存储单元通常通过读出放大器中与存储器单元连接的位线的电位进行读取，其中互补的第二位线的电位和识别的电压差被放大。根据本发明的半导体存储器提供了未连接到选择晶体管以连接到互补的第二位线的电容器电极。结果，对于具有相同幅度的工作电压，由于现在由读出放大器输出的两个相互扩展的电位用于偏置存储电容器，所以可以将大量的电荷存储在存储电容器中。信号强度的增加使得半导体存储器对信号损坏不敏感，例如在用于选择晶体管的不同电平的操作电压和信号放大器中的晶体管的情况下。

5. 发明申请

US20050018507A1 Circuit and method for controlling an access to an integrated memory 失效
标题翻译：用于控制对集成存储器的访问的电路和方法
公开(公告)号：US20050018507A1
公开(公告)日：2005-01-27
申请号：US10892251
申请日：2004-07-16
申请人： Stephan Schroder , Aurel Campenhausen , Manfred Proll , Koen Zanden
发明人： Stephan Schroder , Aurel Campenhausen , Manfred Proll , Koen Zanden
IPC分类号： G11C7/10 , G11C7/12 , G11C11/4094 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/109 , G11C7/04 , G11C7/1078 , G11C7/12 , G11C11/4094 , G11C11/4096
摘要： A circuit for controlling an access to an integrated memory includes a command decoder for receiving at least one external command for an access to the memory. An access controller is connected to the command decoder for receiving internal command signals, which are output by the command decoder. In the course of a memory access, the command decoder outputs a precharge command signal for precharging a row of the memory cell array of the integrated memory. A control circuit, which can determine a temperature of the memory, is designed to temporally variably influence the transmission of the precharge command signal of the command decoder to the access controller in a manner dependent on the temperature of the memory. The write recovery time tWR can be retained even for higher operating frequencies of the memory.
摘要翻译：用于控制对集成存储器的访问的电路包括命令解码器，用于接收至少一个外部命令以访问存储器。访问控制器连接到命令解码器，用于接收由命令解码器输出的内部命令信号。在存储器访问的过程中，命令解码器输出用于对集成存储器的存储单元阵列的行进行预充电的预充电命令信号。可以确定存储器的温度的控制电路被设计为以取决于存储器的温度的方式在时间上可变地影响命令解码器的预充电命令信号到访问控制器的传输。即使对于存储器的较高工作频率，也可以保留写恢复时间tWR。

6. 发明授权

US4810178A Apparatus for molding outer and inner soles onto shoe uppers 失效
标题翻译：用于将外鞋底和内鞋底成型到鞋面上的装置
公开(公告)号：US4810178A
公开(公告)日：1989-03-07
申请号：US116666
申请日：1987-11-04
申请人： Manfred Proll , Gunter Rebers
发明人： Manfred Proll , Gunter Rebers
IPC分类号： B29D35/08 , B29C45/16
CPC分类号： B29D35/082 , B29D35/087
摘要： An apparatus for molding an outer sole of elastomer and an inner sole of a mixture of isocyanate and a polyol reacting into polyurethane to shoe uppers includes a vertically movable upper cross block supporting a pivotably mounted mold carrier with a heatable first mold part at one end for the molding of outer soles, and a lower, vertically adjustable cross block has a heatable plate in contact with the first mold part. The mold carrier is pivoted such that the heatable first mold part containing the molded outer sole forms a mold cavity for an inner sole together with laterally movable mold elements and a last supported shoe upper. A vertically adjustable last body has a transfer plate which transfers the molded outer sole from the heatable first mold part for cooling before the molded outer sole is transferred back to a cooled mold part at the opposite end of the mold carrier, after which the last supported shoe upper is rotated to confront the outer sole and the lateral mold elements are closed to define a cavity for the molding of the inner sole.
摘要翻译：用于模制弹性体外底的装置和反应成聚氨酯至鞋面的异氰酸酯和多元醇的混合物的内底的装置包括可垂直运动的上横向块，其支撑可枢转地安装的模具架，其一端具有可加热的第一模具部件外底的成型和下部可垂直调节的交叉块具有与第一模具部分接触的可加热板。模具托架枢转，使得包含模制的外底的可加热的第一模具部件与侧向可移动的模具元件和最后支撑的鞋面形成用于内底的模腔。可垂直调节的最后一个主体具有转印板，该转印板将模制的外底从可加热的第一模具部件转移以进行冷却，然后将模制的外底转移回模具架的相对端处的冷却的模具部件，之后最后支撑鞋面被旋转以面对外底，并且侧模元件被关闭以限定用于内底的模制的空腔。

7. 发明申请

US20070247944A1 Integrated Semiconductor Memory with Refreshing of Memory Cells 审中-公开
标题翻译：集成半导体存储器与内存单元刷新
公开(公告)号：US20070247944A1
公开(公告)日：2007-10-25
申请号：US11739444
申请日：2007-04-24
申请人： Frank Fischer , Manfred Proll , Thilo Schaffroth , Stephan Schroder
发明人： Frank Fischer , Manfred Proll , Thilo Schaffroth , Stephan Schroder
IPC分类号： G11C11/34 , G11C7/04 , G11C7/00
CPC分类号： G11C7/04 , G11C11/406 , G11C11/40626 , G11C29/028 , G11C2029/5002 , G11C2211/4061
摘要： An integrated semiconductor memory with refreshing of memory cells includes a temperature sensor to detect a chip temperature of the integrated semiconductor memory, a connection to apply a command signal, a frequency generation unit to generate a frequency signal, and a memory cell to store a data item, the stored data item being refreshed at the frequency of the frequency signal. The frequency generation unit generates the frequency signal at a first frequency on the basis of a chip temperature detected by the temperature sensor when a first state of the command signal is applied and the frequency generation unit generates the frequency signal at a second frequency, which is changed in comparison with the first frequency, at the same chip temperature when a second state of the command signal is applied.
摘要翻译：具有刷新存储单元的集成半导体存储器包括用于检测集成半导体存储器的芯片温度的温度传感器，应用命令信号的连接，产生频率信号的频率产生单元和用于存储数据的存储单元项目，以频率信号的频率刷新存储的数据项。当施加指令信号的第一状态时，频率产生单元基于由温度传感器检测到的芯片温度，以第一频率产生频率信号，并且频率产生单元以第二频率产生频率信号在施加命令信号的第二状态时，以相同的芯片温度与第一频率相比变化。

8. 发明授权

US4960374A Apparatus for molding outer and inner soles and a sole welt onto shoe uppers 失效
标题翻译：用于成型外鞋底和鞋底的鞋底和鞋底上的鞋底
公开(公告)号：US4960374A
公开(公告)日：1990-10-02
申请号：US340270
申请日：1989-04-19
申请人： Manfred Proll
发明人： Manfred Proll
IPC分类号： B29D35/00 , B29C45/14 , B29D35/08 , B29K105/20 , B29L31/50
CPC分类号： B29D35/082
摘要： Outer and inner soles and a sole welt are molded onto shoe uppers. A molded outer sole is formed by injection molding plasticized thermoplastic material into a first mold cavity defined by a first mold part at an end of a pivotable mold carrier and a confronting mold plate. A molded sole welt closed on itself is formed on a last supported shoe upper by injection molding plasticized thermoplastic material into a sole welt mold cavity defined by an opposed pair of first lateral mold elements closed against the shoe upper while a second mold part at an opposite end of the mold carrier confronts the shoe upper and the lateral mold elements. The mold carrier is shifted away from the lateral mold elements and pivoted to confront the first mold part and the molded outer sole to the shoe upper. An inner sole mold cavity is formed with the molded outer sole by closing an opposed pair of second lateral mold elements located between the first lateral elements and the first mold part. A molded inner sole is formed by injection molding foamed plasticized thermoplastic material into the inner sole mold cavity. The molded outer sole may be formed by separately injection molding plasticized thermoplastic material into portions of the first mold cavity during first and second steps of the first molding cycle.
摘要翻译：外鞋底和鞋底均匀地镶嵌在鞋面上。通过将可塑化的热塑性材料注塑成由可枢转模具托架的端部和相对的模具板的第一模具部件限定的第一模具腔体而形成模制的外底部。通过将增塑的热塑性材料注射成型而成的鞋底边缘模腔中，在最后一个支撑的鞋面上形成一个封闭的模制底部边缘，该底部边缘模具腔由相对的一对第一侧向模具元件限定，模具承载件的端部面对鞋面和侧面模具元件。模具托架从侧面模具元件移开并且枢转以面对第一模具部件和模制的外底部到鞋面。通过闭合位于第一侧向元件和第一模具部件之间的相对的一对第二侧模元件，形成具有模制的外底的内单模模腔。通过将泡沫塑化的热塑性材料注塑成内层模具腔形成模制内底。模制的外底可以通过在第一模制周期的第一和第二步骤期间将增塑的热塑性材料分别注塑成第一模腔的部分而形成。

9. 发明申请

US20050249016A1 Method for testing an integrated semiconductor memory 有权
标题翻译：用于测试集成半导体存储器的方法
公开(公告)号：US20050249016A1
公开(公告)日：2005-11-10
申请号：US11121175
申请日：2005-05-04
申请人： Koen van Zanden , Manfred Proll , Jorg Kliewer , Bjorn Wirker
发明人： Koen van Zanden , Manfred Proll , Jorg Kliewer , Bjorn Wirker
IPC分类号： G11C7/12 , G11C8/00 , G11C11/4091 , G11C29/00 , G11C29/50
CPC分类号： G11C29/50 , G11C11/401 , G11C29/12015 , G11C29/50012 , G11C2029/1204 , G11C2029/2602
摘要： An integrated semiconductor memory can be operated in a normal operating state synchronously with a control clock. In the test operating state, the integrated semiconductor memory is driven synchronously with a clock edge of the control clock with a first control signal and starts a test run independent of the control clock. Driving with the first control signal, selection transistors in a memory bank that can be selected by a memory bank address are turned off. Afterward, bit lines in the selected memory bank are interconnected and driven with a predetermined precharge potential. After a precharge time has elapsed, one of the word lines is selected by an applied word line address and the selection transistors in the selected memory bank connected to the selected word line are turned on. Precharge times are set and tested independently of the clock period of the control clock.
摘要翻译：集成半导体存储器可以在与控制时钟同步的正常操作状态下操作。在测试操作状态下，集成半导体存储器与第一控制信号的控制时钟的时钟边沿同步地驱动，并独立于控制时钟启动测试运行。利用第一控制信号驱动，可以由存储体地址选择的存储体中的选择晶体管截止。之后，所选择的存储体中的位线被互连并以预定的预充电势驱动。在预充电时间过去之后，通过应用的字线地址选择一个字线，并且连接到所选字线的所选存储体中的选择晶体管导通。独立于控制时钟的时钟周期设置和测试预充电时间。

10. 发明申请

US20050248996A1 Integrated circuit for stabilizing a voltage 有权
标题翻译：用于稳定电压的集成电路
公开(公告)号：US20050248996A1
公开(公告)日：2005-11-10
申请号：US11123226
申请日：2005-05-06
申请人： Ralf Schneider , Stephan Schroder , Manfred Proll , Jorg Kliewer
发明人： Ralf Schneider , Stephan Schroder , Manfred Proll , Jorg Kliewer
IPC分类号： G05F1/595 , G11C5/14 , G11C7/00 , G11C11/4074
CPC分类号： G11C11/4074 , G11C5/145
摘要： An integrated circuit includes an input terminal (IN) for application of a supply voltage (Vext) and an output terminal (A) for generation of an output voltage (Vout). A first branch including a first controllable resistance (T1) and a second branch including a charge pump (10) and a second controllable resistance (T2) are connected between the input terminal (IN) and the output terminal (A). A control circuit (20) alters the resistance values of the first and second controllable resistances (T1, T2) in a manner dependent on a ratio of an actual value (Vout) of the output voltage to a desired value (VSout) of the output voltage and a ratio of an actual value (Vext) of the supply voltage to a desired value (VSext) of the supply voltage. As a result, the output voltage (Vout) can be stabilized to the desired value (VSout) virtually independently of fluctuations of the supply voltage.
摘要翻译：集成电路包括用于施加电源电压（Vext）的输入端（IN）和用于产生输出电压（Vout）的输出端子（A）。包括第一可控电阻（T 1）和包括电荷泵（10）和第二可控电阻（T 2）的第二分支的第一分支连接在输入端（IN）和输出端（A）之间。控制电路（20）以取决于输出电压的实际值（Vout）与期望值（VSout）的比值的方式改变第一和第二可控电阻（T 1，T 2）的电阻值输出电压和电源电压的实际值（Vext）与电源电压的期望值（VSext）的比率。结果，输出电压（Vout）可以实际上独立于电源电压的波动而稳定到期望值（VSout）。

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