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1. 发明授权

US08400854B2 Identifying at-risk data in non-volatile storage 有权
标题翻译：识别非易失性存储中的风险数据
公开(公告)号：US08400854B2
公开(公告)日：2013-03-19
申请号：US12694118
申请日：2010-01-26
申请人： Gen Pei , Lanlan Gu , Nima Mokhlesi , Idan Alrod , Eran Sharon , Itshak Afriat
发明人： Gen Pei , Lanlan Gu , Nima Mokhlesi , Idan Alrod , Eran Sharon , Itshak Afriat
IPC分类号： G11C29/04 , G11C29/06
CPC分类号： G11C16/3418 , G06F11/1072
摘要： The non-volatile storage system predicts which blocks (or other units of storage) will become bad based on performance data. User data in those blocks predicted to become bad can be re-programmed to other blocks, and the blocks predicted to become bad can be removed from further use.
摘要翻译：非易失性存储系统基于性能数据预测哪些块（或其他存储单元）将变坏。预测为坏的那些块中的用户数据可以被重新编程到其他块，并且预测为坏的块可以被进一步使用。

2. 发明申请

US20110063918A1 IDENTIFYING AT-RISK DATA IN NON-VOLATILE STORAGE 有权
标题翻译：在非易失性存储中识别风险数据
公开(公告)号：US20110063918A1
公开(公告)日：2011-03-17
申请号：US12694118
申请日：2010-01-26
申请人： Gen Pei , Lanlan Gu , Nima Mokhlesi , Idan Alrod , Eran Sharon , Itshak Afriat
发明人： Gen Pei , Lanlan Gu , Nima Mokhlesi , Idan Alrod , Eran Sharon , Itshak Afriat
IPC分类号： G11C16/04 , G11C29/00
CPC分类号： G11C16/3418 , G06F11/1072
摘要： The non-volatile storage system predicts which blocks (or other units of storage) will become bad based on performance data. User data in those blocks predicted to become bad can be re-programmed to other blocks, and the blocks predicted to become bad can be removed from further use.
摘要翻译：非易失性存储系统基于性能数据预测哪些块（或其他存储单元）将变坏。预测为坏的那些块中的用户数据可以被重新编程到其他块，并且预测为坏的块可以被进一步使用。

3. 发明授权

US08498152B2 Non-volatile memory and methods with soft-bit reads while reading hard bits with compensation for coupling 有权
标题翻译：非易失性存储器和具有软位读取的方法，同时读取具有补偿补偿的硬比特
公开(公告)号：US08498152B2
公开(公告)日：2013-07-30
申请号：US12978368
申请日：2010-12-23
申请人： Idan Alrod , Eran Sharon , Toru Miwa , Gerrit Jan Hemink , Nima Mokhlesi
发明人： Idan Alrod , Eran Sharon , Toru Miwa , Gerrit Jan Hemink , Nima Mokhlesi
IPC分类号： G11C11/34
CPC分类号： G11C16/34 , G06F11/1072 , G11C11/5642 , G11C16/26 , G11C16/3422 , G11C16/3427 , G11C29/00
摘要： A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. Hard bits are obtained when read relative to the first set of reference thresholds. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The soft bits are generated by a combination of a first modulation of voltage on a current word line WLn and a second modulation of voltage on an adjacent word line WLn+1, as in a reading scheme known as “Direct-Lookahead (DLA)”.
摘要翻译：非易失性存储器的单元的阈值被编程在跨越阈值窗口的第一组参考阈值划分的第一组电压带的任一个中。当读取相对于第一组参考阈值时，获得硬比特。相对于第二组参考阈值以更高的分辨率读取单元，以便提供用于纠错的附加软比特。软位是通过对当前字线WLn上的电压的第一次调制和相邻字线WLn + 1上的电压的第二调制的组合产生的，如在称为“直读先锋（DLA）”的读取方案中。

4. 发明申请

US20120163085A1 Non-Volatile Memory And Methods With Soft-Bit Reads While Reading Hard Bits With Compensation For Coupling 有权
标题翻译：非易失性存储器和方法在读取带有补偿补偿的硬位读取软位
公开(公告)号：US20120163085A1
公开(公告)日：2012-06-28
申请号：US12978368
申请日：2010-12-23
申请人： Idan Alrod , Eran Sharon , Toru Miwa , Gerrit Jan Hemink , Nima Mokhlesi
发明人： Idan Alrod , Eran Sharon , Toru Miwa , Gerrit Jan Hemink , Nima Mokhlesi
IPC分类号： G11C16/26
CPC分类号： G11C16/34 , G06F11/1072 , G11C11/5642 , G11C16/26 , G11C16/3422 , G11C16/3427 , G11C29/00
摘要： A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. Hard bits are obtained when read relative to the first set of reference thresholds. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The soft bits are generated by a combination of a first modulation of voltage on a current word line WLn and a second modulation of voltage on an adjacent word line WLn+1, as in a reading scheme known as “Direct-Lookahead (DLA)”.
摘要翻译：非易失性存储器的单元的阈值被编程在跨越阈值窗口的第一组参考阈值划分的第一组电压带的任一个中。当读取相对于第一组参考阈值时，获得硬比特。相对于第二组参考阈值以更高的分辨率读取单元，以便提供用于纠错的附加软比特。软位是通过对当前字线WLn上的电压的第一次调制和相邻字线WLn + 1上的电压的第二调制的组合产生的，如在称为“直读先锋（DLA）”的读取方案中。

5. 发明申请

US20110235420A1 SIMULTANEOUS MULTI-STATE READ OR VERIFY IN NON-VOLATILE STORAGE 有权
标题翻译：在非易失性存储中同时进行多状态读取或验证
公开(公告)号：US20110235420A1
公开(公告)日：2011-09-29
申请号：US12732121
申请日：2010-03-25
申请人： Eran Sharon , Yan Li , Nima Mokhlesi
发明人： Eran Sharon , Yan Li , Nima Mokhlesi
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3459 , G11C11/5642 , G11C16/0483 , G11C16/3454 , G11C2211/5624 , G11C2211/5631
摘要： Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time.
摘要翻译：公开了用于同时验证或读取非易失性存储器中的多个状态的方法和装置。公开了用于有效地减少或消除非易失性存储器中的交叉耦合效应的方法和装置。公开了用于有效执行多个电压读取以搜索存储器单元的阈值电压的方法和装置。可以在不同的NAND串上同时读取的存储单元测试不同的阈值电压电平。可以通过对不同阈值电压进行测试的存储器单元施加不同的栅极至源极电压来对不同的阈值电压测试存储器单元。可以通过对存储器单元施加不同的漏极到源极电压来对不同的阈值电压测试存储器单元。交叉耦合影响的不同量的补偿可以应用于同时读取或编程的不同NAND串上的存储单元。

6. 发明授权

US08509000B2 Simultaneous multi-state read or verify in non-volatile storage 有权
标题翻译：在非易失性存储中同时进行多状态读取或验证
公开(公告)号：US08509000B2
公开(公告)日：2013-08-13
申请号：US13491166
申请日：2012-06-07
申请人： Eran Sharon , Yan Li , Nima Mokhlesi
发明人： Eran Sharon , Yan Li , Nima Mokhlesi
IPC分类号： G11C16/04
CPC分类号： G11C16/3459 , G11C11/5642 , G11C16/0483 , G11C16/3454 , G11C2211/5624 , G11C2211/5631
摘要： Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time.
摘要翻译：公开了用于同时验证或读取非易失性存储器中的多个状态的方法和装置。公开了用于有效地减少或消除非易失性存储器中的交叉耦合效应的方法和装置。公开了用于有效执行多个电压读取以搜索存储器单元的阈值电压的方法和装置。可以在不同的NAND串上同时读取的存储单元测试不同的阈值电压电平。可以通过对不同阈值电压进行测试的存储器单元施加不同的栅极至源极电压来对不同阈值电压进行存储单元的测试。可以通过对存储器单元施加不同的漏极到源极电压来对不同的阈值电压测试存储器单元。交叉耦合影响的不同量的补偿可以应用于同时读取或编程的不同NAND串上的存储单元。

7. 发明申请

US20120250415A1 SIMULTANEOUS MULTI-STATE READ OR VERIFY IN NON-VOLATILE STORAGE 有权
标题翻译：在非易失性存储中同时进行多状态读取或验证
公开(公告)号：US20120250415A1
公开(公告)日：2012-10-04
申请号：US13491166
申请日：2012-06-07
申请人： Eran Sharon , Yan Li , Nima Mokhlesi
发明人： Eran Sharon , Yan Li , Nima Mokhlesi
IPC分类号： G11C16/04
CPC分类号： G11C16/3459 , G11C11/5642 , G11C16/0483 , G11C16/3454 , G11C2211/5624 , G11C2211/5631
摘要： Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time.
摘要翻译：公开了用于同时验证或读取非易失性存储器中的多个状态的方法和装置。公开了用于有效地减少或消除非易失性存储器中的交叉耦合效应的方法和装置。公开了用于有效执行多个电压读取以搜索存储器单元的阈值电压的方法和装置。可以在不同的NAND串上同时读取的存储单元测试不同的阈值电压电平。可以通过对不同阈值电压进行测试的存储器单元施加不同的栅极至源极电压来对不同的阈值电压测试存储器单元。可以通过对存储器单元施加不同的漏极到源极电压来对不同的阈值电压测试存储器单元。交叉耦合影响的不同量的补偿可以应用于同时读取或编程的不同NAND串上的存储单元。

8. 发明授权

US08233324B2 Simultaneous multi-state read or verify in non-volatile storage 有权
标题翻译：在非易失性存储中同时进行多状态读取或验证
公开(公告)号：US08233324B2
公开(公告)日：2012-07-31
申请号：US12732121
申请日：2010-03-25
申请人： Eran Sharon , Yan Li , Nima Mokhlesi
发明人： Eran Sharon , Yan Li , Nima Mokhlesi
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3459 , G11C11/5642 , G11C16/0483 , G11C16/3454 , G11C2211/5624 , G11C2211/5631
摘要： Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time.
摘要翻译：公开了用于同时验证或读取非易失性存储器中的多个状态的方法和装置。公开了用于有效地减少或消除非易失性存储器中的交叉耦合效应的方法和装置。公开了用于有效执行多个电压读取以搜索存储器单元的阈值电压的方法和装置。可以在不同的NAND串上同时读取的存储单元测试不同的阈值电压电平。可以通过对不同阈值电压进行测试的存储器单元施加不同的栅极至源极电压来对不同的阈值电压测试存储器单元。可以通过对存储器单元施加不同的漏极到源极电压来对不同的阈值电压测试存储器单元。交叉耦合影响的不同量的补偿可以应用于同时读取或编程的不同NAND串上的存储单元。

9. 发明授权

US08468424B2 Method for decoding data in non-volatile storage using reliability metrics based on multiple reads 有权
标题翻译：使用基于多个读取的可靠性度量来解码非易失性存储器中的数据的方法
公开(公告)号：US08468424B2
公开(公告)日：2013-06-18
申请号：US13024676
申请日：2011-02-10
申请人： Nima Mokhlesi , Henry Chin , Dengtao Zhao
发明人： Nima Mokhlesi , Henry Chin , Dengtao Zhao
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F12/00 , G11C11/5642 , G11C16/04 , G11C16/28 , G11C29/00 , G11C29/02 , G11C29/028 , H03M13/11 , H03M13/37
摘要： Data stored in non-volatile storage is decoded using iterative probabilistic decoding and multiple read operations to achieve greater reliability. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding read data of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. If convergence does not occur, e.g., within a set time period, the state of the non-volatile storage element is sensed again, current values of the reliability metrics in the decoder are adjusted, and the decoding again attempts to converge.
摘要翻译：使用迭代概率解码和多次读取操作来解码存储在非易失性存储器中的数据，以实现更高的可靠性。可以使用诸如低密度奇偶校验码的纠错码。在一种方法中，初始可靠性度量（诸如对数似然比）被用于解码一组非易失性存储元件的读取数据。解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。如果没有发生收敛，例如在设定的时间周期内，再次感测到非易失性存储元件的状态，则调整解码器中的可靠性度量的当前值，并且解码再次尝试收敛。

10. 发明授权

US08368137B2 Dual bit line metal layers for non-volatile memory 有权
标题翻译：用于非易失性存储器的双位线金属层
公开(公告)号：US08368137B2
公开(公告)日：2013-02-05
申请号：US11768468
申请日：2007-06-26
申请人： Nima Mokhlesi , Jun Wan
发明人： Nima Mokhlesi , Jun Wan
IPC分类号： H01L29/788
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1006 , G11C7/18 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4ƒpitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are formed between each of the bit lines on each metal layer.
摘要翻译：公开了用于在非易失性存储系统中减少位线到位线电容的结构和技术。位线在两个分离的金属层中的每一个中以4fpitch形成，并且布置成在每个层之间交替。在替代实施例中，在每个金属层上的每个位线之间形成屏蔽。

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