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1. 发明授权

US5908310A Method to form a buried implanted plate for DRAM trench storage capacitors 失效
标题翻译：形成用于DRAM沟槽存储电容器的埋入式植入板的方法
公开(公告)号：US5908310A
公开(公告)日：1999-06-01
申请号：US580816
申请日：1995-12-27
申请人： Gary B. Bronner , Wilfried Hansch , Wendell P. Noble
发明人： Gary B. Bronner , Wilfried Hansch , Wendell P. Noble
IPC分类号： H01L27/04 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L21/331
CPC分类号： H01L29/66181
摘要： A buried plate particularly suitable for formation of a common plate of a plurality of trench capacitors, such as are employed in dynamic random access memories, is formed by implantation of impurities in one or more regions of a wafer or semiconductor layer, epitaxially growing a layer of semiconductor material over the implanted regions and diffusing the implanted impurities into the wafer or semiconductor layer and into the epitaxial layer. Diffusion from such a source avoids process complexity compared with provision of diffusion sources within capacitor trenches and further provides an impurity concentration profile which varies with depth within the resulting body of semiconductor material, resulting in a well-defined boundary of the buried plate and an isolation region both above and below the buried plate. The structure allows biasing of the buried plate as desired, such as for reducing electrical stress on the capacitor dielectric to allow reduction in thickness thereof and reduction of area required for the trench capacitor.
摘要翻译：特别适用于形成诸如用于动态随机存取存储器中的多个沟槽电容器的公共板的掩埋板通过在晶片或半导体层的一个或多个区域中注入杂质来形成，外延生长层的半导体材料，并将注入的杂质扩散到晶片或半导体层中并进入外延层。与在电容器沟槽内提供扩散源相比，这种源的扩散避免了工艺复杂性，并且进一步提供了杂质浓度分布，随着半导体材料体内的深度而变化，导致掩埋板的明确界定和隔离掩埋板上方和下方的区域。该结构可以根据需要偏置掩埋板，例如用于减小电容器电介质上的电应力，以允许减小其厚度并减小沟槽电容器所需的面积。

2. 发明授权

US06180972B2 Buried, implanted plate for DRAM trench storage capacitors 失效
标题翻译：埋地植入板用于DRAM沟槽存储电容器
公开(公告)号：US06180972B2
公开(公告)日：2001-01-30
申请号：US08679799
申请日：1996-07-15
申请人： Gary B. Bronner , Wilfried Hansch , Wendell P. Noble
发明人： Gary B. Bronner , Wilfried Hansch , Wendell P. Noble
IPC分类号： H01L27108
CPC分类号： H01L29/66181
摘要： A buried plate particularly suitable for formation of a common plate of a plurality of trench capacitors, such as are employed in dynamic random access memories, is formed by implantation of impurities in one or more regions of a wafer or semiconductor layer, epitaxially growing a layer of semiconductor material over the implanted regions and diffusing the implanted impurities into the wafer or semiconductor layer and into the epitaxial layer. Diffusion from such a source avoids process complexity compared with provision of diffusion sources within capacitor trenches and further provides an impurity concentration profile which varies with depth within the resulting body of semiconductor material, resulting in a well-defined boundary of the buried plate and an isolation region both above and below the buried plate. The structure allows biasing of the buried plate as desired, such as for reducing electrical stress on the capacitor dielectric to allow reduction in thickness thereof and reduction of area required for the trench capacitor.
摘要翻译：特别适用于形成诸如用于动态随机存取存储器中的多个沟槽电容器的公共板的掩埋板通过在晶片或半导体层的一个或多个区域中注入杂质来形成，外延生长层的半导体材料，并将注入的杂质扩散到晶片或半导体层中并进入外延层。与在电容器沟槽内提供扩散源相比，这种源的扩散避免了工艺复杂性，并且进一步提供了杂质浓度分布，随着半导体材料体内的深度而变化，导致掩埋板的明确界定和隔离掩埋板上方和下方的区域。该结构可以根据需要偏置掩埋板，例如用于减小电容器电介质上的电应力，以允许减小其厚度并减小沟槽电容器所需的面积。

3. 发明授权

US07883962B2 Trench DRAM cell with vertical device and buried word lines 有权
标题翻译：沟槽DRAM单元与垂直设备和埋地字线
公开(公告)号：US07883962B2
公开(公告)日：2011-02-08
申请号：US12848369
申请日：2010-08-02
申请人： Wendell P. Noble
发明人： Wendell P. Noble
IPC分类号： H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10867
摘要： A DRAM array having trench capacitor cells of potentially 4F2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor.
摘要翻译：具有潜在的4F2表面积的沟槽电容器单元的DRAM阵列（F是光刻最小特征宽度）以及制造这种阵列的工艺。阵列具有交叉点单元布局，其中存储单元位于每个位线和每个字线的交点处。阵列中的每个单元具有诸如晶体管的垂直器件，晶体管的源极，漏极和沟道区域由外延生长的单晶硅形成。垂直晶体管形成在沟槽电容器的上方。

4. 发明申请

US20100297819A1 Trench DRAM Cell with Vertical Device and Buried Word Lines 有权
标题翻译：具有垂直设备和埋入字线的沟槽DRAM单元
公开(公告)号：US20100297819A1
公开(公告)日：2010-11-25
申请号：US12848369
申请日：2010-08-02
申请人： Wendell P. Noble
发明人： Wendell P. Noble
IPC分类号： H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10867
摘要： A DRAM array having trench capacitor cells of potentially 4F2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor.
摘要翻译：具有潜在的4F2表面积的沟槽电容器单元的DRAM阵列（F是光刻最小特征宽度）以及制造这种阵列的工艺。阵列具有交叉点单元布局，其中存储单元位于每个位线和每个字线的交点处。阵列中的每个单元具有诸如晶体管的垂直器件，晶体管的源极，漏极和沟道区域由外延生长的单晶硅形成。垂直晶体管形成在沟槽电容器的上方。

5. 发明授权

US07223678B2 Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor 失效
标题翻译：具有垂直晶体管和沟槽电容器的折叠位线存储单元的电路和方法
公开(公告)号：US07223678B2
公开(公告)日：2007-05-29
申请号：US11214557
申请日：2005-08-30
申请人： Wendell P. Noble , Leonard Forbes
发明人： Wendell P. Noble , Leonard Forbes
IPC分类号： H01L21/8238
CPC分类号： H01L27/10864 , H01L27/10838
摘要： A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal semiconductor material. The access transistor has first and second source/drain regions and a body region that are vertically aligned. The access transistor further includes a gate coupled to a wordline disposed adjacent to the body region. The memory cell also includes a passing wordline that is separated from the gate by an insulator for coupling to other memory cells adjacent to the memory cell. The memory cell also includes a trench capacitor. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor. The trench capacitor also includes a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide.
摘要翻译：用于折叠位线配置中的存储器阵列的存储单元。存储单元包括形成在单晶半导体材料的柱中的存取晶体管。存取晶体管具有垂直对齐的第一和第二源极/漏极区域和主体区域。存取晶体管还包括耦合到邻近体区设置的字线的栅极。存储单元还包括通过绝缘体与栅极分离的通过字线，用于耦合到与存储器单元相邻的其它存储单元。存储单元还包括沟槽电容器。沟槽电容器包括与存取晶体管的第一源极/漏极区域一体形成的第一板。沟槽电容器还包括与第一板相邻设置并与栅极氧化物与第一板隔离的第二板。

6. 发明授权

US07176087B2 Methods of forming electrical connections 有权
标题翻译：形成电气连接的方法
公开(公告)号：US07176087B2
公开(公告)日：2007-02-13
申请号：US09896877
申请日：2001-06-29
申请人： Wendell P. Noble
发明人： Wendell P. Noble
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L21/76838 , H01L23/52 , H01L27/10844 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate. Conductive material is formed which is received within at least one of the isolation regions. In one preferred implementation, a silicon-on-insulator (SOI) substrate is utilized to support integrated circuitry which is formed utilizing the methodical aspects of the invention. In another preferred implementation, other substrates, such as conventional bulk substrates are utilized.
摘要翻译：一方面，本发明提供了一种在集成电路装置中形成电连接的方法。根据一个优选的实施方案，扩散区域形成在半导体材料中。形成与扩散区域横向间隔开的导线。导电线优选地形成在分离衬底有源区域的隔离氧化物内部和内部。导电线随后与扩散区域互连。根据另一优选实施方案，在半导体材料内形成氧化物隔离栅。导电材料形成在氧化物隔离栅格内以在其中形成导电栅格。然后去除导电栅格的选定部分以在氧化物隔离栅格内限定互连线。根据另一优选实施方式，在半导体衬底上形成多个氧化物隔离区。形成在至少一个隔离区域内的导电材料。在一个优选实施例中，使用绝缘体上硅（SOI）衬底来支持利用本发明的方法方面形成的集成电路。在另一个优选的实施方式中，利用了诸如常规体积衬底的其它衬底。

7. 发明授权

US07057223B2 Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor 失效
公开(公告)号：US07057223B2
公开(公告)日：2006-06-06
申请号：US10879378
申请日：2004-06-29
申请人： Wendell P. Noble , Leonard Forbes
发明人： Wendell P. Noble , Leonard Forbes
IPC分类号： H01L29/76
CPC分类号： H01L27/10864 , H01L27/10838
摘要： A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal semiconductor material. The access transistor has first and second source/drain regions and a body region that are vertically aligned. The access transistor further includes a gate coupled to a wordline disposed adjacent to the body region. The memory cell also includes a passing wordline that is separated from the gate by an insulator for coupling to other memory cells adjacent to the memory cell. The memory cell also includes a trench capacitor. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor. The trench capacitor also includes a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide.

8. 发明授权

US06809985B2 DRAM technology compatible processor/memory chips 失效
标题翻译： DRAM技术兼容处理器/内存芯片
公开(公告)号：US06809985B2
公开(公告)日：2004-10-26
申请号：US10191332
申请日：2002-07-09
申请人： Leonard Forbes , Eugene H. Cloud , Wendell P. Noble
发明人： Leonard Forbes , Eugene H. Cloud , Wendell P. Noble
IPC分类号： G11C800
CPC分类号： G11C7/1006 , G11C16/0416 , G11C16/08 , H01L27/1052 , H01L27/10852 , H01L27/10894 , H01L29/66825 , H03K19/17716
摘要： The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile memory cells arranged in rows and columns of a second logic plane receive the outputs of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a MOSFET. Each non-volatile memory cell includes a stacked capacitor formed according to a DRAM process. Each nonvolatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The present invention also includes methods for producing the Ics and arrays.
摘要翻译：本发明包括具有接收多个输入信号的第一逻辑平面的可编程逻辑阵列。第一逻辑平面具有互连以提供多个逻辑输出的以行和列排列的多个非易失性存储单元。布置在第二逻辑平面的行和列中的多个非易失性存储单元接收第一逻辑平面的输出并互连以产生多个逻辑输出，使得可编程逻辑阵列实现逻辑功能。每个非易失性存储单元包括MOSFET。每个非易失性存储单元包括根据DRAM工艺形成的堆叠电容器。每个非易失性存储器单元包括将堆叠的电容器耦合到MOSFET的栅极的电接触。本发明还包括用于制造IC和阵列的方法。

9. 发明授权

US06699742B2 Base current reversal SRAM memory cell and method 失效
标题翻译：基极电流反转SRAM存储单元及方法
公开(公告)号：US06699742B2
公开(公告)日：2004-03-02
申请号：US10284984
申请日：2002-10-30
申请人： Wendell P. Noble
发明人： Wendell P. Noble
IPC分类号： H01L218238
CPC分类号： H01L27/11
摘要： A SRAM memory cell including an access device formed on a storage device is described. The storage device has at least two stable states that may be used to store information. In operation, the access device is switched ON to allow a signal representing data to be coupled to the storage device. The storage device switches to a state representative of the signal and maintains this state after the access device is switched OFF. When the access device is switched ON, the state of the storage device may be sensed to read the data stored in the storage device. The memory cell may be formed to be unusually compact and has a reduced power supply requirements compared to conventional SRAM memory cells. As a result, a compact and robust SRAM having reduced standby power requirements is realized.
摘要翻译：描述了包括形成在存储装置上的访问装置的SRAM存储单元。存储设备具有至少两个可用于存储信息的稳定状态。在操作中，接入设备被接通以允许表示数据的信号被耦合到存储设备。存储设备切换到代表信号的状态，并且在接入设备关闭之后保持该状态。当接入设备被接通时，可以感测存储设备的状态以读取存储在存储设备中的数据。与常规SRAM存储单元相比，存储单元可以形成为非常紧凑并且具有降低的电源要求。结果，实现了具有降低的待机功率要求的紧凑且鲁棒的SRAM。

10. 发明授权

US06696746B1 Buried conductors 失效
标题翻译：埋地导体
公开(公告)号：US06696746B1
公开(公告)日：2004-02-24
申请号：US09069326
申请日：1998-04-29
申请人： Paul A. Farrar , Wendell P. Noble
发明人： Paul A. Farrar , Wendell P. Noble
IPC分类号： H01L2940
CPC分类号： H01L21/743 , H01L21/76898 , H01L23/535 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Buried conductors within semiconductor devices and structures, and methods for forming such conductors, are disclosed. In one embodiment of the invention, a semiconductor structure includes a substrate and a plurality of conductive elements buried within the substrate. The conductive elements may be metal, such as tungsten or a tungsten alloy. The invention described in the disclosure provides for advantages including formation of three-dimensional structures without resort to external wiring.
摘要翻译：公开了半导体器件和结构中的埋入导体以及用于形成这种导体的方法。在本发明的一个实施例中，半导体结构包括衬底和埋在衬底内的多个导电元件。导电元件可以是金属，例如钨或钨合金。本公开中描述的本发明提供了包括形成三维结构而不借助于外部布线的优点。

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