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1. 发明授权

US5908310A Method to form a buried implanted plate for DRAM trench storage capacitors 失效
标题翻译：形成用于DRAM沟槽存储电容器的埋入式植入板的方法
公开(公告)号：US5908310A
公开(公告)日：1999-06-01
申请号：US580816
申请日：1995-12-27
申请人： Gary B. Bronner , Wilfried Hansch , Wendell P. Noble
发明人： Gary B. Bronner , Wilfried Hansch , Wendell P. Noble
IPC分类号： H01L27/04 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L21/331
CPC分类号： H01L29/66181
摘要： A buried plate particularly suitable for formation of a common plate of a plurality of trench capacitors, such as are employed in dynamic random access memories, is formed by implantation of impurities in one or more regions of a wafer or semiconductor layer, epitaxially growing a layer of semiconductor material over the implanted regions and diffusing the implanted impurities into the wafer or semiconductor layer and into the epitaxial layer. Diffusion from such a source avoids process complexity compared with provision of diffusion sources within capacitor trenches and further provides an impurity concentration profile which varies with depth within the resulting body of semiconductor material, resulting in a well-defined boundary of the buried plate and an isolation region both above and below the buried plate. The structure allows biasing of the buried plate as desired, such as for reducing electrical stress on the capacitor dielectric to allow reduction in thickness thereof and reduction of area required for the trench capacitor.
摘要翻译：特别适用于形成诸如用于动态随机存取存储器中的多个沟槽电容器的公共板的掩埋板通过在晶片或半导体层的一个或多个区域中注入杂质来形成，外延生长层的半导体材料，并将注入的杂质扩散到晶片或半导体层中并进入外延层。与在电容器沟槽内提供扩散源相比，这种源的扩散避免了工艺复杂性，并且进一步提供了杂质浓度分布，随着半导体材料体内的深度而变化，导致掩埋板的明确界定和隔离掩埋板上方和下方的区域。该结构可以根据需要偏置掩埋板，例如用于减小电容器电介质上的电应力，以允许减小其厚度并减小沟槽电容器所需的面积。

2. 发明授权

US5602410A Off-state gate-oxide field reduction in CMOS 失效
标题翻译： CMOS中的非状态栅氧化物场减少
公开(公告)号：US5602410A
公开(公告)日：1997-02-11
申请号：US519669
申请日：1995-08-25
申请人： Udo Schwalke , Wilfried Hansch
发明人： Udo Schwalke , Wilfried Hansch
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/49 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/823842 , H01L29/4916
摘要： A MOSFET device utilizes the gate depletion effect to reduce the oxide field over the junction area. Since the gate depletion effect is present in the non-conducting off state for n.sup.+ gate PMOS devices and p.sup.+ gate NMOS devices, performance degradation is overcome. The level of doping of the gate is critical. In order to prevent gate depletion in the conducting, on state, the NMOS FET must use a highly doped n.sup.+ gate. The PMOS FET n.sup.+ gate must be non-degeneratively doped in order to utilize the advantage of the gate depletion in the non-conducting, off state. This is accomplished by implanting different doses of the same dopant type into the different gates. The MOSFET device can be implemented equally well for n.sup.+ gate PMOS FET devices as well as for p.sup.+ gate NMOS FET devices.
摘要翻译： MOSFET器件利用栅极耗尽效应来减少接合区域上的氧化物场。由于栅极耗尽效应存在于n +栅极PMOS器件和p +栅极NMOS器件的非导通截止状态，因此克服了性能下降。栅极的掺杂水平至关重要。为了防止导通，导通状态下的栅极耗尽，NMOS FET必须使用高掺杂n +栅极。 PMOS FET n +栅极必须是非退化掺杂的，以便利用非导通关断状态下栅极耗尽的优点。这是通过将不同剂量的相同掺杂剂类型注入不同的栅极来实现的。对于n +栅极PMOS FET器件以及p +栅极NMOS FET器件，可以均匀地实现MOSFET器件。

3. 发明授权

US06180972B2 Buried, implanted plate for DRAM trench storage capacitors 失效
标题翻译：埋地植入板用于DRAM沟槽存储电容器
公开(公告)号：US06180972B2
公开(公告)日：2001-01-30
申请号：US08679799
申请日：1996-07-15
申请人： Gary B. Bronner , Wilfried Hansch , Wendell P. Noble
发明人： Gary B. Bronner , Wilfried Hansch , Wendell P. Noble
IPC分类号： H01L27108
CPC分类号： H01L29/66181
摘要： A buried plate particularly suitable for formation of a common plate of a plurality of trench capacitors, such as are employed in dynamic random access memories, is formed by implantation of impurities in one or more regions of a wafer or semiconductor layer, epitaxially growing a layer of semiconductor material over the implanted regions and diffusing the implanted impurities into the wafer or semiconductor layer and into the epitaxial layer. Diffusion from such a source avoids process complexity compared with provision of diffusion sources within capacitor trenches and further provides an impurity concentration profile which varies with depth within the resulting body of semiconductor material, resulting in a well-defined boundary of the buried plate and an isolation region both above and below the buried plate. The structure allows biasing of the buried plate as desired, such as for reducing electrical stress on the capacitor dielectric to allow reduction in thickness thereof and reduction of area required for the trench capacitor.
摘要翻译：特别适用于形成诸如用于动态随机存取存储器中的多个沟槽电容器的公共板的掩埋板通过在晶片或半导体层的一个或多个区域中注入杂质来形成，外延生长层的半导体材料，并将注入的杂质扩散到晶片或半导体层中并进入外延层。与在电容器沟槽内提供扩散源相比，这种源的扩散避免了工艺复杂性，并且进一步提供了杂质浓度分布，随着半导体材料体内的深度而变化，导致掩埋板的明确界定和隔离掩埋板上方和下方的区域。该结构可以根据需要偏置掩埋板，例如用于减小电容器电介质上的电应力，以允许减小其厚度并减小沟槽电容器所需的面积。

4. 发明授权

US5268317A Method of forming shallow junctions in field effect transistors 失效
标题翻译：在场效应晶体管中形成浅结的方法
公开(公告)号：US5268317A
公开(公告)日：1993-12-07
申请号：US790953
申请日：1991-11-12
申请人： Udo Schwalke , Christoph Zeller , Heinrich J. Zeininger , Wilfried Hansch
发明人： Udo Schwalke , Christoph Zeller , Heinrich J. Zeininger , Wilfried Hansch
IPC分类号： H01L29/78 , H01L21/225 , H01L21/265 , H01L21/336 , H01L21/44
CPC分类号： H01L29/6659 , H01L21/2257 , H01L21/2652 , H01L29/41783
摘要： A method of making a MOS field effect transistor having shallow source and drain regions with improved breakdown and leakage characteristics includes the step of forming a layer of a metal silicide along a surface of a body of silicon at each side of a gate which is on an insulated from the surface. A high concentration of an impurity of a desired conductivity type is implanted only into the metal silicide layers. A lower concentration of the impurity is then implanted through the metal silicide layers and into the body just beneath the metal silicide layers. The body is then annealed at a temperature which drives the impurities from the metal silicide layer into the body to form the junctions.

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