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1. 发明授权

US08433850B2 Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor 有权
标题翻译：用于处理器的微操作缓存中的管道包含和指令重新启动的方法和装置
公开(公告)号：US08433850B2
公开(公告)日：2013-04-30
申请号：US12326885
申请日：2008-12-02
申请人： Lihu Rappoport , Chen Koren , Franck Sala , Ilhyun Kim , Lior Libis , Ron Gabor , Oded Lempel
发明人： Lihu Rappoport , Chen Koren , Franck Sala , Ilhyun Kim , Lior Libis , Ron Gabor , Oded Lempel
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0864 , G06F12/0875 , G06F12/1045 , G06F12/126 , Y02D10/13
摘要： Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.
摘要翻译：公开了用于指令重新启动并包含在处理器微操作高速缓存中的方法和装置。微操作高速缓存的实施例具有方式存储字段来记录存储相应宏指令的指令高速缓存方式。与存储指令的指令 - 高速缓存行相关联的指令缓存使用指示在微操作高速缓存命中时被更新。可以使用微操作高速缓存线中记录的指令高速缓存方式来定位使用中的指示。受害者缓存释放微操作在微操作高速缓存未命中同步之后的微操作队列中排队，响应于从指令缓存到受害缓存的驱逐。包含逻辑还定位并排除对应于所记录的指令 - 高速缓存方式的微操作高速缓存行，以响应于来自指令高速缓存的逐出。

2. 发明授权

US08782374B2 Method and apparatus for inclusion of TLB entries in a micro-op cache of a processor 有权
标题翻译：在处理器的微操作高速缓存中包含TLB条目的方法和装置
公开(公告)号：US08782374B2
公开(公告)日：2014-07-15
申请号：US12326882
申请日：2008-12-02
申请人： Lihu Rappoport , Chen Koren , Franck Sala , Oded Lempel , Ido Ouziel , Ron Gabor , Gregory Pribush , Lior Libis
发明人： Lihu Rappoport , Chen Koren , Franck Sala , Oded Lempel , Ido Ouziel , Ron Gabor , Gregory Pribush , Lior Libis
IPC分类号： G06F12/00 , G06F13/00 , G06F12/10
CPC分类号： G06F12/1027 , G06F12/0864 , G06F12/0875 , G06F12/1036 , G06F12/1045 , G06F12/126 , G06F2212/652 , Y02D10/13
摘要： Methods and apparatus for inclusion of TLB (translation look-aside buffer) in processor micro-op caches are disclosed. Some embodiments for inclusion of TLB entries have micro-op cache inclusion fields, which are set responsive to accessing the TLB entry. Inclusion logic may the flush the micro-op cache or portions of the micro-op cache and clear corresponding inclusion fields responsive to a replacement or invalidation of a TLB entry whenever its associated inclusion field had been set. Front-end processor state may also be cleared and instructions refetched when replacement resulted from a TLB miss.
摘要翻译：公开了在处理器微操作高速缓存中包含TLB（翻译后备缓冲器）的方法和装置。包含TLB条目的一些实施例具有响应于访问TLB条目设置的微操作高速缓存包含字段。包含逻辑可以刷新微操作高速缓存或微操作高速缓存的部分，并且每当其相关联的包含字段被设置时响应于TLB条目的替换或无效而清除相应的包含字段。前端处理器状态也可以被清除，并且在由TLB未命中引起替换时，指令被重新指定。

3. 发明申请

US20100138610A1 METHOD AND APPARATUS FOR INCLUSION OF TLB ENTRIES IN A MICRO-OP CACHE OF A PROCESSOR 有权
标题翻译：在处理器的微型高速缓存中包含TLB入口的方法和装置
公开(公告)号：US20100138610A1
公开(公告)日：2010-06-03
申请号：US12326882
申请日：2008-12-02
申请人： Lihu Rappoport , Chen Koren , Franck Sala , Oded Lempel , Ido Ouziel , Ron Gabor , Gregory Pribush , Lior Libis
发明人： Lihu Rappoport , Chen Koren , Franck Sala , Oded Lempel , Ido Ouziel , Ron Gabor , Gregory Pribush , Lior Libis
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0864 , G06F12/0875 , G06F12/1036 , G06F12/1045 , G06F12/126 , G06F2212/652 , Y02D10/13
摘要： Methods and apparatus for inclusion of TLB (translation look-aside buffer) in processor micro-op caches are disclosed. Some embodiments for inclusion of TLB entries have micro-op cache inclusion fields, which are set responsive to accessing the TLB entry. Inclusion logic may the flush the micro-op cache or portions of the micro-op cache and clear corresponding inclusion fields responsive to a replacement or invalidation of a TLB entry whenever its associated inclusion field had been set. Front-end processor state may also be cleared and instructions refetched when replacement resulted from a TLB miss.
摘要翻译：公开了在处理器微操作高速缓存中包含TLB（翻译后备缓冲器）的方法和装置。包含TLB条目的一些实施例具有响应于访问TLB条目设置的微操作高速缓存包含字段。包含逻辑可以刷新微操作高速缓存或微操作高速缓存的部分，并且每当其相关联的包含字段被设置时响应于TLB条目的替换或无效而清除相应的包含字段。前端处理器状态也可以被清除，并且在由TLB未命中引起替换时，指令被重新指定。

4. 发明申请

US20140185928A1 HARDWARE-SUPPORTED HUFFMAN CODING OF IMAGES 审中-公开
标题翻译：硬件支持的图像编码
公开(公告)号：US20140185928A1
公开(公告)日：2014-07-03
申请号：US13729764
申请日：2012-12-28
申请人： Shai Ben NUN , Lior LIBIS , Itay FRANKO
发明人： Shai Ben NUN , Lior LIBIS , Itay FRANKO
IPC分类号： G06T9/00
CPC分类号： G06T9/005 , H04N19/186 , H04N19/42 , H04N19/91
摘要： Embodiments of the present invention may provide a apparatus and method for compressing image data by dividing the data into color components data streams, taking the differences between successive pixels in the data streams, and coding these differences into a compressed data stream using a Huffman coding scheme. The compressed data may be transmitted to a decompressor over an interface. The decompressor may divide the compressed data stream back into color component data streams and decompress the pixels by adding the coded differences to reference values corresponding to previously decompressed pixels of the same color component to generate successive pixels of that color component. Merge registers may then recombined the decompressed data into the original image data. According to embodiments of the present invention, the compression/decompression process may be lossless.
摘要翻译：本发明的实施例可以提供一种用于通过将数据划分为颜色分量数据流来压缩图像数据的装置和方法，取得数据流中连续像素之间的差异，并使用霍夫曼编码方案将这些差分编码为压缩数据流。压缩数据可以通过接口传送到解压缩器。解压缩器可以将压缩数据流分割回彩色分量数据流，并通过将编码差加到与先前相同颜色分量的解压缩像素相对应的参考值来解压缩像素，以产生该颜色分量的连续像素。合并寄存器然后可以将解压缩的数据重组为原始图像数据。根据本发明的实施例，压缩/解压缩过程可以是无损的。

5. 发明申请

US20100138608A1 Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor 有权
标题翻译：用于处理器的微操作缓存中的管道包含和指令重新启动的方法和装置
公开(公告)号：US20100138608A1
公开(公告)日：2010-06-03
申请号：US12317959
申请日：2008-12-31
申请人： Lihu Rappoport , Chen Koren , Franck Sala , Oded Lempel , Ido Ouziel , Ilhyun Kim , Ron Gabor , Lior Libis , Gregory Pribush
发明人： Lihu Rappoport , Chen Koren , Franck Sala , Oded Lempel , Ido Ouziel , Ilhyun Kim , Ron Gabor , Lior Libis , Gregory Pribush
IPC分类号： G06F12/00
CPC分类号： G06F12/0806 , G06F12/0864 , G06F12/0875 , G06F12/1045 , G06F12/126 , Y02D10/13
摘要： Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.
摘要翻译：公开了用于指令重新启动并包含在处理器微操作高速缓存中的方法和装置。微操作高速缓存的实施例具有方式存储字段来记录存储相应宏指令的指令高速缓存方式。与存储指令的指令 - 高速缓存行相关联的指令缓存使用指示在微操作高速缓存命中时被更新。可以使用微操作高速缓存线中记录的指令高速缓存方式来定位使用中的指示。受害者缓存释放微操作在微操作高速缓存未命中同步之后的微操作队列中排队，响应于从指令缓存到受害缓存的驱逐。包含逻辑还定位并排除对应于所记录的指令 - 高速缓存方式的微操作高速缓存行，以响应于来自指令高速缓存的逐出。

6. 发明授权

US08127085B2 Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor 有权
标题翻译：用于处理器的微操作缓存中的管道包含和指令重新启动的方法和装置
公开(公告)号：US08127085B2
公开(公告)日：2012-02-28
申请号：US12317959
申请日：2008-12-31
申请人： Lihu Rappoport , Chen Koren , Franck Sala , Oded Lempel , Ido Ouziel , Ilhyun Kim , Ron Gabor , Lior Libis , Gregory Pribush
发明人： Lihu Rappoport , Chen Koren , Franck Sala , Oded Lempel , Ido Ouziel , Ilhyun Kim , Ron Gabor , Lior Libis , Gregory Pribush
IPC分类号： G06F12/06
CPC分类号： G06F12/0806 , G06F12/0864 , G06F12/0875 , G06F12/1045 , G06F12/126 , Y02D10/13
摘要： Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.
摘要翻译：公开了用于指令重新启动并包含在处理器微操作高速缓存中的方法和装置。微操作高速缓存的实施例具有方式存储字段来记录存储相应宏指令的指令高速缓存方式。与存储指令的指令 - 高速缓存行相关联的指令缓存使用指示在微操作高速缓存命中时被更新。可以使用微操作高速缓存线中记录的指令高速缓存方式来定位使用中的指示。受害者缓存释放微操作在微操作高速缓存未命中同步之后的微操作队列中排队，响应于从指令缓存到受害缓存的驱逐。包含逻辑还定位并排除与记录的指令 - 高速缓存方式对应的微操作高速缓存行，以响应于来自指令高速缓存的逐出。

7. 发明申请

US20100138611A1 METHOD AND APPARATUS FOR PIPELINE INCLUSION AND INSTRUCTION RESTARTS IN A MICRO-OP CACHE OF A PROCESSOR 有权
标题翻译：方法和装置在处理器的微型高速缓存中的管道包含和指导性恢复
公开(公告)号：US20100138611A1
公开(公告)日：2010-06-03
申请号：US12326885
申请日：2008-12-02
申请人： LIHU RAPPOPORT , Chen Koren , Franck Sala , Ilhyun Kim , Lior Libis , Ron Gabor , Oded Lempel
发明人： LIHU RAPPOPORT , Chen Koren , Franck Sala , Ilhyun Kim , Lior Libis , Ron Gabor , Oded Lempel
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F12/0875 , G06F12/1045 , G06F12/126 , Y02D10/13
摘要： Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.
摘要翻译：公开了用于指令重新启动并包含在处理器微操作高速缓存中的方法和装置。微操作高速缓存的实施例具有方式存储字段来记录存储相应宏指令的指令高速缓存方式。与存储指令的指令 - 高速缓存行相关联的指令缓存使用指示在微操作高速缓存命中时被更新。可以使用微操作高速缓存线中记录的指令高速缓存方式来定位使用中的指示。受害者缓存释放微操作在微操作高速缓存未命中同步之后的微操作队列中排队，响应于从指令缓存到受害缓存的驱逐。包含逻辑还定位并排除对应于所记录的指令 - 高速缓存方式的微操作高速缓存行，以响应于来自指令高速缓存的逐出。

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