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1. 发明申请

US20120124332A1 VECTOR PROCESSING CIRCUIT, COMMAND ISSUANCE CONTROL METHOD, AND PROCESSOR SYSTEM 有权
标题翻译：矢量处理电路，指令发布控制方法和处理器系统
公开(公告)号：US20120124332A1
公开(公告)日：2012-05-17
申请号：US13279482
申请日：2011-10-24
申请人： GE Yi , Yoshimasa Takebe , Hiromasa Takahashi
发明人： GE Yi , Yoshimasa Takebe , Hiromasa Takahashi
IPC分类号： G06F9/302 , G06F9/44
CPC分类号： G06F9/30014 , G06F9/30109 , G06F9/30149 , G06F9/3836
摘要： A vector processing circuit includes a vector register file including a plurality of array elements, a command issuance control circuit, and a plurality of pipeline arithmetic units. Each pipeline arithmetic unit performs arithmetic processing of data stored in the array elements indicated as a source by one command in parts through a plurality of cycles and stores the result in the array elements indicated as a destination by the one command through a plurality of cycles. When data word length of a preceding command is longer than that of a subsequent command, the command issuance control circuit changes data sizes of the array elements in accordance with data word length of the command and determines whether there is register interference between the array element to be processed at a non-head cycle of the preceding command, and the array element to be processed at a head cycle of the subsequent command.
摘要翻译：矢量处理电路包括包括多个阵列元素的矢量寄存器文件，命令发布控制电路和多个流水线运算单元。每个流水线运算单元通过多个周期以部分方式，通过一个命令对存储在源表示的数组元素中的数据进行算术处理，并将该结果存储在通过多个周期的一个命令作为目的地表示的数组元素中。当前一个命令的数据字长度大于后续命令的数据字长时，命令发布控制电路根据命令的数据字长度改变数组元素的数据大小，并确定数组元素与在前一个命令的非头循环处理，以及要在后续命令的头循环处理的数组元素。

2. 发明授权

US08874879B2 Vector processing circuit, command issuance control method, and processor system 有权
标题翻译：矢量处理电路，命令发布控制方法和处理器系统
公开(公告)号：US08874879B2
公开(公告)日：2014-10-28
申请号：US13279482
申请日：2011-10-24
申请人： Yi Ge , Yoshimasa Takebe , Hiromasa Takahashi
发明人： Yi Ge , Yoshimasa Takebe , Hiromasa Takahashi
IPC分类号： G06F9/00 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30014 , G06F9/30109 , G06F9/30149 , G06F9/3836
摘要： A vector processing circuit includes a vector register file including a plurality of array elements, a command issuance control circuit, and a plurality of pipeline arithmetic units. Each pipeline arithmetic unit performs arithmetic processing of data stored in the array elements indicated as a source by one command in parts through a plurality of cycles and stores the result in the array elements indicated as a destination by the one command through a plurality of cycles. When data word length of a preceding command is longer than that of a subsequent command, the command issuance control circuit changes data sizes of the array elements in accordance with data word length of the command and determines whether there is register interference between the array element to be processed at a non-head cycle of the preceding command, and the array element to be processed at a head cycle of the subsequent command.
摘要翻译：矢量处理电路包括包括多个阵列元素的矢量寄存器文件，命令发布控制电路和多个流水线运算单元。每个流水线运算单元通过多个周期以部分方式，通过一个命令对存储在源表示的数组元素中的数据进行算术处理，并将该结果存储在通过多个周期的一个命令作为目的地表示的数组元素中。当前一个命令的数据字长度大于后续命令的数据字长时，命令发布控制电路根据命令的数据字长度改变数组元素的数据大小，并确定数组元素与在前一个命令的非头循环处理，以及要在后续命令的头循环处理的数组元素。

3. 发明申请

US20070028071A1 Memory device 有权
标题翻译：内存设备
公开(公告)号：US20070028071A1
公开(公告)日：2007-02-01
申请号：US11271913
申请日：2005-11-14
申请人： Akira Nodomi , Yoshimasa Takebe
发明人： Akira Nodomi , Yoshimasa Takebe
IPC分类号： G06F12/00
CPC分类号： G06F12/0802
摘要： A memory device that can handle various transmission-source devices and transmission-destination devices without modifying the hardware configuration. The memory device is used to transmit and receive data, and includes a data buffer for storing data output from a data-transmission source and outputting the data to a data-transmission destination serving as the data output destination; a transmission-source address converter for performing arrangement processing on the data output from the data-transmission source when the data-transmission source is a device that passively outputs data; and a transmission-destination address converter for performing arrangement processing on the data to be input to the data-transmission destination when the data-transmission destination is a device to which data is passively input.
摘要翻译：一种可以处理各种传输源设备和传输目的地设备而不修改硬件配置的存储设备。存储装置用于发送和接收数据，并且包括数据缓冲器，用于存储从数据传输源输出的数据，并将数据输出到作为数据输出目的地的数据传输目的地; 发送源地址转换器，用于当数据发送源是被动地输出数据的设备时，对从数据发送源输出的数据进行配置处理; 以及发送目的地地址转换器，用于当数据发送目的地是被动地输入数据的设备时，对要输入到数据发送目的地的数据进行配置处理。

4. 发明授权

US07134004B1 Processing device for buffering sequential and target sequences and target address information for multiple branch instructions 失效
标题翻译：用于缓冲顺序和目标序列的处理设备以及多个分支指令的目标地址信息
公开(公告)号：US07134004B1
公开(公告)日：2006-11-07
申请号：US09666853
申请日：2000-09-20
申请人： Shin-ichiro Tago , Taizo Sato , Yoshimasa Takebe , Yasuhiro Yamazaki , Teruhiko Kamigata , Atsuhiro Suga , Hiroshi Okano , Hitoshi Yoda
发明人： Shin-ichiro Tago , Taizo Sato , Yoshimasa Takebe , Yasuhiro Yamazaki , Teruhiko Kamigata , Atsuhiro Suga , Hiroshi Okano , Hitoshi Yoda
IPC分类号： G06F9/00
CPC分类号： G06F9/3804 , G06F9/3806 , G06F9/3846
摘要： An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which assigns a read address to the instruction store portion, an instruction buffering portion which includes a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion. A branching instruction detection portion detects a branching instruction in the instruction sequence read from the instruction store portion. A branch target address information buffering portion includes a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction.
摘要翻译：信息处理装置通过流水线处理从指令存储部分读取，缓冲，解码和执行指令，包括：向指令存储部分分配读取地址的指令读取请求部分，包括多个指令缓冲器的指令缓冲部分，缓冲从指令存储部分读取的指令序列; 指令执行单元，其对由指令缓冲部分缓冲的指令进行解码和执行。分支指令检测部分检测从指令存储部分读取的指令序列中的分支指令。分支目标地址信息缓冲部分包括多个分支目标地址信息缓冲器，当分支指令检测部分已经检测到分支指令时，缓冲用于生成分支指令的分支目标地址的转移目标地址信息。

5. 发明授权

US08806184B2 Branch prediction method and branch prediction circuit performing the method 有权
标题翻译：执行该方法的分支预测方法和分支预测电路
公开(公告)号：US08806184B2
公开(公告)日：2014-08-12
申请号：US13052197
申请日：2011-03-21
申请人： Yoshimasa Takebe
发明人： Yoshimasa Takebe
IPC分类号： G06F9/30
CPC分类号： G06F9/3844 , G06F9/3806
摘要： A branch prediction circuit includes: a memory for storing information representing a branch instruction and a branch prediction; a control circuit for controlling rewriting information in the memory in accordance with a result of determining whether or not a predicted branch has been taken, and determining an attribute of the predicted branch from a branch condition set by the branch instruction and the predicted branch that has been taken, if the predicted branch has been taken; and a rewriting circuit rewriting the information in the memory under the control of the control circuit.
摘要翻译：分支预测电路包括：存储器，用于存储表示分支指令和分支预测的信息; 控制电路，用于根据确定是否已经采用了预测分支的结果来控制存储器中的重写信息，以及由分支指令和预测分支设置的分支条件确定预测分支的属性如果预测的分支被采取，则被采取; 并且重写电路在控制电路的控制下重写存储器中的信息。

6. 发明授权

US07434023B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US07434023B2
公开(公告)日：2008-10-07
申请号：US11271913
申请日：2005-11-14
申请人： Akira Nodomi , Yoshimasa Takebe
发明人： Akira Nodomi , Yoshimasa Takebe
IPC分类号： G06F9/22 , G06F9/30
CPC分类号： G06F12/0802
摘要： A memory device that can handle various transmission-source devices and transmission-destination devices without modifying the hardware configuration. The memory device is used to transmit and receive data, and includes a data buffer for storing data output from a data-transmission source and outputting the data to a data-transmission destination serving as the data output destination; a transmission-source address converter for performing arrangement processing on the data output from the data-transmission source when the data-transmission source is a device that passively outputs data; and a transmission-destination address converter for performing arrangement processing on the data to be input to the data-transmission destination when the data-transmission destination is a device to which data is passively input.
摘要翻译：一种可以处理各种传输源设备和传输目的地设备而不修改硬件配置的存储设备。存储装置用于发送和接收数据，并且包括数据缓冲器，用于存储从数据传输源输出的数据，并将数据输出到作为数据输出目的地的数据传输目的地; 发送源地址转换器，用于当数据发送源是被动地输出数据的设备时，对从数据发送源输出的数据进行配置处理; 以及发送目的地地址转换器，用于当数据发送目的地是被动地输入数据的设备时，对要输入到数据发送目的地的数据进行配置处理。

7. 发明授权

US08484446B2 Microprocessor saving data stored in register and register saving method 有权
标题翻译：微处理器保存数据存储在寄存器和寄存器保存方法中
公开(公告)号：US08484446B2
公开(公告)日：2013-07-09
申请号：US12076857
申请日：2008-03-24
申请人： Yoshimasa Takebe
发明人： Yoshimasa Takebe
IPC分类号： G06F12/02
CPC分类号： G06F9/30123 , G06F9/30043 , G06F9/30134 , G06F9/30138 , G06F9/35 , G06F9/4484
摘要： A microprocessor which realizes fast register saving and restoring which are involved in subroutine calls, and is capable of reducing the scale of a program. A register file is provided with at least one register for storing data to be used for computational processing. A saving memory stores therein data saved from the registers. A saving control unit saves data from a writing destination register to the saving memory when an instruction to write to the register is executed in a subroutine. Then the saving control unit restores data saved in the saving memory back to the original registers when an instruction to return from the subroutine is executed.
摘要翻译：实现快速寄存器保存和恢复的微处理器涉及子程序调用，并且能够减少程序的规模。寄存器文件具有至少一个用于存储要用于计算处理的数据的寄存器。保存存储器存储从寄存器保存的数据。当在子程序中执行写入寄存器的指令时，保存控制单元将数据从写入目的地寄存器保存到保存存储器。然后，当执行从子程序返回的指令时，保存控制单元将保存在保存存储器中的数据恢复回原始寄存器。

8. 发明申请

US20110238966A1 BRANCH PREDICTION METHOD AND BRANCH PREDICTION CIRCUIT FOR EXECUTING THE SAME 审中-公开
标题翻译：分支预测方法和分支预测电路执行相同
公开(公告)号：US20110238966A1
公开(公告)日：2011-09-29
申请号：US13070983
申请日：2011-03-24
申请人： Yoshimasa Takebe
发明人： Yoshimasa Takebe
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/3806
摘要： A branch prediction method executed in a branch prediction circuit executes the branch instruction, the branch prediction method includes: a branch information storing process for storing the information in the first storage unit or the second storage unit; a process for determining on the basis of a branch condition set by the branch instruction and a realized branch whether the branch prediction is realized; a rewriting process for performing a rewrite of the information in one of the first storage unit and the second storage unit in accordance with the determination and the degree of likelihood that a branch indicated by the branch prediction occurs; and a process for performing branch prediction in response to the branch information when the branch instruction is executed in the processor.
摘要翻译：在分支预测电路中执行的分支预测方法执行分支指令，分支预测方法包括：分支信息存储处理，用于将信息存储在第一存储单元或第二存储单元中; 基于由分支指令设定的分支条件和实现的分支来确定分支预测是否实现的处理; 根据由分支预测指示的分支的确定和可能性程度，进行第一存储单元和第二存储单元之一中的信息的重写的重写处理; 以及当在处理器中执行分支指令时，响应于分支信息执行分支预测的处理。

9. 发明申请

US20060143416A1 Multiprocessor system with high-speed exclusive control 有权
标题翻译：具有高速独占控制的多处理器系统
公开(公告)号：US20060143416A1
公开(公告)日：2006-06-29
申请号：US11113056
申请日：2005-04-25
申请人： Teruhiko Kamigata , Shinichiro Tago , Atsushi Ike , Yoshimasa Takebe
发明人： Teruhiko Kamigata , Shinichiro Tago , Atsushi Ike , Yoshimasa Takebe
IPC分类号： G06F12/14
CPC分类号： G06F9/526
摘要： A multiprocessor system includes a plurality of processors, a shared bus coupled to the plurality of processors, a resource coupled to the shared bus and shared by the plurality of processors, and an exclusive control unit coupled to the plurality of processors and configured to include a lock flag indicative of a locked/unlocked state regarding exclusive use of the resource, wherein the processors include a special purpose register interface coupled to the exclusive control unit, and are configured to access the lock flag by special purpose register access through the special purpose register interface.
摘要翻译：多处理器系统包括多个处理器，耦合到多个处理器的共享总线，耦合到共享总线并被多个处理器共享的资源，以及耦合到多个处理器的排他控制单元，并且被配置为包括指示关于资源的独占使用的锁定/解锁状态的锁定标志，其中处理器包括耦合到排他控制单元的专用寄存器接口，并且被配置为通过专用寄存器访问专用寄存器访问锁定标志接口。

10. 发明申请

US20090172296A1 Cache Memory System and Cache Memory Control Method 审中-公开
标题翻译：缓存内存系统和缓存内存控制方法
公开(公告)号：US20090172296A1
公开(公告)日：2009-07-02
申请号：US12343251
申请日：2008-12-23
申请人： Masayuki TSUJI , Yoshimasa Takebe , Akira Nodomi
发明人： Masayuki TSUJI , Yoshimasa Takebe , Akira Nodomi
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F2212/1044
摘要： A cache memory system including a processing unit and a cache memory which is connected to the processing unit, wherein when a store instruction of storing write data into a certain address is executed, the cache memory system executes selectively one of, a first operation mode of allocating an area of the address to the cache memory in response to a generation of a cache miss due to an access to the address, copying data of the address of the main memory unit to the cache memory and then rewriting the copied data on the cache memory using the write data, and a second operation mode in response to a generation of a cache miss due to the access to the address and storing the write data to the cache memory without copying data of the address of the main memory unit to the allocated area on the cache memory.
摘要翻译：一种高速缓冲存储器系统，包括连接到处理单元的处理单元和高速缓存存储器，其中当执行将写入数据存储到特定地址的存储指令时，高速缓冲存储器系统选择性地执行以下操作中的一种：第一操作模式响应于由于访问地址而产生高速缓存未命中而将地址的区域分配给高速缓冲存储器，将主存储器单元的地址的数据复制到高速缓冲存储器，然后在缓存上重写复制的数据存储器，以及响应于由于访问地址而产生高速缓存未命中的第二操作模式，并且将写入数据存储到高速缓冲存储器，而不将主存储器单元的地址的数据复制到所分配的缓存中的区域。

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