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1. 发明授权

US08874879B2 Vector processing circuit, command issuance control method, and processor system 有权
标题翻译：矢量处理电路，命令发布控制方法和处理器系统
公开(公告)号：US08874879B2
公开(公告)日：2014-10-28
申请号：US13279482
申请日：2011-10-24
申请人： Yi Ge , Yoshimasa Takebe , Hiromasa Takahashi
发明人： Yi Ge , Yoshimasa Takebe , Hiromasa Takahashi
IPC分类号： G06F9/00 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30014 , G06F9/30109 , G06F9/30149 , G06F9/3836
摘要： A vector processing circuit includes a vector register file including a plurality of array elements, a command issuance control circuit, and a plurality of pipeline arithmetic units. Each pipeline arithmetic unit performs arithmetic processing of data stored in the array elements indicated as a source by one command in parts through a plurality of cycles and stores the result in the array elements indicated as a destination by the one command through a plurality of cycles. When data word length of a preceding command is longer than that of a subsequent command, the command issuance control circuit changes data sizes of the array elements in accordance with data word length of the command and determines whether there is register interference between the array element to be processed at a non-head cycle of the preceding command, and the array element to be processed at a head cycle of the subsequent command.
摘要翻译：矢量处理电路包括包括多个阵列元素的矢量寄存器文件，命令发布控制电路和多个流水线运算单元。每个流水线运算单元通过多个周期以部分方式，通过一个命令对存储在源表示的数组元素中的数据进行算术处理，并将该结果存储在通过多个周期的一个命令作为目的地表示的数组元素中。当前一个命令的数据字长度大于后续命令的数据字长时，命令发布控制电路根据命令的数据字长度改变数组元素的数据大小，并确定数组元素与在前一个命令的非头循环处理，以及要在后续命令的头循环处理的数组元素。

2. 发明授权

US08806184B2 Branch prediction method and branch prediction circuit performing the method 有权
标题翻译：执行该方法的分支预测方法和分支预测电路
公开(公告)号：US08806184B2
公开(公告)日：2014-08-12
申请号：US13052197
申请日：2011-03-21
申请人： Yoshimasa Takebe
发明人： Yoshimasa Takebe
IPC分类号： G06F9/30
CPC分类号： G06F9/3844 , G06F9/3806
摘要： A branch prediction circuit includes: a memory for storing information representing a branch instruction and a branch prediction; a control circuit for controlling rewriting information in the memory in accordance with a result of determining whether or not a predicted branch has been taken, and determining an attribute of the predicted branch from a branch condition set by the branch instruction and the predicted branch that has been taken, if the predicted branch has been taken; and a rewriting circuit rewriting the information in the memory under the control of the control circuit.
摘要翻译：分支预测电路包括：存储器，用于存储表示分支指令和分支预测的信息; 控制电路，用于根据确定是否已经采用了预测分支的结果来控制存储器中的重写信息，以及由分支指令和预测分支设置的分支条件确定预测分支的属性如果预测的分支被采取，则被采取; 并且重写电路在控制电路的控制下重写存储器中的信息。

3. 发明授权

US07434023B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US07434023B2
公开(公告)日：2008-10-07
申请号：US11271913
申请日：2005-11-14
申请人： Akira Nodomi , Yoshimasa Takebe
发明人： Akira Nodomi , Yoshimasa Takebe
IPC分类号： G06F9/22 , G06F9/30
CPC分类号： G06F12/0802
摘要： A memory device that can handle various transmission-source devices and transmission-destination devices without modifying the hardware configuration. The memory device is used to transmit and receive data, and includes a data buffer for storing data output from a data-transmission source and outputting the data to a data-transmission destination serving as the data output destination; a transmission-source address converter for performing arrangement processing on the data output from the data-transmission source when the data-transmission source is a device that passively outputs data; and a transmission-destination address converter for performing arrangement processing on the data to be input to the data-transmission destination when the data-transmission destination is a device to which data is passively input.
摘要翻译：一种可以处理各种传输源设备和传输目的地设备而不修改硬件配置的存储设备。存储装置用于发送和接收数据，并且包括数据缓冲器，用于存储从数据传输源输出的数据，并将数据输出到作为数据输出目的地的数据传输目的地; 发送源地址转换器，用于当数据发送源是被动地输出数据的设备时，对从数据发送源输出的数据进行配置处理; 以及发送目的地地址转换器，用于当数据发送目的地是被动地输入数据的设备时，对要输入到数据发送目的地的数据进行配置处理。

4. 发明申请

US20070028071A1 Memory device 有权
标题翻译：内存设备
公开(公告)号：US20070028071A1
公开(公告)日：2007-02-01
申请号：US11271913
申请日：2005-11-14
申请人： Akira Nodomi , Yoshimasa Takebe
发明人： Akira Nodomi , Yoshimasa Takebe
IPC分类号： G06F12/00
CPC分类号： G06F12/0802
摘要： A memory device that can handle various transmission-source devices and transmission-destination devices without modifying the hardware configuration. The memory device is used to transmit and receive data, and includes a data buffer for storing data output from a data-transmission source and outputting the data to a data-transmission destination serving as the data output destination; a transmission-source address converter for performing arrangement processing on the data output from the data-transmission source when the data-transmission source is a device that passively outputs data; and a transmission-destination address converter for performing arrangement processing on the data to be input to the data-transmission destination when the data-transmission destination is a device to which data is passively input.
摘要翻译：一种可以处理各种传输源设备和传输目的地设备而不修改硬件配置的存储设备。存储装置用于发送和接收数据，并且包括数据缓冲器，用于存储从数据传输源输出的数据，并将数据输出到作为数据输出目的地的数据传输目的地; 发送源地址转换器，用于当数据发送源是被动地输出数据的设备时，对从数据发送源输出的数据进行配置处理; 以及发送目的地地址转换器，用于当数据发送目的地是被动地输入数据的设备时，对要输入到数据发送目的地的数据进行配置处理。

5. 发明授权

US07134004B1 Processing device for buffering sequential and target sequences and target address information for multiple branch instructions 失效
标题翻译：用于缓冲顺序和目标序列的处理设备以及多个分支指令的目标地址信息
公开(公告)号：US07134004B1
公开(公告)日：2006-11-07
申请号：US09666853
申请日：2000-09-20
申请人： Shin-ichiro Tago , Taizo Sato , Yoshimasa Takebe , Yasuhiro Yamazaki , Teruhiko Kamigata , Atsuhiro Suga , Hiroshi Okano , Hitoshi Yoda
发明人： Shin-ichiro Tago , Taizo Sato , Yoshimasa Takebe , Yasuhiro Yamazaki , Teruhiko Kamigata , Atsuhiro Suga , Hiroshi Okano , Hitoshi Yoda
IPC分类号： G06F9/00
CPC分类号： G06F9/3804 , G06F9/3806 , G06F9/3846
摘要： An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which assigns a read address to the instruction store portion, an instruction buffering portion which includes a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion. A branching instruction detection portion detects a branching instruction in the instruction sequence read from the instruction store portion. A branch target address information buffering portion includes a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction.
摘要翻译：信息处理装置通过流水线处理从指令存储部分读取，缓冲，解码和执行指令，包括：向指令存储部分分配读取地址的指令读取请求部分，包括多个指令缓冲器的指令缓冲部分，缓冲从指令存储部分读取的指令序列; 指令执行单元，其对由指令缓冲部分缓冲的指令进行解码和执行。分支指令检测部分检测从指令存储部分读取的指令序列中的分支指令。分支目标地址信息缓冲部分包括多个分支目标地址信息缓冲器，当分支指令检测部分已经检测到分支指令时，缓冲用于生成分支指令的分支目标地址的转移目标地址信息。

6. 发明申请

US20090172296A1 Cache Memory System and Cache Memory Control Method 审中-公开
标题翻译：缓存内存系统和缓存内存控制方法
公开(公告)号：US20090172296A1
公开(公告)日：2009-07-02
申请号：US12343251
申请日：2008-12-23
申请人： Masayuki TSUJI , Yoshimasa Takebe , Akira Nodomi
发明人： Masayuki TSUJI , Yoshimasa Takebe , Akira Nodomi
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F2212/1044
摘要： A cache memory system including a processing unit and a cache memory which is connected to the processing unit, wherein when a store instruction of storing write data into a certain address is executed, the cache memory system executes selectively one of, a first operation mode of allocating an area of the address to the cache memory in response to a generation of a cache miss due to an access to the address, copying data of the address of the main memory unit to the cache memory and then rewriting the copied data on the cache memory using the write data, and a second operation mode in response to a generation of a cache miss due to the access to the address and storing the write data to the cache memory without copying data of the address of the main memory unit to the allocated area on the cache memory.
摘要翻译：一种高速缓冲存储器系统，包括连接到处理单元的处理单元和高速缓存存储器，其中当执行将写入数据存储到特定地址的存储指令时，高速缓冲存储器系统选择性地执行以下操作中的一种：第一操作模式响应于由于访问地址而产生高速缓存未命中而将地址的区域分配给高速缓冲存储器，将主存储器单元的地址的数据复制到高速缓冲存储器，然后在缓存上重写复制的数据存储器，以及响应于由于访问地址而产生高速缓存未命中的第二操作模式，并且将写入数据存储到高速缓冲存储器，而不将主存储器单元的地址的数据复制到所分配的缓存中的区域。

7. 发明授权

US07543135B2 Processor and method for selectively processing instruction to be read using instruction code already in pipeline or already stored in prefetch buffer 失效
标题翻译：处理器和方法，用于使用已经在流水线中或已经存储在预取缓冲器中的指令代码来选择性地处理要被读取的指令
公开(公告)号：US07543135B2
公开(公告)日：2009-06-02
申请号：US11497290
申请日：2006-08-02
申请人： Yoshimasa Takebe
发明人： Yoshimasa Takebe
IPC分类号： G06F7/00
CPC分类号： G06F9/3802 , G06F9/3863 , G06F12/0855 , G06F12/0862 , G06F12/0875 , G06F2212/6022 , Y02D10/13
摘要： There is provided a processor including: an instruction pipeline pipeline-processing an instruction code; a comparison unit that compares an instruction code in the instruction pipeline or in an instruction prefetch buffer and an instruction code to be read next from an instruction cache memory or from a main memory, to judge whether or not the instruction codes are identical with each other; and a control unit whose control when the instruction codes are identical with each other is to read the instruction code neither from the instruction cache memory nor from the main memory but to process the instruction code stored in the instruction pipeline or in the instruction prefetch buffer again in the instruction pipeline or in the instruction prefetch buffer.
摘要翻译：提供了一种处理器，包括：指令流水线处理指令代码; 比较单元，其将指令流水线中的指令代码或指令预取缓冲器和接下来从指令高速缓冲存储器或主存储器读取的指令代码进行比较，以判断指令代码是否相同 ; 以及当指令代码相同时控制的控制单元既不从指令高速缓存存储器也不从主存储器读取指令代码，而是再次处理存储在指令流水线或指令预取缓冲器中的指令代码在指令流水线或指令预取缓冲区中。

8. 发明申请

US20080215859A1 Computer with high-speed context switching 审中-公开
标题翻译：具有高速上下文切换的计算机
公开(公告)号：US20080215859A1
公开(公告)日：2008-09-04
申请号：US12073042
申请日：2008-02-28
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Masayuki Tsuji , Yasuhiro Yamazaki , Yoshimasa Takebe , Taizo Sato , Shinichiro Tago
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Masayuki Tsuji , Yasuhiro Yamazaki , Yoshimasa Takebe , Taizo Sato , Shinichiro Tago
IPC分类号： G06F9/312 , G06F9/302
CPC分类号： G06F7/535 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3861 , G06F9/3867 , G06F9/3877 , G06F9/461 , G06F9/5016 , G06F2207/5353 , Y02D10/22
摘要： A computer which performs parallel processing of a plurality of programs in a time-division fashion includes hardware resources divided into a plurality of areas, an evacuation unit which records identification information identifying a first program, and evacuates information stored in an area of said plurality of areas if the area is necessary for execution of a second program and is being used for execution of the first program, and a restoration unit which restores the evacuated information to the area based on the identification information when the second program comes to a halt or to an end.
摘要翻译：以时分方式执行多个程序的并行处理的计算机包括划分为多个区域的硬件资源，记录识别第一程序的识别信息的撤离单元，以及排除存储在所述多个区域的区域中的信息如果该区域是执行第二程序所必需的并被用于执行第一程序的区域，以及恢复单元，其在第二程序停止时基于识别信息将该撤离信息恢复到该区域，或者结束。

9. 发明授权

US07409506B2 Multiprocessor system with high-speed exclusive control 有权
标题翻译：具有高速独占控制的多处理器系统
公开(公告)号：US07409506B2
公开(公告)日：2008-08-05
申请号：US11113056
申请日：2005-04-25
申请人： Teruhiko Kamigata , Shinichiro Tago , Atsushi Ike , Yoshimasa Takebe
发明人： Teruhiko Kamigata , Shinichiro Tago , Atsushi Ike , Yoshimasa Takebe
IPC分类号： G06F13/18 , G06F13/16
CPC分类号： G06F9/526
摘要： A multiprocessor system includes a plurality of processors, a shared bus coupled to the plurality of processors, a resource coupled to the shared bus and shared by the plurality of processors, and an exclusive control unit coupled to the plurality of processors and configured to include a lock flag indicative of a locked/unlocked state regarding exclusive use of the resource, wherein the processors include a special purpose register interface coupled to the exclusive control unit, and are configured to access the lock flag by special purpose register access through the special purpose register interface.
摘要翻译：多处理器系统包括多个处理器，耦合到多个处理器的共享总线，耦合到共享总线并被多个处理器共享的资源，以及耦合到多个处理器的排他控制单元，并且被配置为包括指示关于资源的独占使用的锁定/解锁状态的锁定标志，其中处理器包括耦合到排他控制单元的专用寄存器接口，并且被配置为通过专用寄存器访问专用寄存器访问锁定标志接口。

10. 发明授权

US07055023B2 Apparatus and method for branch prediction where data for predictions is selected from a count in a branch history table or a bias in a branch target buffer 有权
标题翻译：用于分支预测的装置和方法，其中从分支历史表中的计数或分支目标缓冲器中的偏差中选择用于预测的数据
公开(公告)号：US07055023B2
公开(公告)日：2006-05-30
申请号：US10091147
申请日：2002-03-06
申请人： Shinichiro Tago , Tomohiro Yamana , Yoshimasa Takebe
发明人： Shinichiro Tago , Tomohiro Yamana , Yoshimasa Takebe
IPC分类号： G06F9/32
CPC分类号： G06F9/3806 , G06F9/3848
摘要： An apparatus for branch prediction includes a history register which stores therein history of previous branch instructions, an index generation circuit which generates a first index from an instruction address and the history stored in the history register, a history table which stores therein a portion of the instruction address as a tag and a first value indicative of likelihood of branching in association with the first index, a branch destination buffer which stores therein a branch destination address or predicted branch destination address of an instruction indicated by the instruction address and a second value indicative of likelihood of branching in association with a second index that is at least a portion of the instruction address, and a selection unit which makes a branch prediction by selecting one of the first value and the second value.
摘要翻译：一种用于分支预测的装置包括：历史寄存器，其存储先前分支指令的历史，从指令地址生成第一索引的索引生成电路和存储在历史寄存器中的历史;历史表，其中存储有指示地址作为标签，以及指示与第一索引相关联的分支的可能性的第一值;分支目的地缓冲器，其中存储由指令地址指示的指令的分支目的地地址或预测分支目的地地址，以及第二值指示与作为指令地址的至少一部分的第二索引相关联的分支的可能性，以及通过选择第一值和第二值中的一个进行分支预测的选择单元。

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