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1. 发明授权

US08839210B2 Program performance analysis apparatus 有权
标题翻译：程序性能分析仪
公开(公告)号：US08839210B2
公开(公告)日：2014-09-16
申请号：US12382753
申请日：2009-03-23
申请人： Teruhiko Kamigata , Atsuhiro Suga , Shigeru Kimura
发明人： Teruhiko Kamigata , Atsuhiro Suga , Shigeru Kimura
IPC分类号： G06F9/44 , G06F11/00 , G06F9/45
CPC分类号： G06F11/3612 , G06F11/3428 , G06F2201/865
摘要： To provide a program performance analysis apparatus that can present to a user whether tuning made to a program operating on a predetermined hardware is either good or bad, a performance information acquisition unit for obtaining the performance information of a program, a difference information generation unit for generating difference information by making a comparison between the performance information of a first program and that of a second program obtained by making a change to the first program, and a change evaluation unit for evaluating whether the change is either good or bad are comprised.
摘要翻译：为了提供一种程序性能分析装置，其可以向用户呈现无论对在预定硬件上操作的程序的调谐是好还是坏，执行信息获取单元用于获得程序的性能信息，差异信息生成单元，用于通过对第一程序的性能信息和通过对第一程序进行改变而获得的第二程序的性能信息进行比较来生成差异信息，以及用于评估变化是好还是坏的变化评估单元。

2. 发明申请

US20080313404A1 MULTIPROCESSOR SYSTEM AND OPERATING METHOD OF MULTIPROCESSOR SYSTEM 有权
标题翻译：多处理器系统的多处理器系统和操作方法
公开(公告)号：US20080313404A1
公开(公告)日：2008-12-18
申请号：US12199240
申请日：2008-08-27
申请人： Shinichiro TAGO , Atsuhiro Suga
发明人： Shinichiro TAGO , Atsuhiro Suga
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F2212/271 , G06F2212/601
摘要： According to one aspect of embodiments, a multiprocessor system includes a cache memory corresponding to each of the processors, a hierarchy setting register in which the hierarchical level of each cache memory is set, an access control unit that controls access between each cache memory. The hierarchical level of the cache memory for each processor is stored in a rewritable hierarchy setting register. Each processor handles a cache memory corresponding to another processor as the cache memory having a deeper hierarchy than the cache memory corresponding to the each processor. As the result, each processor can access all the cache memories, and therefore the efficiency of cache memory utilization can be improved and the hierarchical level can be set so that the latency becomes optimal for each application.
摘要翻译：根据实施例的一个方面，多处理器系统包括对应于每个处理器的高速缓存存储器，其中设置每个高速缓存存储器的层级的层次结构设置寄存器，控制每个高速缓冲存储器之间的访问的访问控制单元。每个处理器的高速缓冲存储器的层次级存储在可重写层次结构设置寄存器中。每个处理器处理与另一个处理器相对应的高速缓冲存储器，因为高速缓冲存储器具有比对应于每个处理器的高速缓冲存储器更深的层级。结果，每个处理器可以访问所有高速缓冲存储器，因此可以提高高速缓冲存储器利用率的效率，并且可以设置层次级别，使得等待时间对于每个应用来说是最佳的。

3. 发明授权

US06868472B1 Method of Controlling and addressing a cache memory which acts as a random address memory to increase an access speed to a main memory 失效
标题翻译：控制和寻址作为随机地址存储器以增加对主存储器的访问速度的高速缓冲存储器的方法
公开(公告)号：US06868472B1
公开(公告)日：2005-03-15
申请号：US09671117
申请日：2000-09-28
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Teruhiko Kamigata , Hitoshi Yoda , Hiroshi Okano , Yoshio Hirose
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Teruhiko Kamigata , Hitoshi Yoda , Hiroshi Okano , Yoshio Hirose
IPC分类号： G06F12/08 , G06F12/12 , G06F12/00
CPC分类号： G06F12/0802 , G06F2212/2515
摘要： In a cache memory control method and computer of the present invention, a cache memory is connected to a main memory and divided into a plurality of cache blocks, and a lock/unlock signal is supplied to the cache memory to either set a replace-inhibition state of at least one of the cache blocks in which replacing at least one of the cache blocks to the main memory is inhibited, or reset the replace-inhibition state of at least one of the cache clocks such that replacing at least one of the cache block to the main memory is allowed. Either reading or writing of the main memory is performed by using the remaining cache blocks of the cache memory, other than the at least one of the cache blocks, such that, when the replace-inhibition state is set by the lock/unlock signal, replacing the at least one of the cache blocks to the main memory is inhibited during the reading or writing of the main memory.
摘要翻译：在本发明的高速缓冲存储器控制方法和计算机中，高速缓存存储器连接到主存储器并被分成多个高速缓存块，并且锁定/解锁信号被提供给高速缓冲存储器以设置替换抑制禁止将至少一个高速缓存块替换为主存储器的至少一个缓存块的状态，或者重置至少一个高速缓冲存储器时钟的替换禁止状态，使得更换高速缓存中的至少一个阻塞到主内存是允许的。通过使用高速缓冲存储器的其余高速缓冲存储器（除了至少一个高速缓存块之外）来执行读取或写入主存储器，使得当通过锁定/解锁信号设置替换禁止状态时，在主存储器的读取或写入期间禁止将至少一个缓存块替换到主存储器。

4. 发明授权

US06374334B1 Data processing apparatus with a cache controlling device 失效
标题翻译：具有高速缓存控制装置的数据处理装置
公开(公告)号：US06374334B1
公开(公告)日：2002-04-16
申请号：US08954561
申请日：1997-10-20
申请人： Atsuhiro Suga , Akitoshi Ino , Tsutomu Tanaka , Hideki Sakata
发明人： Atsuhiro Suga , Akitoshi Ino , Tsutomu Tanaka , Hideki Sakata
IPC分类号： G06F1208
CPC分类号： G06F9/3824 , G06F12/0855
摘要： A data processing apparatus temporarily stores data to a cache write buffer and then stores the data in a cache storing device. The cache storage device performs a data storage operation with precedence over another operation even if a store instruction contends with a read instruction for accessing the cache storing device. A storage request low signal, sent from a cache write buffer controlling device to a cache controlling device, allows a read request to have precedence over a store instruction even when there is data stored in the cache write buffer waiting to be transferred to the cache storing device in response to the store instruction. However, when the read instruction contends with the store instruction and a state transition signal, such as an instruction cancellation signal generated from an instruction controlling device, is detected, the cache write buffer controlling device changes the output signal to a storage request high signal that causes the storage operation to have precedence over the read operation.
摘要翻译：数据处理装置将数据临时存储到高速缓存写入缓冲器，然后将数据存储在高速缓存存储装置中。即使存储指令与用于访问高速缓存存储装置的读指令进行竞争，高速缓存存储装置优先执行另一操作的数据存储操作。从高速缓存写入缓冲器控制装置发送到高速缓存控制装置的存储请求低信号允许读请求优先于存储指令，即使当存储在高速缓存写入缓冲器中的数据等待被传送到高速缓冲存储器时设备响应商店指令。然而，当读取指令与存储指令相抵触时，检测到诸如从指令控制装置产生的指令消除信号的状态转移信号时，高速缓存写入缓冲器控制装置将输出信号改变为存储请求高信号，导致存储操作优先于读取操作。

5. 发明授权

US06078993A Data supplying apparatus for independently performing hit determination and data access 失效
公开(公告)号：US06078993A
公开(公告)日：2000-06-20
申请号：US672485
申请日：1996-06-26
申请人： Takuya Iwata , Atsuhiro Suga
发明人： Takuya Iwata , Atsuhiro Suga
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F9/3802 , G06F12/0855 , G06F12/0875
摘要： An address buffer that stores information used to access a data memory is disposed in a cache unit that supplies data such as an instruction code to an instruction executing unit. A tag memory and a data memory are independently accessed. The data memory is accessed corresponding to access information stored in the address buffer. Data is output from the data memory in the input order of data requests. When a data release signal is not received from the instruction executing unit, since access information is buffered in the address buffer, a large data buffer for storing the output data of the data memory is not required. In addition, in an associative type cache unit, the tag memory and the address buffer can be formed in the same memory.

6. 发明授权

US5828860A Data processing device equipped with cache memory and a storage unit for storing data between a main storage or CPU cache memory 失效
标题翻译：配备有高速缓冲存储器的数据处理装置和用于在主存储器或CPU缓存存储器之间存储数据的存储单元
公开(公告)号：US5828860A
公开(公告)日：1998-10-27
申请号：US739062
申请日：1996-10-28
申请人： Hitoshi Miyaoku , Atsuhiro Suga , Koichi Sasamori , Kazuhide Yoshino
发明人： Hitoshi Miyaoku , Atsuhiro Suga , Koichi Sasamori , Kazuhide Yoshino
IPC分类号： G06F9/312 , G06F9/38 , G06F12/08
CPC分类号： G06F9/3814 , G06F12/0855 , G06F12/0862 , G06F9/30043 , G06F9/3802 , G06F9/3824 , G06F9/383 , G06F2212/6022 , G06F2212/6028
摘要： A data processing device includes a cache memory, a load buffer primary (LBP) for storing 1-line instruction data including an instruction requested to be transmitted by an instruction processing unit and transmitted from a main storage or a secondary cache memory, and a load buffer secondary (LBS) for storing 1-line instruction data preceded by the above described 1-line data. With this configuration, the device may determine the validity of prefetched data in the LBP using lower order bits of the addresses of the data. If the data are determined to be valid, the data stored in the LBS are stored in the cache memory. A cache storage device, hierarchically provided between a central processing unit a n d a main storage device, includes a cache memory, a storage buffer, a write-in buffer and a cache storage control unit. The cache storage device fast writes storage data into a write-in buffer instead of directly into cache memory. In the case of a miss in an access to a cache tag during the execution of a load command, move-in data are read out from the main storage device or a cache storage device of a different hierarchy, for storage into a write-in buffer. The data stored in the write-in buffer are then written into cache memory when the central processing unit executes another store command.
摘要翻译：数据处理装置包括高速缓存存储器，用于存储包括由指令处理单元请求发送并从主存储器或辅助高速缓存存储器发送的指令的1行指令数据的加载缓冲器初级（LBP）和负载用于存储在上述1行数据之前的1行指令数据的缓存次级（LBS）。利用该配置，设备可以使用数据的地址的低位来确定LBP中预取数据的有效性。如果数据被确定为有效，则存储在LBS中的数据被存储在高速缓冲存储器中。分层地设置在主存储装置的中央处理单元之间的高速缓存存储装置包括高速缓冲存储器，存储缓冲器，写入缓冲器和高速缓存存储控制单元。高速缓存存储设备将存储数据快速写入写入缓冲区，而不是直接写入高速缓存。在执行加载命令期间访问高速缓存标签的错误的情况下，从主存储设备或不同层次的高速缓存存储设备读出移入数据，以存储到写入缓冲。当中央处理单元执行另一个存储命令时，存储在写入缓冲器中的数据被写入高速缓冲存储器。

7. 发明授权

US07401204B1 Parallel Processor efficiently executing variable instruction word 有权
标题翻译：并行处理器有效执行可变指令字
公开(公告)号：US07401204B1
公开(公告)日：2008-07-15
申请号：US09654527
申请日：2000-09-01
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Yoshimasa Takebe
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Yoshimasa Takebe
IPC分类号： G06F15/00
CPC分类号： G06F9/382 , G06F9/3802 , G06F9/3853
摘要： A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information. The processor includes: a plurality of instruction execution units performing processes in accordance with corresponding, supplied basic instructions in parallel; an instruction fetch unit fetching the instruction words one by one in accordance with the instruction delimiting information; and an instruction issue unit recognizing and, in accordance therewith, selecting each of the basic instructions contained in each of the instruction words fetched by the instruction fetch unit to a corresponding instruction execution unit to execute the basic instruction.
摘要翻译：并行处理器对包含在由指令定界信息定界的多个指令字中的每个指令字中的一个或多个基本指令执行高效的并行处理。处理器包括：多个指令执行单元，并行地执行根据相应的所提供的基本指令的处理; 指令读取单元根据指令定界信息逐个取出指令字; 以及指令发布单元，其识别并且根据其选择包含在由指令获取单元获取的每个指令字中的每个基本指令给相应的指令执行单元以执行基本指令。

8. 发明申请

US20060224870A1 Information processing device 审中-公开
标题翻译：信息处理装置
公开(公告)号：US20060224870A1
公开(公告)日：2006-10-05
申请号：US11444221
申请日：2006-05-31
申请人： Shin-ichiro Tago , Taizo Sato , Yoshimasa Takebe , Yasuhiro Yamazaki , Teruhiko Kamigata , Atsuhiro Suga , Hiroshi Okano , Hitoshi Yoda
发明人： Shin-ichiro Tago , Taizo Sato , Yoshimasa Takebe , Yasuhiro Yamazaki , Teruhiko Kamigata , Atsuhiro Suga , Hiroshi Okano , Hitoshi Yoda
IPC分类号： G06F9/00
CPC分类号： G06F9/3804 , G06F9/3806 , G06F9/3846
摘要： The present invention is defined in that an information processing device which reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing comprises: an instruction reading request portion which assigns a read address to the instruction store portion; an instruction buffering portion including a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion; a branching instruction detection portion which detects a branching instruction in the instruction sequence read from the instruction store portion; and a branch target address information buffering portion including a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction; wherein, when the branching instruction detection portion has detected a branching instruction, either the branch target address information of the branching instruction is stored in one of the plurality of branch target address information buffers, or the branch target instruction sequence of the branching instruction is stored in one of the plurality of instruction buffers in addition to the storing in the branch target address information buffer.
摘要翻译：本发明的定义在于，通过流水线处理从指令存储部分读取，缓冲，解码和执行指令的信息处理设备包括：指令读取请求部分，其向指令存储部分分配读取地址; 指令缓冲部分，包括缓冲从指令存储部分读取的指令序列的多个指令缓冲器; 指令执行单元，其对由指令缓冲部分缓冲的指令进行解码和执行; 分支指令检测部分，其检测从指令存储部分读取的指令序列中的分支指令; 以及分支目标地址信息缓冲部分，包括多个分支目标地址信息缓冲器，当分支指令检测部分已经检测到分支指令时，缓冲用于生成分支指令的分支目标地址的转移目标地址信息; 其中，当分支指令检测部分已经检测到分支指令时，分支指令的分支目标地址信息被存储在多个分支目标地址信息缓冲器中的一个中，或分支指令的分支目标指令序列被存储除了存储在分支目标地址信息缓冲器之外，还包括在多个指令缓冲器之一中。

9. 发明授权

US07028151B2 Information processing device equipped with improved address queue register files for cache miss 失效
标题翻译：信息处理设备配备改进的地址队列寄存器文件，用于缓存未命中
公开(公告)号：US07028151B2
公开(公告)日：2006-04-11
申请号：US10643223
申请日：2003-08-19
申请人： Satoshi Imai , Fumihiko Hayakawa , Atsuhiro Suga
发明人： Satoshi Imai , Fumihiko Hayakawa , Atsuhiro Suga
IPC分类号： G06F12/00
CPC分类号： G06F12/0859
摘要： When an input address AD is previously stored in a register 211, if a matching signal EQ1 is active, then an address queue control circuit 19A latches an offset of the input address AD into a register 241, or else, latches the input address AD into a register 212 through a selector 262. When the input address AD is previously stored in the register 241, the address queue control circuit 19A latches the input address AD into the register 212 through the selector 262. After reading the contents of the register 211, the address queue control circuit 19A shifts the offset OFS of the register 241 to the offset field of the register 211 through a selector 261, and resets a valid flag EF of the register 241.
摘要翻译：当输入地址AD预先存储在寄存器211中时，如果匹配信号EQ1有效，则地址队列控制电路19A将输入地址AD的偏移锁存到寄存器241中，否则锁存输入地址 AD通过选择器262进入寄存器212。当输入地址AD预先存储在寄存器241中时，地址队列控制电路19A通过选择器262将输入地址AD锁存到寄存器212中。在读取寄存器211的内容之后，地址队列控制电路19A通过选择器261将寄存器241的偏移量OFS移位到寄存器211的偏移场，并且复位寄存器241的有效标志EF。

10. 发明授权

US06889315B2 Processor and method of controlling the same 失效
标题翻译：处理器和控制方法
公开(公告)号：US06889315B2
公开(公告)日：2005-05-03
申请号：US09736357
申请日：2000-12-15
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/3834 , G06F9/30076 , G06F9/30087 , G06F9/3832 , G06F9/3842 , G06F9/3861
摘要： The present invention relates to a processor that performs a load operation prior to a store operation while avoiding ambiguous memory reference, and achieves high-speed operations. The present invention also relates to a method of controlling such a processor. This processor includes a history control unit that stores a storage destination of a result obtained by executing a second instruction that is executed prior to a first instruction placed before the second instruction. When it is determined that the address of first data to be processed by the first instruction is included in the address region of second data to be processed by the second instruction, the history control unit overwrites the result obtained by the execution of the first instruction on the second data corresponding to the address.
摘要翻译：本发明涉及一种在存储操作之前执行加载操作同时避免不明确的存储器参考并且实现高速操作的处理器。本发明还涉及一种控制这种处理器的方法。该处理器包括历史控制单元，其存储通过执行在第二指令之前放置的第一指令之前执行的第二指令而获得的结果的存储目的地。当确定要由第一指令处理的第一数据的地址被包括在要由第二指令处理的第二数据的地址区域中时，历史控制单元将通过执行第一指令获得的结果覆盖第二个数据对应地址。

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