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1. 发明授权

US5521411A Transistor spacer etch pinpoint structure 失效
标题翻译：晶体管间隔蚀刻精确点结构
公开(公告)号：US5521411A
公开(公告)日：1996-05-28
申请号：US271565
申请日：1994-07-07
申请人： Fusen E. Chen , Frank R. Bryant , Girish A. Dixit
发明人： Fusen E. Chen , Frank R. Bryant , Girish A. Dixit
IPC分类号： H01L21/266 , H01L21/336 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/6659 , H01L21/266 , H01L29/6656
摘要： A method is provided for forming a transistor spacer etch endpoint structure of an integrated circuit, and an integrated circuit formed according to the same. A gate is formed over a portion of a substrate. A dielectric layer is formed over the integrated circuit and an oxide layer is formed over the dielectric layer. the oxide layer is patterned and etched to form sidewall oxide spacers on each side of the gate and over a portion of the dielectric layer. The dielectric layer not covered by the sidewall oxide spacers is then removed.
摘要翻译：提供一种用于形成集成电路的晶体管间隔物蚀刻端点结构的方法，以及根据该集成电路形成的集成电路。栅极形成在衬底的一部分上。在集成电路上形成电介质层，并且在电介质层上形成氧化物层。对氧化物层进行图案化和蚀刻以在栅极的每一侧和电介质层的一部分上形成侧壁氧化物间隔物。然后除去未被侧壁氧化物间隔物覆盖的电介质层。

2. 发明授权

US5493144A Field progammable device with contact openings 失效
标题翻译：具有接触开口的现场可操作装置
公开(公告)号：US5493144A
公开(公告)日：1996-02-20
申请号：US258609
申请日：1994-06-10
申请人： Frank R. Bryant , Fusen E. Chen , Girish A. Dixit
发明人： Frank R. Bryant , Fusen E. Chen , Girish A. Dixit
IPC分类号： H01L21/82 , H01L21/768 , H01L21/822 , H01L23/522 , H01L23/525 , H01L27/04 , H01L23/48 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： H01L23/5252 , H01L2924/0002 , Y10S148/055
摘要： A method is provided for forming a field programmable device of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first conductive layer is formed. A first, fusible, dielectric layer is formed over the first conductive layer. The dielectric layer is patterned and etched to form a plurality of dielectric regions exposing portions of the first conductive layer. A second dielectric layer is then formed over the dielectric regions and the exposed portions of the first conductive layer. A plurality of contact openings through the second dielectric layer are formed to expose portions of the first conductive layer and portions of the dielectric regions. A second conductive layer is then formed over the second dielectric layer and in the contact openings.
摘要翻译：提供一种用于形成半导体集成电路的现场可编程器件的方法和根据该集成电路形成的集成电路。形成第一导电层。在第一导电层上形成第一可熔介电层。对介电层进行构图和蚀刻以形成露出第一导电层的部分的多个电介质区域。然后在电介质区域和第一导电层的暴露部分上形成第二电介质层。形成穿过第二电介质层的多个接触开口以暴露第一导电层和电介质区域的部分。然后在第二介电层上和接触开口中形成第二导电层。

3. 发明授权

US5233135A Interconnect for integrated circuits 失效
标题翻译：集成电路互连
公开(公告)号：US5233135A
公开(公告)日：1993-08-03
申请号：US722702
申请日：1991-06-28
申请人： Fusen E. Chen , Frank R. Bryant , Girish A. Dixit
发明人： Fusen E. Chen , Frank R. Bryant , Girish A. Dixit
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76877 , H01L21/76816 , H01L21/76829 , H01L23/53214 , H01L2924/0002
摘要： A technique for forming metal interconnect signal lines provides for planarization of an interlevel dielectric layer. A thin layer of material which can function as an etch stop, such as a metal oxide, is formed over the interlevel dielectric. An alignment process is used to pattern and define openings through the etch stop layer where contacts to underlying conductive regions will be formed. Another insulating layer is formed over the etch stop layer, and patterned to define all interconnect signal lines. When the signal line locations are etched away, the etching process stops on the etch stop layer in regions where the signal lines will be, and continues through to the underlying conductive layer where contacts are needed. A metal refill process can be used to then form interconnects and contacts within the etched holes, followed by an anisotropic etchback to remove any metal which lies on top of the upper insulating layer. This results in interconnect and contacts having upper surfaces which are substantially coplanar with the upper insulating layer in which they are formed.

4. 发明授权

US5847457A Structure and method of forming vias 失效
标题翻译：形成通孔的结构和方法
公开(公告)号：US5847457A
公开(公告)日：1998-12-08
申请号：US738040
申请日：1996-10-24
申请人： Fusen E. Chen , Fu-Tai Liou , Girish A. Dixit
发明人： Fusen E. Chen , Fu-Tai Liou , Girish A. Dixit
IPC分类号： H01L23/522 , H01L23/48
CPC分类号： H01L23/5226 , H01L2924/0002
摘要： A method is provided for forming a contact opening or via of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first metal region is formed over an underlying region. A first insulating layer is formed over the integrated circuit. A second insulating layer is then formed over the first insulating layer. A portion of the second insulating layer is etched to expose a portion of the first insulating layer wherein the exposed first insulating layer and the remaining second insulating layer form a substantially planar surface. A metal oxide layer is formed over the exposed first insulating layer and the remaining second insulating layer. A photoresist layer is formed and patterned over the metal oxide layer. The metal oxide layer is then selectively etched to form a via exposing a portion of the first insulating layer. The first insulating layer in the via is then selectively etched to expose a portion of the first metal region. The photoresist layer is removed and a second metal layer is then formed over the metal oxide layer and in the via contacting the first metal region.
摘要翻译：提供一种用于形成半导体集成电路的接触开口或通路的方法，以及根据该集成电路形成的集成电路。在下面的区域上形成第一金属区域。在集成电路上形成第一绝缘层。然后在第一绝缘层上形成第二绝缘层。蚀刻第二绝缘层的一部分以暴露第一绝缘层的一部分，其中暴露的第一绝缘层和剩余的第二绝缘层形成基本平坦的表面。在暴露的第一绝缘层和剩余的第二绝缘层上形成金属氧化物层。在金属氧化物层上形成并图案化光致抗蚀剂层。然后选择性地蚀刻金属氧化物层以形成露出第一绝缘层的一部分的通孔。然后选择性地蚀刻通孔中的第一绝缘层以暴露第一金属区域的一部分。去除光致抗蚀剂层，然后在金属氧化物层上形成第二金属层，并在通孔中与第一金属区接触。

5. 发明授权

US5593921A Method of forming vias 失效
标题翻译：形成通孔的方法
公开(公告)号：US5593921A
公开(公告)日：1997-01-14
申请号：US438167
申请日：1995-05-09
申请人： Fusen E. Chen , Fu-Tai Liou , Girish A. Dixit
发明人： Fusen E. Chen , Fu-Tai Liou , Girish A. Dixit
IPC分类号： H01L21/768 , H01L23/522 , H01L21/441
CPC分类号： H01L21/76802 , Y10S148/043 , Y10S148/118
摘要： A method is provided for forming a contact opening or via of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first metal region is formed over an underlying region. A first insulating layer is formed over the integrated circuit. A second insulating layer is then formed over the first insulating layer. A portion of the second insulating layer is etched to expose a portion of the first insulating layer wherein the exposed first insulating layer and the remaining second insulating layer form a substantially planar surface. A metal oxide layer is formed over the exposed first insulating layer and the remaining second insulating layer. A photoresist layer is formed and patterned over the metal oxide layer. The metal oxide layer is then selectively etched to form a via exposing a portion of the first insulating layer. The first insulating layer in the via is then selectively etched to expose a portion of the first metal region. The photoresist layer is removed and a second metal layer is then formed over the metal oxide layer and in the via contacting the first metal region.
摘要翻译：提供一种用于形成半导体集成电路的接触开口或通路的方法，以及根据该集成电路形成的集成电路。在下面的区域上形成第一金属区域。在集成电路上形成第一绝缘层。然后在第一绝缘层上形成第二绝缘层。蚀刻第二绝缘层的一部分以暴露第一绝缘层的一部分，其中暴露的第一绝缘层和剩余的第二绝缘层形成基本平坦的表面。在暴露的第一绝缘层和剩余的第二绝缘层上形成金属氧化物层。在金属氧化物层上形成并图案化光致抗蚀剂层。然后选择性地蚀刻金属氧化物层以形成露出第一绝缘层的一部分的通孔。然后选择性地蚀刻通孔中的第一绝缘层以暴露第一金属区域的一部分。去除光致抗蚀剂层，然后在金属氧化物层上形成第二金属层，并在通孔中与第一金属区接触。

6. 发明授权

US5348901A Interconnect and resistor for integrated circuits 失效
标题翻译：集成电路的互连和电阻
公开(公告)号：US5348901A
公开(公告)日：1994-09-20
申请号：US911167
申请日：1992-07-09
申请人： Fusen E. Chen , Girish A. Dixit , Robert O. Miller
发明人： Fusen E. Chen , Girish A. Dixit , Robert O. Miller
IPC分类号： H01L21/265 , H01L21/02 , H01L21/316 , H01L21/768 , H01L23/522 , H01L27/00 , H01L27/10 , H01L27/11 , H01L21/205 , H01L21/285
CPC分类号： H01L28/20 , H01L21/76889 , H01L27/1112
摘要： A method is provided for forming a polycrystalline silicon resistive load element of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A lightly doped first conductive layer having a conductivity of a first type. A first oxide layer is formed over the integrated circuit with a first opening therethrough exposing a portion of the first conductive layer. Using the first oxide layer as a mask, the exposed portion of the first conductive layer is then implanted with a dopant of a second conductivity type to form a junction between the exposed portion and the portion covered by the mask. A second oxide region is then formed on a portion of the first oxide layer in the first opening, over the junction and over a portion of the exposed first conductive layer adjacent to the junction. A silicide is formed over the exposed portion of the first conductive layer.
摘要翻译：提供一种用于形成半导体集成电路的多晶硅电阻性负载元件的方法和根据该集成电路形成的集成电路。具有第一类型的导电性的轻掺杂的第一导电层。在集成电路上形成第一氧化物层，其中第一开口穿过其暴露第一导电层的一部分。使用第一氧化物层作为掩模，然后用第二导电类型的掺杂剂注入第一导电层的暴露部分，以形成暴露部分和被掩模覆盖的部分之间的结。然后在第一开口中的第一氧化物层的一部分上形成第二氧化物区域，并且在接合处以及暴露的第一导电层的与接合部相邻的部分上形成第二氧化物区域。在第一导电层的暴露部分上形成硅化物。

7. 发明授权

US5571752A Method of forming a planar contact with a void 失效
标题翻译：与空隙形成平面接触的方法
公开(公告)号：US5571752A
公开(公告)日：1996-11-05
申请号：US370456
申请日：1995-01-09
申请人： Fusen E. Chen , Girish A. Dixit , Robert O. Miller
发明人： Fusen E. Chen , Girish A. Dixit , Robert O. Miller
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L21/283
CPC分类号： H01L21/76843 , H01L21/76877 , Y10S257/915
摘要： A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A first conductive structure is formed over the integrated circuit. A dielectric is formed over the first conductive structure having a contact opening exposing a portion of the underlying first conductive layer. A barrier layer is formed in the bottom of the contact opening. A second, substantially conformal conductive layer is formed by chemical vapor deposition over the dielectric layer; along the sidewalls and in the bottom of the contact opening. A third conductive layer is then formed over the second conductive layer wherein the third conductive layer does not fill the contact opening. The second and third conductive layers are etched to form an interconnect substantially over the contact opening.
摘要翻译：提供了用于图案化集成电路的亚微米半导体层的方法，以及根据该集成电路形成的集成电路。在集成电路上形成第一导电结构。在第一导电结构上形成电介质，其具有暴露下面的第一导电层的一部分的接触开口。阻挡层形成在接触开口的底部。通过化学气相沉积在介电层上形成第二基本上保形的导电层; 沿着接触开口的侧壁和底部。然后在第二导电层上形成第三导电层，其中第三导电层不填充接触开口。第二和第三导电层被蚀刻以形成基本上在接触开口上的互连。

8. 发明授权

US5510294A Method of forming vias for multilevel metallization 失效
标题翻译：形成多层金属化通孔的方法
公开(公告)号：US5510294A
公开(公告)日：1996-04-23
申请号：US453563
申请日：1995-05-26
申请人： Girish A. Dixit , Fusen E. Chen , Alexander Kalnitsky
发明人： Girish A. Dixit , Fusen E. Chen , Alexander Kalnitsky
IPC分类号： H01L21/768 , H01L21/44 , H01L21/467
CPC分类号： H01L21/76804 , Y10S148/105 , Y10S148/106 , Y10S438/978
摘要： A method is provided for forming a via for multilevel metallization of an integrated circuit, and an integrated circuit formed according to the same. A first conductive layer is formed over the integrated circuit. A first dielectric layer is then, formed over the first conductive layer. A second dielectric layer over the first dielectric layer and a second conductive layer is formed over the second dielectric layer. A photoresist layer is formed and patterned over the second conductive layer to expose a portion of the second conductive layer. The second conductive layer is etched to form an opening exposing a portion of the second dielectric layer. The second dielectric layer is then etched in the opening to form partially sloped sidewalls sloping outward at an upper surface of the dielectric layer. The photoresist layer is removed. The remaining second dielectric layer and the first electric layer is then anisotropically etched in the opening exposing the portion of the first conductive layer in the opening. The second conductive layer is then removed. A third conductive layer is deposited over the second dielectric layer and in the opening.
摘要翻译：提供了一种用于形成用于集成电路的多层金属化的通孔的方法，以及根据该集成电路形成的集成电路。在集成电路上形成第一导电层。然后，在第一导电层上形成第一介电层。第二电介质层上的第二电介质层和第二导电层形成在第二介电层上。在第二导电层上形成并图案化光致抗蚀剂层以暴露第二导电层的一部分。蚀刻第二导电层以形成露出第二介电层的一部分的开口。然后在开口中蚀刻第二电介质层，以形成在电介质层的上表面向外倾斜的部分倾斜的侧壁。去除光致抗蚀剂层。然后将剩余的第二电介质层和第一电层在开口中各向异性地蚀刻，露出开口中的第一导电层的部分。然后去除第二导电层。第三导电层沉积在第二介电层上和开口中。

9. 发明授权

US5440166A Planarized isolation structure for CMOS devices 失效
标题翻译： CMOS器件的平面隔离结构
公开(公告)号：US5440166A
公开(公告)日：1995-08-08
申请号：US276039
申请日：1994-07-15
申请人： Girish A. Dixit , Fusen E. Chen , Robert O. Miller
发明人： Girish A. Dixit , Fusen E. Chen , Robert O. Miller
IPC分类号： H01L21/76 , H01L21/762 , H01L21/763 , H01L27/08 , H01L21/473
CPC分类号： H01L21/763 , H01L21/76224 , Y10S148/05
摘要： A field oxide structure is formed within a cavity formed in a semiconductor substrate. The cavity has a U-shaped cross section. A layer of thermal oxide covers the walls and bottom of the cavity, and a region of reflowable glass or spin on glass fills the cavity. A layer of undoped oxide, having an upper surface coplanar with the substrate upper surface is formed over the cavity, so that the spin on or reflowable glass is completely surrounded by either thermal oxide or an undoped oxide layer.
摘要翻译：在形成在半导体衬底中的空腔内形成场氧化物结构。空腔具有U形横截面。一层热氧化物覆盖空腔的壁和底部，玻璃上可旋转的区域或玻璃上的旋转填充空腔。在空腔之上形成具有与基板上表面共面的上表面的未掺杂氧化物层，使得旋转或可回流玻璃被热氧化物或未掺杂的氧化物层完全包围。

10. 发明授权

US5317192A Semiconductor contact via structure having amorphous silicon side walls 失效
标题翻译：具有非晶硅侧壁的半导体接触通孔结构
公开(公告)号：US5317192A
公开(公告)日：1994-05-31
申请号：US879190
申请日：1992-05-06
申请人： Fusen E. Chen , Girish A. Dixit , Che-Chia Wei
发明人： Fusen E. Chen , Girish A. Dixit , Che-Chia Wei
IPC分类号： H01L21/28 , H01L21/768 , H01L23/522 , H01L23/532 , H01L29/400
CPC分类号： H01L23/5226 , H01L21/76801 , H01L21/76804 , H01L21/76814 , H01L21/76831 , H01L23/5329 , H01L23/53295 , H01L2924/0002
摘要： A method is provided for forming an integrated circuit contact structure. A conductive region is formed on a semiconductor device. Thereafter an insulating layer is formed over the conductive region. An opening is then formed through the insulating region to the conductive region. A thin barrier layer is deposited over the integrated circuit contact structure. A portion of the thin barrier layer is removed by backsputtering the integrated circuit contact structure so that only a thin barrier sidewall remains. Finally, a conductive metal layer is deposited over the integrated circuit contact structure. In one embodiment, the integrated circuit contact structure is baked before the conductive metal layer is deposited.
摘要翻译：提供了一种用于形成集成电路接触结构的方法。在半导体器件上形成导电区域。此后，在导电区域上形成绝缘层。然后通过绝缘区域形成到导电区域的开口。薄的势垒层沉积在集成电路接触结构上。通过反向溅射集成电路接触结构来去除薄势垒层的一部分，使得只有薄的阻挡侧壁保留。最后，在集成电路接触结构上沉积导电金属层。在一个实施例中，在沉积导电金属层之前烘烤集成电路接触结构。

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