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1. 发明授权

US06399479B1 Processes to improve electroplating fill 有权
标题翻译：改善电镀填充的工艺
公开(公告)号：US06399479B1
公开(公告)日：2002-06-04
申请号：US09386077
申请日：1999-08-30
申请人： Fusen Chen , Zheng Xu , Peijun Ding , Barry Chin , Ashok Sinha
发明人： Fusen Chen , Zheng Xu , Peijun Ding , Barry Chin , Ashok Sinha
IPC分类号： H01L214763
CPC分类号： H01L21/76862 , H01L21/76865 , H01L21/76868 , H01L21/76873 , H01L21/76877
摘要： The invention provides a method for filling a structure on a substrate comprising: depositing a barrier layer on one or more surfaces of the structure, depositing a seed layer over the barrier layer, removing a portion of the seed layer, and electrochemically depositing a metal to fill the structure. Preferably, a portion or all of the seed layer formed on the sidewall portion of the structure is removed using a electrochemical de-plating process prior to the electroplating process.
摘要翻译：本发明提供了一种用于在衬底上填充结构的方法，包括：在结构的一个或多个表面上沉积阻挡层，在阻挡层上沉积种子层，去除种子层的一部分，以及电化学沉积金属填写结构。优选地，在电镀工艺之前使用电化学去镀工艺去除在结构的侧壁部分上形成的种子层的一部分或全部。

2. 发明申请

US20070241458A1 Metal / metal nitride barrier layer for semiconductor device applications 失效
标题翻译：用于半导体器件应用的金属/金属氮化物阻挡层
公开(公告)号：US20070241458A1
公开(公告)日：2007-10-18
申请号：US11809153
申请日：2007-05-30
申请人： Peijun Ding , Zheng Xu , Hong Zhang , Xianmin Tang , Praburam Gopalraja , Suraj Rengarajan , John Forster , Jianming Fu , Tony Chiang , Gongda Yao , Fusen Chen , Barry Chin , Gene Kohara
发明人： Peijun Ding , Zheng Xu , Hong Zhang , Xianmin Tang , Praburam Gopalraja , Suraj Rengarajan , John Forster , Jianming Fu , Tony Chiang , Gongda Yao , Fusen Chen , Barry Chin , Gene Kohara
IPC分类号： H01L23/48
CPC分类号： H01L21/02183 , C23C14/024 , C23C14/046 , C23C14/0641 , C23C14/165 , C23C14/541 , C23C14/5806 , H01L21/022 , H01L21/02266 , H01L21/02271 , H01L21/02362 , H01L21/2855 , H01L21/318 , H01L21/76846 , H01L21/76856 , H01L21/76862 , H01L21/76876 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A metal/metal nitride barrier layer for semiconductor device applications. The barrier layer is particularly useful in contact vias where high conductivity of the via is important, and a lower resistivity barrier layer provides improved overall via conductivity.
摘要翻译：用于半导体器件应用的金属/金属氮化物阻挡层。阻挡层在通孔的高导电性很重要的接触孔中特别有用，并且较低电阻率的阻挡层提供改进的整体通孔导电性。

3. 发明申请

US20050085068A1 Method of depositing a metal seed layer on semiconductor substrates 失效
标题翻译：在半导体衬底上沉积金属种子层的方法
公开(公告)号：US20050085068A1
公开(公告)日：2005-04-21
申请号：US10981319
申请日：2004-11-03
申请人： Tony Chiang , Gongda Yao , Peijun Ding , Fusen Chen , Barry Chin , Gene Kohara , Zheng Xu , Hong Zhang
发明人： Tony Chiang , Gongda Yao , Peijun Ding , Fusen Chen , Barry Chin , Gene Kohara , Zheng Xu , Hong Zhang
IPC分类号： H01L21/285 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76843 , C23C14/046 , C23C14/165 , H01L21/2855 , H01L21/76805 , H01L21/76844 , H01L21/76846 , H01L21/76862 , H01L21/76865 , H01L21/76871 , H01L21/76877 , H01L21/76879 , H01L21/76883
摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper. In the application of a barrier layer, a first portion of barrier layer material is deposited on the substrate surface using standard sputtering techniques or using an ion deposition plasma, but in combination with sufficiently low substrate bias voltage (including at no applied substrate voltage) that the surfaces impacted by ions are not sputtered in an amount which is harmful to device performance or longevity. Subsequently, a second portion of barrier material is applied using ion deposition sputtering at increased substrate bias voltage which causes resputtering (sculpturing) of the first portion of barrier layer material, while enabling a more anisotropic deposition of newly depositing material. A conductive material, and particularly a copper seed layer applied to the feature may be accomplished using the same sculpturing technique as that described above with reference to the barrier layer.
摘要翻译：我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染，所述方法包括步骤：a）以足够低的衬底偏压施加雕刻层的第一部分，使得施加所述雕刻层的表面不会以对所述半导体器件的性能或寿命有害的量被腐蚀掉或污染; 以及b）将所述雕刻层的后续部分施加足够高的衬底偏压，以从所述第一部分雕刻形状，同时沉积附加层材料。该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层，并且当导电层是铜时尤其有用。在施加阻挡层时，使用标准溅射技术或使用离子沉积等离子体将阻挡层材料的第一部分沉积在衬底表面上，但是与足够低的衬底偏置电压（包括没有施加的衬底电压）组合，受离子影响的表面不会以对器件性能或寿命有害的量溅射。随后，使用离子沉积溅射在增加的衬底偏置电压下施加阻挡材料的第二部分，这导致阻挡层材料的第一部分的再溅射（雕刻），同时能够进行更多的各向异性沉积新沉积的材料。应用于特征的导电材料，特别是铜种子层可以使用与上述参考阻挡层所述相同的雕刻技术来实现。

4. 发明申请

US20070178682A1 Damage-free sculptured coating deposition 审中-公开
标题翻译：无损伤雕刻涂层沉积
公开(公告)号：US20070178682A1
公开(公告)日：2007-08-02
申请号：US11733671
申请日：2007-04-10
申请人： Tony Chiang , Gongda Yao , Peijun Ding , Fusen Chen , Barry Chin , Gene Kohara , Zheng Xu , Hong Zhang
发明人： Tony Chiang , Gongda Yao , Peijun Ding , Fusen Chen , Barry Chin , Gene Kohara , Zheng Xu , Hong Zhang
IPC分类号： H01L21/20
CPC分类号： H01L21/76843 , C23C14/046 , C23C14/165 , H01L21/2855 , H01L21/76805 , H01L21/76844 , H01L21/76846 , H01L21/76862 , H01L21/76865 , H01L21/76871 , H01L21/76877 , H01L21/76879 , H01L21/76883
摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of: a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper. In the application of a barrier layer, a first portion of barrier layer material is deposited on the substrate surface using standard sputtering techniques or using an ion deposition plasma, but in combination with sufficiently low substrate bias voltage (including at no applied substrate voltage) that the surfaces impacted by ions are not sputtered in an amount which is harmful to device performance or longevity. Subsequently, a second portion of barrier material is applied using ion deposition sputtering at increased substrate bias voltage which causes resputtering (sculpturing) of the first portion of barrier layer material, while enabling a more anisotropic deposition of newly depositing material. A conductive material, and particularly a copper seed layer applied to the feature may be accomplished using the same sculpturing technique as that described above with reference to the barrier layer.
摘要翻译：我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染，所述方法包括步骤：a）以足够低的衬底偏压施加雕刻层的第一部分，使得施加所述雕刻层的表面不会以对所述半导体器件的性能或寿命有害的量被侵蚀或污染; 以及b）将所述雕刻层的后续部分施加足够高的衬底偏压，以从所述第一部分雕刻形状，同时沉积附加层材料。该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层，并且当导电层是铜时尤其有用。在施加阻挡层时，使用标准溅射技术或使用离子沉积等离子体将阻挡层材料的第一部分沉积在衬底表面上，但是与足够低的衬底偏置电压（包括没有施加的衬底电压）组合，受离子影响的表面不会以对器件性能或寿命有害的量溅射。随后，使用离子沉积溅射在增加的衬底偏置电压下施加阻挡材料的第二部分，这导致阻挡层材料的第一部分的再溅射（雕刻），同时能够进行更多的各向异性沉积新沉积的材料。应用于特征的导电材料，特别是铜种子层可以使用与上述参考阻挡层所述相同的雕刻技术来实现。

5. 发明申请

US20050020080A1 Method of depositing a diffusion barrier layer and a metal conductive layer 审中-公开
标题翻译：沉积扩散阻挡层和金属导电层的方法
公开(公告)号：US20050020080A1
公开(公告)日：2005-01-27
申请号：US10922052
申请日：2004-08-18
申请人： Tony Chiang , Gongda Yao , Peijun Ding , Fusen Chen , Barry Chin , Gene Kohara , Zheng Xu , Hong Zhang
发明人： Tony Chiang , Gongda Yao , Peijun Ding , Fusen Chen , Barry Chin , Gene Kohara , Zheng Xu , Hong Zhang
IPC分类号： H01L21/285 , H01L21/768 , H01L21/4763 , H01L21/302 , H01L21/461
CPC分类号： H01L21/76843 , C23C14/046 , C23C14/165 , H01L21/2855 , H01L21/76805 , H01L21/76844 , H01L21/76846 , H01L21/76862 , H01L21/76865 , H01L21/76871 , H01L21/76877 , H01L21/76879 , H01L21/76883
摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of: a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper. In the application of a barrier layer, a first portion of barrier layer material is deposited on the substrate surface using standard sputtering techniques or using all ion deposition plasma, but in combination with sufficiently low substrate bias voltage (including at no applied substrate voltage) that the surfaces impacted by ions are not sputtered in an amount which is harmful to device performance or longevity. Subsequently, a second portion of barrier material is applied using ion deposition sputtering at increased substrate bias voltage which causes resputtering (sculpturing) or the first portion of barrier layer material, while enabling a more anisotropic deposition of newly depositing material. A conductive material, and particularly a copper seed layer applied to the feature may be accomplished using the same sculpturing technique as that described above with reference to the barrier layer.
摘要翻译：我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染，所述方法包括步骤：a）以足够低的衬底偏压施加雕刻层的第一部分，使得施加所述雕刻层的表面不会以对所述半导体器件的性能或寿命有害的量被侵蚀或污染; 以及b）将所述雕刻层的后续部分施加足够高的衬底偏压，以从所述第一部分雕刻形状，同时沉积附加层材料。该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层，并且当导电层是铜时尤其有用。在施加阻挡层时，使用标准溅射技术或使用所有离子沉积等离子体将阻挡层材料的第一部分沉积在衬底表面上，但是与足够低的衬底偏置电压（包括没有施加的衬底电压）相结合，受离子影响的表面不会以对器件性能或寿命有害的量溅射。随后，使用离子沉积溅射以增加的衬底偏置电压施加阻挡材料的第二部分，其引起再溅射（雕刻）或阻挡层材料的第一部分，同时能够进行更多的各向异性沉积新沉积材料。应用于特征的导电材料，特别是铜种子层可以使用与上述参考阻挡层所述相同的雕刻技术来实现。

6. 发明申请

US20050272254A1 Method of depositing low resistivity barrier layers for copper interconnects 审中-公开
标题翻译：沉积用于铜互连的低电阻阻挡层的方法
公开(公告)号：US20050272254A1
公开(公告)日：2005-12-08
申请号：US11184404
申请日：2005-07-18
申请人： Peijun Ding , Zheng Xu , Hong Zhang , Xianmin Tang , Praburam Gopalraja , Suraj Rengarajan , John Forster , Jianming Fu , Tony Chiang , Gongda Yao , Fusen Chen , Barry Chin , Gene Kohara
发明人： Peijun Ding , Zheng Xu , Hong Zhang , Xianmin Tang , Praburam Gopalraja , Suraj Rengarajan , John Forster , Jianming Fu , Tony Chiang , Gongda Yao , Fusen Chen , Barry Chin , Gene Kohara
IPC分类号： C23C14/06 , C23C14/16 , C23C14/32 , H01L21/285 , H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/02183 , C23C14/0641 , C23C14/165 , C23C14/541 , C23C14/5806 , H01L21/02266 , H01L21/2855 , H01L21/318 , H01L21/76846 , H01L21/76856 , H01L21/76862 , H01L21/76876
摘要： We have discovered a method of providing a thin approximately from about 2 Å to about 100 Å thick TaN seed layer, which can be used to induce the formation of alpha tantalum when tantalum is deposited over the TaN seed layer. Further, the TaN seed layer exhibits low resistivity, in the range of 30 μΩ cm and can be used as a low resistivity barrier layer in the absence of an alpha tantalum layer. In one embodiment of the method, a TaN film is altered on its surface form the TaN seed layer. In another embodiment of the method, a Ta film is altered on its surface to form the TaN seed layer.
摘要翻译：我们已经发现了一种提供大约约2埃至大约100埃的Ta N种子层的薄膜的方法，当钽沉积在Ta上时可用于诱导形成α钽， SUB> N 种子层。此外，Ta N N种子层在30μΩ·cm的范围内显示低电阻率，并且可以在不存在α钽层的情况下用作低电阻率阻挡层。在该方法的一个实施方案中，TaN膜在其表面上形成Ta N N种子层。在该方法的另一个实施方案中，在其表面上改变Ta膜以形成Ta N N种子层。

7. 发明申请

US20070020922A1 Method of depositing a metal seed layer on semiconductor substrates 有权
标题翻译：在半导体衬底上沉积金属种子层的方法
公开(公告)号：US20070020922A1
公开(公告)日：2007-01-25
申请号：US11450703
申请日：2006-06-09
申请人： Tony Chiang , Gongda Yao , Peijun Ding , Fusen Chen , Barry Chin , Gene Kohara , Zheng Xu , Hong Zhang
发明人： Tony Chiang , Gongda Yao , Peijun Ding , Fusen Chen , Barry Chin , Gene Kohara , Zheng Xu , Hong Zhang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , C23C14/046 , C23C14/165 , H01L21/2855 , H01L21/76805 , H01L21/76844 , H01L21/76846 , H01L21/76862 , H01L21/76865 , H01L21/76871 , H01L21/76877 , H01L21/76879 , H01L21/76883
摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.
摘要翻译：我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻的材料层的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染。使用传统的溅射或离子沉积溅射将第一保护层材料沉积在衬底表面上，结合足够低的衬底偏压，使得施加层的表面在保护层沉积期间不被腐蚀掉或被污染。随后，使用离子沉积溅射在增加的衬底偏压下施加雕刻的第二材料层，以从材料的第一保护层的一部分和第二沉积材料层的一部分雕刻出形状。该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层。

8. 发明申请

US20050208767A1 Method of depositing a tantalum nitride / tantalum diffusion barrier layer system 失效
标题翻译：沉积氮化钽/钽扩散阻挡层体系的方法
公开(公告)号：US20050208767A1
公开(公告)日：2005-09-22
申请号：US11069348
申请日：2005-02-28
申请人： Peijun Ding , Zheng Xu , Hong Zhang , Xianmin Tang , Praburam Gopalraja , Suraj Rengarajan , John Forster , Jianming Fu , Tony Chiang , Gongda Yao , Fusen Chen , Barry Chin , Gene Kohara
发明人： Peijun Ding , Zheng Xu , Hong Zhang , Xianmin Tang , Praburam Gopalraja , Suraj Rengarajan , John Forster , Jianming Fu , Tony Chiang , Gongda Yao , Fusen Chen , Barry Chin , Gene Kohara
IPC分类号： C23C14/06 , C23C14/16 , C23C14/32 , H01L21/285 , H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/02183 , C23C14/024 , C23C14/046 , C23C14/0641 , C23C14/165 , C23C14/541 , C23C14/5806 , H01L21/022 , H01L21/02266 , H01L21/02271 , H01L21/02362 , H01L21/2855 , H01L21/318 , H01L21/76846 , H01L21/76856 , H01L21/76862 , H01L21/76876 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： We have discovered a method of providing a thin, approximately from about 2 Å to about 100 Å thick TaN seed layer, which can be used to induce the formation of alpha tantalum when tantalum is deposited over the TaN seed layer. Further, the TaN seed layer exhibits low resistivity, in the range of 30 μΩcm and can be used as a low resistivity barrier layer in the absence of an alpha tantalum layer. In one embodiment of the method, a TaN film is altered on its surface to form the TaN seed layer. In another embodiment of the method, a Ta film is altered on its surface to form the TaN seed layer.
摘要翻译：我们已经发现了一种提供大约从大约2埃到大约100埃的Ta N种子层的薄的方法，其可以在钽沉积在Ta上时用于诱导形成α钽 N种子层。此外，Ta N N种子层在30微米范围内显示低电阻率，并且可以在不存在α钽层的情况下用作低电阻率阻挡层。在该方法的一个实施方案中，在其表面上改变TaN膜以形成Ta N N种子层。在该方法的另一个实施方案中，在其表面上改变Ta膜以形成Ta N N种子层。

9. 发明授权

US08696875B2 Self-ionized and inductively-coupled plasma for sputtering and resputtering 有权
标题翻译：用于溅射和再溅射的自电离和电感耦合等离子体
公开(公告)号：US08696875B2
公开(公告)日：2014-04-15
申请号：US10495506
申请日：2002-11-14
申请人： Peijun Ding , Rong Tao , Zheng Xu , Daniel C. Lubben , Suraj Rengarajan , Michael A. Miller , Arvind Sundarrajan , Xianmin Tang , John C. Forster , Jianming Fu , Roderick C. Mosely , Fusen Chen , Praburam Gopalraja
发明人： Peijun Ding , Rong Tao , Zheng Xu , Daniel C. Lubben , Suraj Rengarajan , Michael A. Miller , Arvind Sundarrajan , Xianmin Tang , John C. Forster , Jianming Fu , Roderick C. Mosely , Fusen Chen , Praburam Gopalraja
IPC分类号： C23C14/35
CPC分类号： C23C14/046 , C23C14/345 , C23C14/3457 , C23C14/35 , C23C14/358 , C23C14/564 , C23C14/568 , H01J37/321 , H01J37/3402 , H01J37/3408 , H01J37/3441 , H01J2237/3327 , H01L21/2855 , H01L21/76805 , H01L21/76814 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76862 , H01L21/76865 , H01L21/76868 , H01L21/76871 , H01L21/76873 , H01L21/76876 , H01L21/76877 , H01L2221/1089
摘要： A magnetron sputter reactor (410) and its method of use, in which SIP sputtering and ICP sputtering are promoted is disclosed. In another chamber (412) an array of auxiliary magnets positioned along sidewalls (414) of a magnetron sputter reactor on a side towards the wafer from the target is disclosed. The magnetron (436) preferably is a small one having a stronger outer pole (442) of a first polarity surrounding a weaker inner pole (440) of a second polarity all on a yoke (444) and rotates about the axis (438) of the chamber using rotation means (446, 448, 450). The auxiliary magnets (462) preferably have the first polarity to draw the unbalanced magnetic field (460) towards the wafer (424), which is on a pedestal (422) supplied with power (454). Argon (426) is supplied through a valve (428). The target (416) is supplied with power (434).
摘要翻译：公开了一种促进SIP溅射和ICP溅射的磁控溅射反应器（410）及其使用方法。在另一个室（412）中，公开了一种辅助磁体阵列，其沿着磁控溅射反应器的侧面（414）定位，所述磁控溅射反应器在朝向晶片的一侧朝向靶。优选地，磁控管（436）是小的，其具有第一极性的更强的外极（442），其具有围绕轭（444）的第二极性的较弱内极（440），并且围绕轴线（438）旋转所述腔室使用旋转装置（446,448,450）。辅助磁体（462）优选地具有第一极性，以将不平衡磁场（460）朝着被提供电力（454）的基座（422）上的晶片（424）拉出。氩（426）通过阀（428）供应。目标（416）被供电（434）。

10. 发明授权

US07294574B2 Sputter deposition and etching of metallization seed layer for overhang and sidewall improvement 有权
标题翻译：金属化种子层的溅射沉积和蚀刻用于悬垂和侧壁改进
公开(公告)号：US07294574B2
公开(公告)日：2007-11-13
申请号：US10915139
申请日：2004-08-09
申请人： Peijun Ding , Fuhong Zhang , Hsien-Lung Yang , Michael A. Miller , Jianming Fu , Jick M. Yu , Zheng Xu , Fusen Chen
发明人： Peijun Ding , Fuhong Zhang , Hsien-Lung Yang , Michael A. Miller , Jianming Fu , Jick M. Yu , Zheng Xu , Fusen Chen
IPC分类号： H01L21/44
CPC分类号： H01L21/2855 , H01L21/76843 , H01L21/76865 , H01L21/76873 , H01L2221/1089
摘要： An integrated sputtering method and reactor for copper or aluminum seed layers in which a plasma sputter reactor initially deposits a thin conformal layer onto a substrate including a high-aspect ratio hole subject to the formation of overhangs. After the seed deposition, the same sputter reactor is used to sputter etch the substrate with energetic light ions, especially helium, having an energy sufficiently low that it selectively etches the metallization to the heavier underlying barrier layer, for example, copper over tantalum or aluminum over titanium. An RF inductive coil generates the plasma during the sputtering etching while the target power is turned off. A final copper flash step deposits copper over the bare barrier field region before copper is electrochemically plated to fill the hole. The invention also includes a simultaneous sputter deposition and sputter etch, and an energetic ion processing of the copper seed sidewall.
摘要翻译：一种用于铜或铝种子层的集成溅射方法和反应器，其中等离子体溅射反应器最初将薄的共形层沉积到包括形成突出端的高纵横比孔的基板上。在种子沉积之后，使用相同的溅射反应器以能量足够低的能量的能量轻离子（特别是氦）溅射蚀刻衬底，以使其能够将金属化选择性地蚀刻到较重的下层阻挡层，例如钽或铝上的铜超过钛。 RF感应线圈在溅射蚀刻期间产生等离子体，同时关闭目标电源。在铜电化学镀以填充孔之前，最终的铜闪光步骤将铜沉积在裸露的屏障场区域上。本发明还包括同时溅射沉积和溅射蚀刻以及铜种子侧壁的能量离子处理。

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