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1. 发明申请

US20120217571A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20120217571A1
公开(公告)日：2012-08-30
申请号：US13402477
申请日：2012-02-22
申请人： Fumitaka ARAI , Satoshi Nagashima , Hisataka Meguro , Hideto Takekida , Kenta Yamada
发明人： Fumitaka ARAI , Satoshi Nagashima , Hisataka Meguro , Hideto Takekida , Kenta Yamada
IPC分类号： H01L29/792 , H01L21/76
CPC分类号： H01L27/11524 , G11C16/0466 , H01L27/11551 , H01L29/66825 , H01L29/7881
摘要： Nonvolatile semiconductor memory device includes first memory cell array layer, first insulating layer formed thereabove, and second memory cell array layer formed thereabove. First memory cell array layer includes first NAND cell units each including plural first memory cells. The first memory cell includes first semiconductor layer, first gate insulating film formed thereabove, and first charge accumulation layer formed thereabove. The second memory cell array layer includes second NAND cell units each including plural second memory cells. The second memory cell includes second charge accumulation layer, second gate insulating film formed thereabove, and second semiconductor layer formed thereabove. Control gates are formed, via an inter-gate insulating film, on first-direction both sides of the first and second charge accumulation layers positioned the latter above the former via the first insulating layer. The control gates extend in a second direction perpendicular to the first direction.
摘要翻译：非易失性半导体存储器件包括第一存储单元阵列层，形成在其上的第一绝缘层和形成在其上的第二存储单元阵列层。第一存储单元阵列层包括每个包括多个第一存储单元的第一NAND单元单元。第一存储单元包括形成在其上的第一半导体层，第一栅极绝缘膜和在其上形成的第一电荷累积层。第二存储单元阵列层包括每个包括多个第二存储单元的第二NAND单元单元。第二存储单元包括第二电荷累积层，在其上形成的第二栅极绝缘膜，以及在其上形成的第二半导体层。控制栅极经由栅极间绝缘膜，在第一和第二电荷累积层的第一方向两侧经由第一绝缘层位于前者之上。控制门在垂直于第一方向的第二方向延伸。

2. 发明授权

US08624317B2 Nonvolatile semiconductor memory device and method for manufacturing same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08624317B2
公开(公告)日：2014-01-07
申请号：US13402477
申请日：2012-02-22
申请人： Fumitaka Arai , Satoshi Nagashima , Hisataka Meguro , Hideto Takekida , Kenta Yamada
发明人： Fumitaka Arai , Satoshi Nagashima , Hisataka Meguro , Hideto Takekida , Kenta Yamada
IPC分类号： H01L29/792
CPC分类号： H01L27/11524 , G11C16/0466 , H01L27/11551 , H01L29/66825 , H01L29/7881
摘要： Nonvolatile semiconductor memory device includes first memory cell array layer, first insulating layer formed thereabove, and second memory cell array layer formed thereabove. First memory cell array layer includes first NAND cell units each including plural first memory cells. The first memory cell includes first semiconductor layer, first gate insulating film formed thereabove, and first charge accumulation layer formed thereabove. The second memory cell array layer includes second NAND cell units each including plural second memory cells. The second memory cell includes second charge accumulation layer, second gate insulating film formed thereabove, and second semiconductor layer formed thereabove. Control gates are formed, via an inter-gate insulating film, on first-direction both sides of the first and second charge accumulation layers positioned the latter above the former via the first insulating layer. The control gates extend in a second direction perpendicular to the first direction.
摘要翻译：非易失性半导体存储器件包括第一存储单元阵列层，形成在其上的第一绝缘层和形成在其上的第二存储单元阵列层。第一存储单元阵列层包括每个包括多个第一存储单元的第一NAND单元单元。第一存储单元包括形成在其上的第一半导体层，第一栅极绝缘膜和在其上形成的第一电荷累积层。第二存储单元阵列层包括每个包括多个第二存储单元的第二NAND单元单元。第二存储单元包括第二电荷累积层，在其上形成的第二栅极绝缘膜，以及在其上形成的第二半导体层。控制栅极经由栅极间绝缘膜，在第一和第二电荷累积层的第一方向两侧经由第一绝缘层位于前者之上。控制门在垂直于第一方向的第二方向延伸。

3. 发明授权

US08541830B1 Nonvolatile semiconductor memory device and method for manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08541830B1
公开(公告)日：2013-09-24
申请号：US13601468
申请日：2012-08-31
申请人： Satoshi Nagashima , Fumitaka Arai , Hisataka Meguro
发明人： Satoshi Nagashima , Fumitaka Arai , Hisataka Meguro
IPC分类号： H01L29/788 , H01L21/336 , G11C11/34
CPC分类号： H01L27/088 , H01L21/28273 , H01L27/11524 , H01L27/11551 , H01L29/788 , H01L29/7881
摘要： A nonvolatile semiconductor memory device according to an embodiment includes a plurality of cell array layers, each cell array layer including: a plurality of semiconductor layers that extends in a first direction; gate insulating layers; a plurality of floating gates arranged in the first direction; inter-gate insulating layers; and a plurality of control gates that extends in a second direction intersecting semiconductor layers, and faces the floating gates via the inter-gate insulating layers, in which, in the cell array layers adjacent each other in a stacking direction, the control gates of a lower cell array layer and the control gates of the an upper cell array layer are intersecting each other, and the floating gates within the lower cell array layer and the semiconductor layers within the upper cell array layer are aligned in position with each other.
摘要翻译：根据实施例的非易失性半导体存储器件包括多个单元阵列层，每个单元阵列层包括：沿第一方向延伸的多个半导体层; 栅绝缘层; 沿所述第一方向布置的多个浮动栅极; 栅极间绝缘层; 以及多个控制栅极，其在与半导体层交叉的第二方向上延伸，并且经由所述栅极间绝缘层面向所述浮置栅极，其中，在层叠方向上彼此相邻的所述单元阵列层中，所述控制栅极下单元阵列层和上单元阵列层的控制栅极彼此相交，并且下单元阵列层内的浮置栅极和上单元阵列层内的半导体层彼此对准。

4. 发明授权

US09059035B2 Nonvolatile semiconductor device and its manufacturing method having memory cells with multiple layers 有权
标题翻译：非易失性半导体器件及其具有多层存储单元的制造方法
公开(公告)号：US09059035B2
公开(公告)日：2015-06-16
申请号：US13606757
申请日：2012-09-07
申请人： Satoshi Nagashima , Fumitaka Arai , Hisataka Meguro
发明人： Satoshi Nagashima , Fumitaka Arai , Hisataka Meguro
IPC分类号： H01L29/788 , H01L27/115 , H01L21/28 , H01L29/66 , H01L29/423 , G11C16/04
CPC分类号： H01L21/28273 , G11C16/0408 , H01L27/11524 , H01L27/11551 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： A nonvolatile semiconductor memory device a first memory cell array layer, a first insulation layer formed on top of the first memory cell array layer, a second memory cell array layer formed on the first insulation layer, and a control gate. The first and second memory cell array layers have first and second NAND cell units provided with multiple first and second memory cells connected in series in a first direction and the first and second selection gates connected at both ends of the multiple first and second memory cells. The control gate is formed via an insulation layer between gates of the memory cells on both sides thereof in the first direction, and extends in the second direction perpendicular to the first direction.
摘要翻译：非易失性半导体存储器件，第一存储单元阵列层，形成在第一存储单元阵列层顶部的第一绝缘层，形成在第一绝缘层上的第二存储单元阵列层和控制栅极。第一和第二存储单元阵列层具有第一和第二NAND单元单元，其具有在第一方向上串联连接的多个第一和第二存储单元，并且第一和第二选择栅极连接在多个第一和第二存储单元的两端。控制栅极是通过在其第一方向的两侧的存储单元的栅极之间的绝缘层形成的，并且在垂直于第一方向的第二方向上延伸。

5. 发明申请

US20100295134A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20100295134A1
公开(公告)日：2010-11-25
申请号：US12560313
申请日：2009-09-15
申请人： Satoshi Nagashima , Fumitaka Arai , Hisataka Meguro , Hiroshi Akahori
发明人： Satoshi Nagashima , Fumitaka Arai , Hisataka Meguro , Hiroshi Akahori
IPC分类号： H01L27/11 , H01L21/8239
CPC分类号： H01L27/11524 , H01L27/11519 , H01L27/11521
摘要： A semiconductor memory device according to one embodiment includes: a semiconductor substrate having an active region divided by an element isolation region; a plurality of stacked-gate type memory cell transistors connected in series on the active region; select transistors connected to both ends of the plurality of memory cell transistors on the active region; and a bit line contact connected to a drain region belonging to the select transistor in the active region, a vertical cross sectional shape of a lower portion of the bit line contact in a channel width direction of the plurality of memory cell transistors being in a skirt shape.
摘要翻译：根据一个实施例的半导体存储器件包括：半导体衬底，其具有由元件隔离区域划分的有源区域; 在有源区上串联连接的多个堆叠栅型存储单元晶体管; 连接到有源区上的多个存储单元晶体管的两端的选择晶体管; 以及与有源区域中属于选择晶体管的漏极区域连接的位线接触部，位于多个存储单元晶体管的沟道宽度方向上的位线接触的下部的垂直截面形状位于裙部形状。

6. 发明授权

US08975178B2 Method of manufacturing a memory device using fine patterning techniques 有权
标题翻译：使用精细图案化技术制造存储器件的方法
公开(公告)号：US08975178B2
公开(公告)日：2015-03-10
申请号：US13602841
申请日：2012-09-04
申请人： Keisuke Kikutani , Satoshi Nagashima , Hidefumi Mukai , Takehiro Kondoh , Hisataka Meguro
发明人： Keisuke Kikutani , Satoshi Nagashima , Hidefumi Mukai , Takehiro Kondoh , Hisataka Meguro
IPC分类号： H01L21/4763 , H01L21/768 , H01L21/033 , H01L21/3213 , H01L27/115
CPC分类号： H01L21/76801 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L27/11519 , H01L27/11524 , H01L27/11548 , H01L27/11565 , H01L27/1157 , H01L27/11575
摘要： According to one embodiment, a method of manufacturing a device, includes forming a first core including a line portion extending between first and second regions and having a first width and a fringe having a dimension larger than the first width, forming a mask on the fringe and on a first sidewall on the first core, removing the first core so that a remaining portion having a dimension larger than the first width is formed below the mask, forming a second sidewall on a pattern corresponding the first sidewall and the remaining portion, the second sidewall having a second width less than the first width and facing a first interval less than the first width in the first region and facing a second interval larger than the first interval in the second region.
摘要翻译：根据一个实施例，一种制造器件的方法包括形成包括在第一和第二区域之间延伸的线部分并具有第一宽度和具有大于第一宽度的尺寸的条纹的第一芯体，在边缘上形成掩模并且在所述第一芯上的第一侧壁上，移除所述第一芯，使得具有大于所述第一宽度的尺寸的剩余部分形成在所述掩模下方，在对应于所述第一侧壁和所述剩余部分的图案上形成第二侧壁，第二侧壁具有小于第一宽度的第二宽度并且面向小于第一区域中的第一宽度的第一间隔并且面向大于第二区域中的第一间隔的第二间隔。

7. 发明授权

US07868376B2 Semiconductor storage device and method for manufacturing the same 失效
公开(公告)号：US07868376B2
公开(公告)日：2011-01-11
申请号：US12354271
申请日：2009-01-15
申请人： Kenji Aoyama , Hisataka Meguro , Satoshi Nagashima
发明人： Kenji Aoyama , Hisataka Meguro , Satoshi Nagashima
IPC分类号： H01L29/792
CPC分类号： H01L21/28247 , H01L21/76229 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.

8. 发明申请

US20090218614A1 SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20090218614A1
公开(公告)日：2009-09-03
申请号：US12354271
申请日：2009-01-15
申请人： Kenji AOYAMA , Hisataka Meguro , Satoshi Nagashima
发明人： Kenji AOYAMA , Hisataka Meguro , Satoshi Nagashima
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28247 , H01L21/76229 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.
摘要翻译：半导体存储装置具有在半导体衬底上形成有预定间隔的多个字线，设置在多个字线的端部的选择晶体管，形成为覆盖字线的侧面的第一绝缘膜所述选择晶体管的侧面以及所述字线之间的所述半导体基板的表面，形成在所述第一绝缘膜上的高电容率膜，形成为覆盖所述字线的上表面的第二绝缘膜，以及选择晶体管，位于字线之间并被高电容率膜和第二绝缘膜包围的第一气隙部分和经由第一绝缘膜和高介电常数膜形成的第二气隙部分，与选择晶体管相邻的字线相对的选择晶体管的侧壁部分，第二气隙部分的上部被第二i 记录膜。

9. 发明授权

US08748965B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US08748965B2
公开(公告)日：2014-06-10
申请号：US13197263
申请日：2011-08-03
申请人： Satoshi Nagashima , Junya Fujita , Hideyuki Yamawaki , Masahiro Kiyotoshi , Hisataka Meguro
发明人： Satoshi Nagashima , Junya Fujita , Hideyuki Yamawaki , Masahiro Kiyotoshi , Hisataka Meguro
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11526 , H01L27/11529 , H01L29/42324
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor obtained by sequentially stacking the gate insulation film, the floating gate electrode, the interelectrode insulation film, and the control gate electrode over the channel semiconductor layer. The control gate electrode has a structure obtained by sequentially stacking the semiconductor film, the silicide phase-change suppressing layer, and the silicide film. In addition, the silicide phase-change suppressing layer includes a polycrystalline silicon film in which at least one of C, F, and N is doped in a concentration range of 1×1020 to 5×1021 [atom/cm3].
摘要翻译：根据一个实施例，非易失性半导体存储器件包括通过在沟道半导体层上依次层叠栅绝缘膜，浮栅电极，电极间绝缘膜和控制栅电极而获得的存储单元晶体管。控制栅电极具有通过顺序堆叠半导体膜，硅化物相变抑制层和硅化物膜而获得的结构。此外，硅化物相变抑制层包括在1×1020〜5×1021 [原子/ cm3]的浓度范围内掺杂有C，F和N中的至少一种的多晶硅膜。

10. 发明授权

US08071449B2 Semiconductor storage device and method for manufacturing the same 失效
标题翻译：半导体存储装置及其制造方法
公开(公告)号：US08071449B2
公开(公告)日：2011-12-06
申请号：US12926677
申请日：2010-12-03
申请人： Kenji Aoyama , Hisataka Meguro , Satoshi Nagashima
发明人： Kenji Aoyama , Hisataka Meguro , Satoshi Nagashima
IPC分类号： H01L21/336
CPC分类号： H01L21/28247 , H01L21/76229 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.
摘要翻译：半导体存储装置具有在半导体衬底上形成有预定间隔的多个字线，设置在多个字线的端部的选择晶体管，形成为覆盖字线的侧面的第一绝缘膜所述选择晶体管的侧面以及所述字线之间的所述半导体基板的表面，形成在所述第一绝缘膜上的高电容率膜，形成为覆盖所述字线的上表面的第二绝缘膜，以及选择晶体管，位于字线之间并被高电容率膜和第二绝缘膜包围的第一气隙部分和经由第一绝缘膜和高介电常数膜形成的第二气隙部分，与选择晶体管相邻的字线相对的选择晶体管的侧壁部分，第二气隙部分的上部被第二i 记录膜。

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