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1. 发明申请

US20120217571A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20120217571A1
公开(公告)日：2012-08-30
申请号：US13402477
申请日：2012-02-22
申请人： Fumitaka ARAI , Satoshi Nagashima , Hisataka Meguro , Hideto Takekida , Kenta Yamada
发明人： Fumitaka ARAI , Satoshi Nagashima , Hisataka Meguro , Hideto Takekida , Kenta Yamada
IPC分类号： H01L29/792 , H01L21/76
CPC分类号： H01L27/11524 , G11C16/0466 , H01L27/11551 , H01L29/66825 , H01L29/7881
摘要： Nonvolatile semiconductor memory device includes first memory cell array layer, first insulating layer formed thereabove, and second memory cell array layer formed thereabove. First memory cell array layer includes first NAND cell units each including plural first memory cells. The first memory cell includes first semiconductor layer, first gate insulating film formed thereabove, and first charge accumulation layer formed thereabove. The second memory cell array layer includes second NAND cell units each including plural second memory cells. The second memory cell includes second charge accumulation layer, second gate insulating film formed thereabove, and second semiconductor layer formed thereabove. Control gates are formed, via an inter-gate insulating film, on first-direction both sides of the first and second charge accumulation layers positioned the latter above the former via the first insulating layer. The control gates extend in a second direction perpendicular to the first direction.
摘要翻译：非易失性半导体存储器件包括第一存储单元阵列层，形成在其上的第一绝缘层和形成在其上的第二存储单元阵列层。第一存储单元阵列层包括每个包括多个第一存储单元的第一NAND单元单元。第一存储单元包括形成在其上的第一半导体层，第一栅极绝缘膜和在其上形成的第一电荷累积层。第二存储单元阵列层包括每个包括多个第二存储单元的第二NAND单元单元。第二存储单元包括第二电荷累积层，在其上形成的第二栅极绝缘膜，以及在其上形成的第二半导体层。控制栅极经由栅极间绝缘膜，在第一和第二电荷累积层的第一方向两侧经由第一绝缘层位于前者之上。控制门在垂直于第一方向的第二方向延伸。

2. 发明授权

US08624317B2 Nonvolatile semiconductor memory device and method for manufacturing same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08624317B2
公开(公告)日：2014-01-07
申请号：US13402477
申请日：2012-02-22
申请人： Fumitaka Arai , Satoshi Nagashima , Hisataka Meguro , Hideto Takekida , Kenta Yamada
发明人： Fumitaka Arai , Satoshi Nagashima , Hisataka Meguro , Hideto Takekida , Kenta Yamada
IPC分类号： H01L29/792
CPC分类号： H01L27/11524 , G11C16/0466 , H01L27/11551 , H01L29/66825 , H01L29/7881
摘要： Nonvolatile semiconductor memory device includes first memory cell array layer, first insulating layer formed thereabove, and second memory cell array layer formed thereabove. First memory cell array layer includes first NAND cell units each including plural first memory cells. The first memory cell includes first semiconductor layer, first gate insulating film formed thereabove, and first charge accumulation layer formed thereabove. The second memory cell array layer includes second NAND cell units each including plural second memory cells. The second memory cell includes second charge accumulation layer, second gate insulating film formed thereabove, and second semiconductor layer formed thereabove. Control gates are formed, via an inter-gate insulating film, on first-direction both sides of the first and second charge accumulation layers positioned the latter above the former via the first insulating layer. The control gates extend in a second direction perpendicular to the first direction.
摘要翻译：非易失性半导体存储器件包括第一存储单元阵列层，形成在其上的第一绝缘层和形成在其上的第二存储单元阵列层。第一存储单元阵列层包括每个包括多个第一存储单元的第一NAND单元单元。第一存储单元包括形成在其上的第一半导体层，第一栅极绝缘膜和在其上形成的第一电荷累积层。第二存储单元阵列层包括每个包括多个第二存储单元的第二NAND单元单元。第二存储单元包括第二电荷累积层，在其上形成的第二栅极绝缘膜，以及在其上形成的第二半导体层。控制栅极经由栅极间绝缘膜，在第一和第二电荷累积层的第一方向两侧经由第一绝缘层位于前者之上。控制门在垂直于第一方向的第二方向延伸。

3. 发明授权

US08099706B2 Software product for semiconductor device design 有权
标题翻译：半导体器件设计软件产品
公开(公告)号：US08099706B2
公开(公告)日：2012-01-17
申请号：US12213412
申请日：2008-06-19
申请人： Kenta Yamada
发明人： Kenta Yamada
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A software product including codes for the method of determining parasitic resistance and capacitance from a layout of an LSI is executed by a computer. The method is achieved by providing a plurality of patterns of a wiring structure which contains a target interconnection; and by producing a library configured to store parameters indicating the parasitic resistance and the parasitic capacitance in relation to the target interconnection to each of the plurality of patterns. The producing is achieved by calculating the parameters to a plurality of conditions corresponding to deviation in manufacture of the wiring structure for each of the plurality of patterns.
摘要翻译：由计算机执行包括从LSI的布局确定寄生电阻和电容的方法的代码的软件产品。该方法通过提供包含目标互连的布线结构的多个图案来实现; 并且通过产生一个库，该库被配置为将指示与目标互连相关的寄生电阻和寄生电容的参数存储到多个模式中的每一个。通过将参数计算为与多个图案中的每一个的布线结构的制造偏差相对应的多个条件来实现。

4. 发明授权

US08069427B2 Method and program for designing semiconductor integrated circuit using peripheral parameter 有权
标题翻译：使用周边参数设计半导体集成电路的方法和程序
公开(公告)号：US08069427B2
公开(公告)日：2011-11-29
申请号：US12219056
申请日：2008-07-15
申请人： Kenta Yamada
发明人： Kenta Yamada
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5068
摘要： A method of designing a semiconductor integrated circuit includes: performing a circuit simulation of a cell with changing a parameter that specifies a layout pattern around the cell; and generating a delay function expressing a delay value of the cell as a function of the parameter, based on a result of the circuit simulation. The method further includes: generating a layout data indicating a layout of the semiconductor integrated circuit, based on a cell-based design technique. The method further includes: referring to the generated layout data to extract the parameter associated with a target cell included in the semiconductor integrated circuit; and calculating a delay value of the target cell by using the extracted parameter and the delay function.
摘要翻译：一种设计半导体集成电路的方法包括：通过改变指定单元周围的布局图案的参数来执行单元的电路仿真; 以及基于所述电路仿真的结果，生成表示所述单元的延迟值作为所述参数的函数的延迟函数。该方法还包括：基于基于单元的设计技术，生成表示半导体集成电路布局的布局数据。该方法还包括：参照生成的布局数据，提取与半导体集成电路中包含的目标单元相关联的参数; 以及通过使用提取的参数和延迟函数来计算目标小区的延迟值。

5. 发明授权

US08056020B2 Method of designing semiconductor integrated circuit and mask data generation program 有权
标题翻译：设计半导体集成电路和掩模数据生成程序的方法
公开(公告)号：US08056020B2
公开(公告)日：2011-11-08
申请号：US12219057
申请日：2008-07-15
申请人： Kenta Yamada
发明人： Kenta Yamada
IPC分类号： G06F17/50 , G06F11/22
CPC分类号： G06F17/5068
摘要： A method of designing a semiconductor integrated circuit includes: generating a layout data indicating a layout; and generating a mask data based on the layout data. The generating the mask data includes: referring to the layout data to extract a parameter that specifies a layout pattern around a target transistor included in the semiconductor integrated circuit, wherein the parameter includes at least a width of a device isolation structure around the target transistor; correcting a gate length and a gate width of the target transistor to offset a variation of a characteristic of the target transistor from a design value, the variation depending on the extracted parameter; and generating the mask data from the layout data in which the gate length and the gate width are corrected.
摘要翻译：一种设计半导体集成电路的方法包括：产生指示布局的布局数据; 以及基于所述布局数据生成掩模数据。生成掩模数据包括：参考布局数据以提取指定包括在半导体集成电路中的目标晶体管周围的布局图案的参数，其中该参数至少包括围绕目标晶体管的器件隔离结构的宽度; 校正所述目标晶体管的栅极长度和栅极宽度，以将所述目标晶体管的特性的变化与设计值相抵消，所述变化取决于所提取的参数; 以及从校正栅极长度和栅极宽度的布局数据生成掩模数据。

6. 发明授权

US08042081B2 Method and system for manufacturing a semiconductor device having plural wiring layers 有权
标题翻译：用于制造具有多个布线层的半导体器件的方法和系统
公开(公告)号：US08042081B2
公开(公告)日：2011-10-18
申请号：US12289296
申请日：2008-10-24
申请人： Kenta Yamada
发明人： Kenta Yamada
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A software product including codes for the method of determining parasitic resistance and capacitance from a layout of an LSI is executed by a computer. The method is achieved by providing a plurality of patterns of a wiring structure which contains a target interconnection; and by producing a library configured to store parameters indicating the parasitic resistance and the parasitic capacitance in relation to the target interconnection to each of the plurality of patterns. The producing is achieved by calculating the parameters to a plurality of conditions corresponding to deviation in manufacture of the wiring structure for each of the plurality of patterns.
摘要翻译：由计算机执行包括从LSI的布局确定寄生电阻和电容的方法的代码的软件产品。该方法通过提供包含目标互连的布线结构的多个图案来实现; 并且通过产生一个库，该库被配置为将指示与目标互连相关的寄生电阻和寄生电容的参数存储到多个模式中的每一个。通过将参数计算为与多个图案中的每一个的布线结构的制造偏差相对应的多个条件来实现。

7. 发明授权

US09579870B2 Welded joint of duplex stainless steel 有权
标题翻译：双相不锈钢焊接
公开(公告)号：US09579870B2
公开(公告)日：2017-02-28
申请号：US13984321
申请日：2012-02-10
申请人： Hiroyuki Nagayama , Kenta Yamada , Masahiko Hamada , Daisuke Motoya , Hisashi Amaya
发明人： Hiroyuki Nagayama , Kenta Yamada , Masahiko Hamada , Daisuke Motoya , Hisashi Amaya
IPC分类号： B23K35/30 , B32B15/01 , C22C38/00 , C22C38/02 , C22C38/04 , C22C38/06 , C22C38/42 , C22C38/44 , B23K9/167 , B23K9/173
CPC分类号： B32B15/013 , B23K9/167 , B23K9/173 , B23K35/3033 , B23K35/3053 , B23K2103/04 , B23K2103/05 , B32B15/01 , C22C38/001 , C22C38/002 , C22C38/02 , C22C38/04 , C22C38/06 , C22C38/42 , C22C38/44 , Y10T428/12972
摘要： A welded joint of duplex stainless steel, which can suppress precipitation σ phase under high heat input welding, is excellent in SCC resistance under high-temperature chloride environments. A weld metal of the welded joint contains, in mass percent, C: at most 0.030%, Si: 0.20 to 1.00%, Mn: at most 8.00%, P: at most 0.040%, S: at most 0.0100%, Cu: at most 2.00%, Ni: 7.00 to 12.00%, Cr: 20.0 to 30.0%, Mo: 1 to 4%, N: 0.100 to 0.350%, sol. Al: at most 0.040%, and O: at most 0.035%, the balance being Fe and impurities. The weld metal satisfies Expressions (1) and (3): 2.2Cr+7Mo+3Cu>66 (1) Cr+11Mo+10Ni−12(Cu+30N)
摘要翻译：提供了双相不锈钢的焊接接头，其可以抑制高热输入焊接时的相的析出，并且在高温氯化物环境下具有优异的SCC电阻。根据本发明的双相不锈钢焊接接头的焊接金属以质量％计含有C：0.030％以下，Si：0.20〜1.00％，Mn：8.00％以下，P：0.040％以下， S：0.0100％以下，Cu：2.00％以下，Ni：7.00〜12.00％，Cr：20.0〜30.0％，Mo：1〜4％，N：0.100〜0.350％ Al：0.040％以下，O：0.035％以下，余量为Fe和杂质，焊接金属满足式（1）和式（3）：2.2 ¢Cr + 7 ¢Mo + 3 ¢ Cu> 66 Cr + 11 ¢Mo + 10 ¢Ni-12 Cu + 30 ¢N <100其中贱金属和焊接金属之一中的每种元素的含量（质量百分比）代入表达式（1）和表达式（3）中的每个元素。

8. 发明申请

US20090089037A1 Method and apparatus for circuit simulation in view of stress exerted on MOS transistor 审中-公开
标题翻译：考虑到施加在MOS晶体管上的应力的电路仿真的方法和装置
公开(公告)号：US20090089037A1
公开(公告)日：2009-04-02
申请号：US12285215
申请日：2008-09-30
申请人： Kenta Yamada
发明人： Kenta Yamada
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A circuit simulation method includes: generating graphical data indicating dimensions of a subject MOS transistor; calculating a parameter correction amount based on said graphical data; correcting a given transistor model parameter in response to said parameter correction amount; and performing circuit simulation of a circuit that includes said subject MOS transistor by using said corrected transistor model parameter. The parameter correction amount is calculated based on said graphical data by using arithmetic equations. The arithmetic equations include at least one stress model equation expressing a stress exerted on a channel region of a model MOS transistor. The stress model equation is suitably defined to simulate the stress exerted on the channel region.
摘要翻译：电路模拟方法包括：产生指示对象MOS晶体管的尺寸的图形数据; 基于所述图形数据计算参数校正量; 响应于所述参数校正量来校正给定的晶体管模型参数; 以及通过使用所述校正晶体管模型参数来执行包括所述目标MOS晶体管的电路的电路仿真。通过使用算术方程式，基于所述图形数据计算参数校正量。算术方程式包括至少一个表达施加在模型MOS晶体管的沟道区上的应力的应力模型方程。应力模型方程被适当地定义以模拟施加在通道区域上的应力。

9. 发明申请

US20090024974A1 Method and program for designing semiconductor integrated circuit 失效
标题翻译：半导体集成电路设计方法和程序
公开(公告)号：US20090024974A1
公开(公告)日：2009-01-22
申请号：US12219058
申请日：2008-07-15
申请人： Kenta Yamada
发明人： Kenta Yamada
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5068 , G06F2217/84
摘要： A design method for an LSI includes: generating a delay library for use in a statistical STA, wherein the delay library provides a delay function that expresses a cell delay value as a function of model parameters of a transistor; generating a layout data; and calculating a delay value of a target cell based on the delay library and the layout data. The calculating includes: referring to the layout data to extract a parameter specifying a layout pattern around a target transistor; modulating model parameters of the target transistor such that the characteristics corresponding to the extracted parameter is obtained in a circuit simulation; calculating, by using the delay function, a reference delay value of the target cell; and calculating, by using the delay function and the modulation amount of the model parameter, a delay variation from the reference delay value depending on the modulation amount.
摘要翻译： LSI的设计方法包括：生成用于统计STA的延迟库，其中所述延迟库提供表示作为晶体管的模型参数的函数的单元延迟值的延迟函数; 生成布局数据; 以及基于所述延迟库和所述布局数据计算目标小区的延迟值。计算包括：参考布局数据提取指定围绕目标晶体管的布局图案的参数; 调制目标晶体管的模型参数，使得在电路仿真中获得与提取的参数对应的特性; 通过使用延迟函数计算目标单元的参考延迟值; 并且通过使用延迟函数和模型参数的调制量，根据调制量从参考延迟值计算延迟变化。

10. 发明授权

US07475377B2 Semiconductor device design system and method, and software product for the same 失效
标题翻译：半导体器件设计系统和方法，以及软件产品相同
公开(公告)号：US07475377B2
公开(公告)日：2009-01-06
申请号：US11341581
申请日：2006-01-30
申请人： Kenta Yamada
发明人： Kenta Yamada
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A software product including codes for the method of determining parasitic resistance and capacitance from a layout of an LSI is executed by a computer. The method is achieved by providing a plurality of patterns of a wiring structure which contains a target interconnection; and by producing a library configured to store parameters indicating the parasitic resistance and the parasitic capacitance in relation to the target interconnection to each of the plurality of patterns. The producing is achieved by calculating the parameters to a plurality of conditions corresponding to deviation in manufacture of the wiring structure for each of the plurality of patterns.
摘要翻译：由计算机执行包括从LSI的布局确定寄生电阻和电容的方法的代码的软件产品。该方法通过提供包含目标互连的布线结构的多个图案来实现; 并且通过产生一个库，该库被配置为将指示与目标互连相关的寄生电阻和寄生电容的参数存储到多个模式中的每一个。通过将参数计算为与多个图案中的每一个的布线结构的制造偏差相对应的多个条件来实现。

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