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    • 6. 发明申请
    • SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN APPARATUS, DATA PROCESSING METHOD THEREOF, AND CONTROL PROGRAM THEREOF
    • 半导体集成电路设计装置及其数据处理方法及其控制程序
    • US20120096421A1
    • 2012-04-19
    • US13262759
    • 2010-04-21
    • Yoshihiro OnoTakeshi WatanabeNaoshi DoiItsuki YamadaTsuneo Tsukagoki
    • Yoshihiro OnoTakeshi WatanabeNaoshi DoiItsuki YamadaTsuneo Tsukagoki
    • G06F17/50
    • G06F17/5031
    • A semiconductor integrated circuit design apparatus (100) includes a delay analysis unit (102) which analyzes a static delay in respective paths of a semiconductor integrated circuit, a noise generation unit (104) which generates noise information based on a predetermined noise definition, a voltage fluctuation level analysis unit (106) which analyzes a voltage fluctuation level of the semiconductor integrated circuit when the noise is applied based on the noise information, and a timing verification unit (108) which makes the delay analysis unit (102) analyze the static delay based on the analyzed voltage fluctuation level, to verify timing for operation of the semiconductor integrated circuit based on a result of the static delay analysis, wherein the noise generation unit (104) generates noise information on noise applied at predetermined application timing, and the timing verification unit (108) verifies the timing for each noise applied with the predetermined application timing.
    • 半导体集成电路设计装置(100)包括分析半导体集成电路的各个路径中的静态延迟的延迟分析单元(102),基于预定噪声定义产生噪声信息的噪声生成单元(104) 电压波动电平分析单元(106),其基于噪声信息分析施加了噪声时的半导体集成电路的电压波动水平;以及定时验证单元(108),其使得所述延迟分析单元(102)分析静态 基于所分析的电压波动水平的延迟,基于静态延迟分析的结果来验证半导体集成电路的操作的定时,其中,噪声产生单元(104)产生关于在预定应用定时处施加的噪声的噪声信息,并且 定时验证单元(108)根据预定的应用定时验证每个噪声的定时。