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1. 发明授权

US6104064A Asymmetrical transistor structure 有权
标题翻译：不对称晶体管结构
公开(公告)号：US6104064A
公开(公告)日：2000-08-15
申请号：US306508
申请日：1999-05-06
申请人： Daniel Kadosh , Mark I. Gardner , Michael Duane , Jon D. Cheek , Fred N. Hause , Robert Dawson , Brad T. Moore
发明人： Daniel Kadosh , Mark I. Gardner , Michael Duane , Jon D. Cheek , Fred N. Hause , Robert Dawson , Brad T. Moore
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78 , H01L29/76
CPC分类号： H01L21/28211 , H01L21/28176 , H01L29/66659 , H01L29/7835
摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.
摘要翻译：提供了用于产生p沟道和/或n沟道晶体管的各种工艺。因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。据此，本方法采用各种技术形成不对称晶体管。各种技术采用根据所需LDD结果而变化的处理步骤。首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。可以存在许多其它修改和替代的处理步骤，其全部在此描述。不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

2. 发明授权

US6137182A Method of reducing via and contact dimensions beyond photolithography equipment limits 有权
标题翻译：降低光刻设备限制以外的通孔和接触尺寸的方法
公开(公告)号：US6137182A
公开(公告)日：2000-10-24
申请号：US137471
申请日：1998-08-20
申请人： Fred N. Hause , Mark I. Gardner , Robert Dawson
发明人： Fred N. Hause , Mark I. Gardner , Robert Dawson
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76816
摘要： A semiconductor process for forming an interlevel contact. A semiconductor wafer is provided with a semiconductor substrate, a first conductive layer formed on the substrate, and a dielectric layer formed on the conductive layer. A border layer, preferably comprised of polysilicon or silicon nitride is formed on the dielectric layer. Portions of the border layer are then selectively removed to expose an upper surface of a spacer region of the dielectric layer, the selective removal of the border layer resulting in a border layer having an annular sidewall extending upward from the dielectric layer and encircling the spacer region. A spacer structure is then formed on the annular sidewall, preferably, the spacer structure is formed by chemically vapor depositing a spacer material and anisotropically etching the spacer material to just clear in the planar regions with minimum overetch. The spacer structure thereby covering peripheral portions of the spacer region such that an upper surface of a contact region remains exposed. Portions of the dielectric layer within the contact region are then removed to form a via extending from an upper surface of the spacer structure to an upper surface of the first conductive layer. Preferably, the lateral dimension of the spacer region is approximately equal to the minimum feature size of a photolithography exposure apparatus in the lateral dimension of the via at substantially less than the minimum feature size of the photolithography exposure apparatus.
摘要翻译：一种用于形成层间接触的半导体工艺。半导体晶片设置有半导体衬底，形成在衬底上的第一导电层和形成在导电层上的电介质层。在电介质层上形成优选由多晶硅或氮化硅构成的边界层。然后选择性地去除边界层的部分以暴露电介质层的间隔区域的上表面，选择性地去除边界层，导致边界层具有从电介质层向上延伸并环绕间隔区域的环形侧壁。然后在环形侧壁上形成间隔结构，优选地，间隔物结构通过化学气相沉积间隔物材料形成，并且各向异性地蚀刻间隔物材料，以便在具有最小过氧化物的平面区域中刚好清除。间隔结构由此覆盖间隔区域的周边部分，使得接触区域的上表面保持暴露。然后去除接触区域内的电介质层的部分以形成从间隔物结构的上表面延伸到第一导电层的上表面的通孔。优选地，间隔区域的横向尺寸基本上等于光刻曝光装置在通孔的横向尺寸中的最小特征尺寸，其基本上小于光刻曝光装置的最小特征尺寸。

3. 发明授权

US5843625A Method of reducing via and contact dimensions beyond photolithography equipment limits 失效
标题翻译：降低光刻设备限制以外的通孔和接触尺寸的方法
公开(公告)号：US5843625A
公开(公告)日：1998-12-01
申请号：US685144
申请日：1996-07-23
申请人： Fred N. Hause , Mark I. Gardner , Robert Dawson
发明人： Fred N. Hause , Mark I. Gardner , Robert Dawson
IPC分类号： H01L21/768 , G03F7/00
CPC分类号： H01L21/76816
摘要： A semiconductor process for forming an interlevel contact. A semiconductor wafer is provided with a semiconductor substrate, a first conductive layer formed on the substrate, and a dielectric layer formed on the conductive layer. A border layer, preferably comprising polysilicon or silicon nitride is formed on the dielectric layer. Portions of the border layer are then selectively removed to expose an upper surface of a spacer region of the dielectric layer, the selective removal of the border layer resulting in a border layer having an annular sidewall extending upward from the dielectric layer and encircling the spacer region. A spacer structure is then formed on the annular sidewall. Preferably, the spacer structure is formed by chemically vapor depositing a spacer material and anisotropically etching the spacer material to just clear in the planar regions with minimum overetch. The spacer structure thereby covers peripheral portions of the spacer region such that an upper surface of a contact region remains exposed. Portions of the dielectric layer within the contact region are then removed to form a via extending from an upper surface of the spacer structure to an upper surface of the first conductive layer. Preferably, the lateral dimension of the spacer region is approximately equal to the minimum feature size of a photolithography exposure apparatus in the lateral dimension of the via at substantially less than the minimum feature size of the photolithography exposure apparatus.
摘要翻译：一种用于形成层间接触的半导体工艺。半导体晶片设置有半导体衬底，形成在衬底上的第一导电层和形成在导电层上的电介质层。优选地包括多晶硅或氮化硅的边界层形成在电介质层上。然后选择性地去除边界层的部分以暴露电介质层的间隔区域的上表面，选择性地去除边界层，导致边界层具有从电介质层向上延伸并环绕间隔区域的环形侧壁。然后在环形侧壁上形成间隔结构。优选地，通过化学气相沉积间隔物材料并且各向异性地蚀刻间隔物材料来形成间隔结构，以便在具有最小过蚀刻的平面区域中刚好清除。间隔结构由此覆盖间隔区域的周边部分，使得接触区域的上表面保持暴露。然后去除接触区域内的电介质层的部分以形成从间隔物结构的上表面延伸到第一导电层的上表面的通孔。优选地，间隔区域的横向尺寸基本上等于光刻曝光装置在通孔的横向尺寸中的最小特征尺寸，其基本上小于光刻曝光装置的最小特征尺寸。

4. 发明授权

US5981357A Semiconductor trench isolation with improved planarization methodology 失效
标题翻译：具有改进的平面化方法的半导体沟槽隔离
公开(公告)号：US5981357A
公开(公告)日：1999-11-09
申请号：US877000
申请日：1997-06-16
申请人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
发明人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
IPC分类号： H01L21/76 , H01L21/3105 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/31053 , Y10S148/05
摘要： An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches. The patterned stacked layers incorporate a polysilicon and/or oxide buffer which prevents deleterious migration of nitrogen from the overlying nitride layer to the underlying silicon mesa upper surface.
摘要翻译：提供隔离技术用于改善填充隔离区相对于相邻硅台面的整体平面度。隔离过程产生具有增强的机械和电性能的硅台面。通过重复填充隔离沟槽，图案化大面积隔离沟槽和重新填充隔离沟槽以呈现具有可以通过化学机械抛光容易去除的凹痕的上表面的步骤来执行平面度。通过利用堆叠在硅衬底上的独特的一组层来增强硅台面上表面，然后对衬底进行图案化以形成其上具有堆叠层的凸起的硅表面或台面。图案化的堆叠层包括不同组合物的独特组合，当被去除时，其离开相邻填充沟槽下方的硅台面上表面。图案化的堆叠层包含多晶硅和/或氧化物缓冲液，其可防止氮从上覆的氮化物层到底层的硅台面上表面的有害迁移。

5. 发明授权

US5904539A Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties 失效
标题翻译：半导体沟槽隔离工艺导致硅台面具有增强的机械和电学性能
公开(公告)号：US5904539A
公开(公告)日：1999-05-18
申请号：US619004
申请日：1996-03-21
申请人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
发明人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229 , Y10S148/05
摘要： An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches. The patterned stacked layers incorporate a polysilicon and/or oxide buffer which prevents deleterious migration of nitrogen from the overlying nitride layer to the underlying silicon mesa upper surface.
摘要翻译：提供隔离技术用于改善填充隔离区相对于相邻硅台面的整体平面度。隔离过程产生具有增强的机械和电性能的硅台面。通过重复填充隔离沟槽，图案化大面积隔离沟槽和重新填充隔离沟槽以呈现具有可以通过化学机械抛光容易去除的凹痕的上表面的步骤来执行平面度。通过利用堆叠在硅衬底上的独特的一组层来增强硅台面上表面，然后对衬底进行图案化以形成其上具有堆叠层的凸起的硅表面或台面。图案化的堆叠层包括不同组合物的独特组合，当被去除时，其离开相邻填充沟槽下方的硅台面上表面。图案化的堆叠层包含多晶硅和/或氧化物缓冲液，其可防止氮从上覆的氮化物层到底层的硅台面上表面的有害迁移。

6. 发明授权

US06365943B1 High density integrated circuit 有权
公开(公告)号：US06365943B1
公开(公告)日：2002-04-02
申请号：US09157644
申请日：1998-09-21
申请人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
发明人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
IPC分类号： H01L2976
CPC分类号： H01L21/823437 , Y10S438/947
摘要： A semiconductor transistor which includes a silicon base layer, a gate dielectric formed on the silicon base layer, first and second silicon source/drain structures, first and second spacer structures, and a silicon gate structure is provided. A method for forming the semiconductor transistor may include a semiconductor process in which a dielectric layer is formed on an upper surface of a semiconductor substrate which includes a silicon base layer. Thereafter, an upper silicon layer is formed on an upper surface of the dielectric layer. The dielectric layer and the upper silicon layer are then patterned to form first and second silicon-dielectric stacks on the upper surface of the base silicon layer. The first and second silicon-dielectric stacks are laterally displaced on either side of a channel region of the silicon substrate and each include a proximal sidewall and a distal sidewall. The proximal sidewalls are approximately coincident with respective boundaries of the channel region. Thereafter, proximal and distal spacer structures are formed on the proximal and distal sidewalls respectively of the first and second silicon-dielectric stacks. A gate dielectric layer is then formed on exposed portions of the silicon base layer over a channel region of the base silicon layer. Portions of the first and second silicon-dielectric stacks located over respective source/drain regions of the base silicon layer are then selectively removed. Silicon is then deposited to fill first and second voids created by the selected removal of the stacks. The silicon deposition also fills a silicon gate region above the gate dielectric over the channel region. Thereafter, an impurity distribution is introduced into the deposited silicon. The deposited silicon is then planarized to physically isolate the silicon within the gate region from the silicon within the first and second voids resulting in the formation of a transistor including a silicon gate structure and first and second source/drain structures.

7. 发明授权

US06323561B1 Spacer formation for precise salicide formation 失效
标题翻译：间歇形成精确的自杀化合物形成
公开(公告)号：US06323561B1
公开(公告)日：2001-11-27
申请号：US08987455
申请日：1997-12-09
申请人： Mark I. Gardner , Fred N. Hause , Charles E. May
发明人： Mark I. Gardner , Fred N. Hause , Charles E. May
IPC分类号： H01L27088
CPC分类号： H01L29/66598 , H01L21/266 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： The formation of a spacer for precise salicide formation is disclosed. In one embodiment, a method includes four steps. In the first step, at least one first spacer is formed, where each spacer is adjacent to an edge of a gate on a substrate and has a triangular geometry. In the second step, an ion implantation is applied to form a graded lightly doped region within the substrate underneath each spacer, the region corresponding to the triangular geometry of the spacer. In the third step, at least one second spacer is formed, where each second spacer overlaps a corresponding first spacer. In the fourth step, a metal silicide within the substrate is formed immediately adjacent to each second spacer.
摘要翻译：公开了形成用于精确的自对准硅化物形成的间隔物。在一个实施例中，一种方法包括四个步骤。在第一步骤中，形成至少一个第一间隔物，其中每个间隔物邻近衬底上的栅极的边缘并且具有三角形几何形状。在第二步骤中，施加离子注入以在每个间隔物下面的衬底内形成渐变的轻掺杂区域，该区域对应于间隔物的三角形几何形状。在第三步骤中，形成至少一个第二间隔物，其中每个第二间隔物与相应的第一间隔物重叠。在第四步骤中，衬底内的金属硅化物紧邻每个第二间隔物形成。

8. 发明授权

US6117739A Semiconductor device with layered doped regions and methods of manufacture 有权
标题翻译：具有分层掺杂区域的半导体器件和制造方法
公开(公告)号：US6117739A
公开(公告)日：2000-09-12
申请号：US166000
申请日：1998-10-02
申请人： Mark I. Gardner , Fred N. Hause , Charles E. May
发明人： Mark I. Gardner , Fred N. Hause , Charles E. May
IPC分类号： H01L21/266 , H01L21/336 , H01L29/10 , H01L29/49
CPC分类号： H01L29/66583 , H01L21/266 , H01L29/1083 , H01L29/4966 , H01L29/66537
摘要： A semiconductor device can be formed with active regions disposed in a substrate adjacent to a gate electrode and a doped region, of the same conductivity type as the active regions, embedded beneath the channel region defined by the active regions. In one embodiment, a patterned masking layer having at least one opening is formed over the substrate. A dopant material is implanted into the substrate using the masking layer to form active regions adjacent to the opening and an embedded doped region that is between and spaced apart from the active regions and is deeper in the substrate then the active regions. In addition or alternatively, spacer structures can be formed on the gate electrode by forming a conformal dielectric layer along a bottom surface and at least one sidewall of the opening and forming a gate electrode in the opening over the dielectric layer. The masking layer is then removed to leave the dielectric layer between the gate electrode and the substrate and as spacer structures on the sidewalls of the gate electrode.
摘要翻译：可以形成半导体器件，该有源区域设置在与由栅极电极相邻的衬底中的有源区域和与有源区域相同的导电类型的掺杂区域，嵌入在由有源区域限定的沟道区域的下面。在一个实施例中，在衬底上形成具有至少一个开口的图案化掩模层。使用掩模层将掺杂剂材料注入到衬底中以形成与开口相邻的有源区和位于有源区之间并且与有源区间隔开的嵌入的掺杂区，并且在衬底中更深的是有源区。另外或替代地，可以通过沿着底表面和开口的至少一个侧壁形成保形电介质层并在电介质层上的开口中形成栅电极，在栅电极上形成间隔结构。然后去除掩模层以在栅电极和衬底之间留下介电层，并且作为栅电极的侧壁上的间隔结构。

9. 发明授权

US6087249A Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation 有权
标题翻译：晶体管制造工艺采用公共室进行栅极氧化和栅极导体的形成
公开(公告)号：US6087249A
公开(公告)日：2000-07-11
申请号：US151075
申请日：1998-09-10
申请人： Mark I. Gardner , Fred N. Hause
发明人： Mark I. Gardner , Fred N. Hause
IPC分类号： C23C16/40 , C23C16/452 , H01L21/28 , H01L21/314 , H01L29/51 , H01L21/3205
CPC分类号： H01L21/28202 , C23C16/402 , C23C16/452 , H01L21/28017 , H01L21/28035 , H01L21/3145 , H01L29/513 , H01L29/518 , H01L21/28185 , Y10S438/907 , Y10S438/908
摘要： An integrated circuit transistor is provided having a gate oxide and a gate conductor arranged upon a semiconductor topography, the gate oxide and gate conductor are formed within a common chamber. The initial semiconductor topography includes a silicon substrate having isolation regions disposed within its upper surface. The semiconductor topography may include an defined region, or well, doped opposite the substrate. The semiconductor topography is first placed in the common chamber. A separate chamber is operably placed gaseous communication with the common chamber. A plasma is created within the separate chamber, causing nitrogen, silicon, and oxygen containing compounds therein to form ions, molecular fragments, and excited molecules which are transported to the common chamber. The ions, molecular fragments, and excited molecules react and bombard the surface of the semiconductor topography to form an oxide layer thereon. The oxide layer is incorporated with nitrogen atoms which act as barrier atoms. Polysilicon is then deposited upon the oxide layer by CVD within the common chamber. The semiconductor topography is never exposed to ambient conditions outside the common chamber during and between the plasma oxide formation and the polysilicon deposition steps. Preventing ingress of outside ambient helps minimize contamination from entering the oxide. During the polysilicon deposition, dopant atoms are forwarded and become entrained within the polysilicon. The barrier atoms within the deposited oxide helps minimize dopant atoms from passing through the oxide and entering the channel below the oxide.
摘要翻译：提供一种集成电路晶体管，其具有栅极氧化物和布置在半导体形貌上的栅极导体，栅极氧化物和栅极导体形成在公共室内。初始半导体形貌包括具有设置在其上表面内的隔离区的硅衬底。半导体形貌可以包括与衬底相对掺杂的限定区域或阱。首先将半导体形貌放置在公共室中。独立的腔室可操作地与公共腔室气体连通。在分离的室内产生等离子体，在其中产生氮，硅和含氧化合物，以形成被输送到公共室的离子，分子片段和被激发的分子。离子，分子片段和激发的分子反应并轰击半导体形貌的表面以在其上形成氧化物层。氧化物层与作为阻挡原子的氮原子结合。然后通过CVD在公共室内将多晶硅沉积在氧化物层上。在等离子体氧化物形成和多晶硅沉积步骤期间和之间，半导体形貌从未暴露于公共室外的环境条件。防止外界进入有助于最大限度地减少进入氧化物的污染。在多晶硅沉积期间，掺杂剂原子被转移并被夹带在多晶硅内。沉积的氧化物内的阻挡原子有助于最小化掺杂剂原子通过氧化物并进入氧化物下方的通道。

10. 发明授权

US6018179A Transistors having a scaled channel length and integrated spacers with enhanced silicidation properties 有权
标题翻译：具有缩放沟道长度的晶体管和具有增强的硅化特性的集成间隔物
公开(公告)号：US6018179A
公开(公告)日：2000-01-25
申请号：US187028
申请日：1998-11-05
申请人： Mark I. Gardner , Fred N. Hause , Derick J. Wristers
发明人： Mark I. Gardner , Fred N. Hause , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/311 , H01L21/321 , H01L21/336 , H01L29/423 , H01L29/51 , H01L27/088
CPC分类号： H01L21/28194 , H01L21/28114 , H01L21/28123 , H01L21/28202 , H01L21/31116 , H01L29/42376 , H01L29/513 , H01L29/518 , H01L29/66583 , H01L29/6659 , H01L21/3212 , Y10S257/90
摘要： A high speed MOS device has a scaled channel length and integrated spacers. The MOS device is formed on a substrate having active and isolation regions. In constructing the MOS device wells and Vt regions are formed as required. Then, a thin nitride layer is formed upon the substrate. Subsequently, an oxide layer is formed upon the nitride layer. Then, the oxide layer is pattern masked to expose gate regions. The gate regions are sloped etched to form slope etched voids. The slope etching may proceed to the nitride layer, through a portion of the nitride layer or fully through the nitride layer, depending upon the embodiment. In another embodiment, the nitride layer is not deposed and the oxide layer is either fully or partially slope etched to the silicon substrate. The patterned mask is then removed and remaining portions of the nitride layer may be converted to an oxynitride. Additionally, a gate oxide may be formed. The slope etched void is then filled with a gate conductor and the surface is planarized in a CMP process. The gate conductor then has a shape wherein its lower surface is smaller than its upper surface. Then, the substrate is isotropically etched to remove portions of the oxide layer and nitride layer unprotected by the gate conductor. The remaining structure includes integrally formed spacers. Active regions, LDD regions and punchthrough regions are then formed to complete formation of the transistor.
摘要翻译：高速MOS器件具有缩放的沟道长度和集成间隔物。 MOS器件形成在具有有源和隔离区域的衬底上。在构建MOS器件时，根据需要形成Vt区域。然后，在基板上形成薄的氮化物层。随后，在氮化物层上形成氧化物层。然后，将氧化层图案掩模以露出栅极区域。栅极区被倾斜蚀刻以形成斜坡蚀刻的空隙。根据实施例，倾斜蚀刻可以通过氮化物层的一部分或完全通过氮化物层而进行到氮化物层。在另一个实施例中，氮化物层不被沉积，并且氧化物层被完全或部分地倾斜蚀刻到硅衬底。然后去除图案化掩模，并且可以将氮化物层的剩余部分转化为氮氧化合物。另外，可以形成栅极氧化物。然后用栅极导体填充斜面蚀刻的空隙，并且在CMP工艺中平坦化表面。然后，栅极导体具有其下表面小于其上表面的形状。然后，各向同性蚀刻衬底，以除去未被栅极导体保护的氧化物层和氮化物层的部分。其余结构包括一体形成的间隔物。然后形成有源区，LDD区和穿透区，以完成晶体管的形成。

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