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1. 发明授权

US6090694A Local interconnect patterning and contact formation 失效
标题翻译：局部互连图案和接触形成
公开(公告)号：US6090694A
公开(公告)日：2000-07-18
申请号：US991742
申请日：1997-12-16
申请人： Fred N. Hause , Charles E. May , Mark I. Gardner
发明人： Fred N. Hause , Charles E. May , Mark I. Gardner
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76802 , H01L21/76832 , Y10S438/952
摘要： A method for forming a semiconductor device to produce a more distortion free via for interconnecting levels within a device or forming a connection between an external surface and an internal layer within a device includes the step of substituting a material similar to an etch stop adjacent one of the layers for the ARC. In other words, an etch stop is placed over the metal layer formed on a layer within the device. This is followed by a layer of silicon dioxide (SiO.sub.2) and then by a layer of material similar to the etch stop. Photoresist is placed on the layer of material similar to etch stop. The photoresist is exposed to light to form the location of the vias. The layer of material similar to etch stop, and the SiO.sub.2 layer are then removed in separate etching steps to form the via pathway from the resist to the etch stop adjacent the metal of the layer selected to be interconnected by the via. The resist can then be removed. This leaves the material similar to the etch stop located adjacent one surface of the SiO.sub.2 layer, and leaves the etch stop covering the metal in the via opening. One etch step can now be used to remove the etch stop covering the metal in the via opening and to remove the material similar to the etch stop located on the SiO.sub.2.
摘要翻译：用于形成半导体器件以产生用于在器件内互连电平或形成器件中的外表面和内部层之间的连接的无失真通孔的方法包括以下步骤：将与蚀刻停止相邻的材料 ARC的层。换句话说，蚀刻停止放置在形成在器件内的层上的金属层上。之后是二氧化硅层（SiO 2），然后是与蚀刻停止层相似的材料层。光刻胶放置在与蚀刻停止相似的材料层上。光致抗蚀剂暴露于光以形成通孔的位置。类似于蚀刻停止的材料层，然后在单独的蚀刻步骤中去除SiO 2层，以形成从抗蚀剂到蚀刻停止件的通孔路径，该蚀刻停止件邻近选定为由通孔相互连接的层的金属。然后可以除去抗蚀剂。这使得材料类似于位于SiO 2层的一个表面附近的蚀刻停止层，并且使蚀刻停止件覆盖通孔孔中的金属。现在可以使用一个蚀刻步骤去除覆盖通孔开口中的金属的蚀刻停止层，并且去除类似于位于SiO 2上的蚀刻停止层的材料。

2. 发明授权

US06323561B1 Spacer formation for precise salicide formation 失效
标题翻译：间歇形成精确的自杀化合物形成
公开(公告)号：US06323561B1
公开(公告)日：2001-11-27
申请号：US08987455
申请日：1997-12-09
申请人： Mark I. Gardner , Fred N. Hause , Charles E. May
发明人： Mark I. Gardner , Fred N. Hause , Charles E. May
IPC分类号： H01L27088
CPC分类号： H01L29/66598 , H01L21/266 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： The formation of a spacer for precise salicide formation is disclosed. In one embodiment, a method includes four steps. In the first step, at least one first spacer is formed, where each spacer is adjacent to an edge of a gate on a substrate and has a triangular geometry. In the second step, an ion implantation is applied to form a graded lightly doped region within the substrate underneath each spacer, the region corresponding to the triangular geometry of the spacer. In the third step, at least one second spacer is formed, where each second spacer overlaps a corresponding first spacer. In the fourth step, a metal silicide within the substrate is formed immediately adjacent to each second spacer.
摘要翻译：公开了形成用于精确的自对准硅化物形成的间隔物。在一个实施例中，一种方法包括四个步骤。在第一步骤中，形成至少一个第一间隔物，其中每个间隔物邻近衬底上的栅极的边缘并且具有三角形几何形状。在第二步骤中，施加离子注入以在每个间隔物下面的衬底内形成渐变的轻掺杂区域，该区域对应于间隔物的三角形几何形状。在第三步骤中，形成至少一个第二间隔物，其中每个第二间隔物与相应的第一间隔物重叠。在第四步骤中，衬底内的金属硅化物紧邻每个第二间隔物形成。

3. 发明授权

US6117739A Semiconductor device with layered doped regions and methods of manufacture 有权
标题翻译：具有分层掺杂区域的半导体器件和制造方法
公开(公告)号：US6117739A
公开(公告)日：2000-09-12
申请号：US166000
申请日：1998-10-02
申请人： Mark I. Gardner , Fred N. Hause , Charles E. May
发明人： Mark I. Gardner , Fred N. Hause , Charles E. May
IPC分类号： H01L21/266 , H01L21/336 , H01L29/10 , H01L29/49
CPC分类号： H01L29/66583 , H01L21/266 , H01L29/1083 , H01L29/4966 , H01L29/66537
摘要： A semiconductor device can be formed with active regions disposed in a substrate adjacent to a gate electrode and a doped region, of the same conductivity type as the active regions, embedded beneath the channel region defined by the active regions. In one embodiment, a patterned masking layer having at least one opening is formed over the substrate. A dopant material is implanted into the substrate using the masking layer to form active regions adjacent to the opening and an embedded doped region that is between and spaced apart from the active regions and is deeper in the substrate then the active regions. In addition or alternatively, spacer structures can be formed on the gate electrode by forming a conformal dielectric layer along a bottom surface and at least one sidewall of the opening and forming a gate electrode in the opening over the dielectric layer. The masking layer is then removed to leave the dielectric layer between the gate electrode and the substrate and as spacer structures on the sidewalls of the gate electrode.
摘要翻译：可以形成半导体器件，该有源区域设置在与由栅极电极相邻的衬底中的有源区域和与有源区域相同的导电类型的掺杂区域，嵌入在由有源区域限定的沟道区域的下面。在一个实施例中，在衬底上形成具有至少一个开口的图案化掩模层。使用掩模层将掺杂剂材料注入到衬底中以形成与开口相邻的有源区和位于有源区之间并且与有源区间隔开的嵌入的掺杂区，并且在衬底中更深的是有源区。另外或替代地，可以通过沿着底表面和开口的至少一个侧壁形成保形电介质层并在电介质层上的开口中形成栅电极，在栅电极上形成间隔结构。然后去除掩模层以在栅电极和衬底之间留下介电层，并且作为栅电极的侧壁上的间隔结构。

4. 发明授权

US5912493A Enhanced oxidation for spacer formation integrated with LDD implantation 失效
标题翻译：与LDD植入相结合的间隔物形成的增强氧化
公开(公告)号：US5912493A
公开(公告)日：1999-06-15
申请号：US970263
申请日：1997-11-14
申请人： Mark I. Gardner , Fred N. Hause , Charles E. May
发明人： Mark I. Gardner , Fred N. Hause , Charles E. May
IPC分类号： H01L21/336 , H01L29/08 , H01L29/10 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66575 , H01L29/0847 , H01L29/107
摘要： A method for forming a semiconductor device to produce graded doping in the source region and the drain region includes the steps of forming a gate on the surface of the substrate separated from the substrate by a gate oxide, and applying a first ion implantation to implant lightly doped source and drain regions into the substrate, and implanting a material to a portion of the gate oxide over the source region and a portion of the gate oxide over the drain region to vary the rate of oxide formation. An oxide layer is then formed. The resulting oxide layer has at least two thicknesses. Another ion implantation is applied through the formed oxide layer. The ion implantation converts a portion of the lightly doped source region into a heavily doped source region, and converts a portion of the lightly doped drain region into a heavily doped drain region. The implanted ions travel a set distance through the oxide layer formed and into the substrate and more specifically into the source and drain regions formed in the substrate. Therefore, the geometry of the interface between the lightly doped region and the heavily doped region in the source region and the drain region depends on the geometry (thickness and pattern) of oxide layer formed. A set of spacers can also be added after lightly doping the substrate to form the Ldd source and Ldd drain. The geometry of the spacers will also then effect the geometry of the interface between the lightly doped and heavily doped regions within the source and the drain. Also disclosed is a device made by this process as well as an information handling system including such a device.
摘要翻译：一种形成半导体器件以在源极区域和漏极区域中产生渐变掺杂的方法包括以下步骤：通过栅极氧化物在衬底的表面上形成栅极，并施加第一离子注入以轻微地注入掺杂的源极和漏极区域进入衬底，并且将材料注入源极区域上的栅极氧化物的一部分和在漏极区域上的栅极氧化物的一部分以改变氧化物形成速率。然后形成氧化物层。所得到的氧化物层具有至少两个厚度。通过形成的氧化物层施加另一离子注入。离子注入将轻掺杂源区的一部分转换为重掺杂源区，并将轻掺杂漏区的一部分转换为重掺杂漏极区。注入的离子通过形成的氧化物层进入设置的距离，并进一步具体地进入形成在衬底中的源区和漏区。因此，源极区域和漏极区域中的轻掺杂区域和重掺杂区域之间的界面的几何形状取决于形成的氧化物层的几何形状（厚度和图案）。在轻掺杂衬底以形成Ldd源和Ldd漏极之后，也可以添加一组间隔物。间隔物的几何形状还将影响源极和漏极之间的轻掺杂区域和重掺杂区域之间的界面的几何形状。还公开了通过该方法制造的装置以及包括这种装置的信息处理系统。

5. 发明授权

US6063679A Spacer formation for graded dopant profile having a triangular geometry 失效
标题翻译：具有三角形几何形状的分级掺杂剂分布的间隔物形成
公开(公告)号：US6063679A
公开(公告)日：2000-05-16
申请号：US987558
申请日：1997-12-09
申请人： Mark I. Gardner , Fred N. Hause , Charles E. May
发明人： Mark I. Gardner , Fred N. Hause , Charles E. May
IPC分类号： H01L21/266 , H01L21/336
CPC分类号： H01L29/66598 , H01L21/266 , H01L29/6659
摘要： The formation of a spacer for a graded dopant profile having a triangular geometry is disclosed. In one embodiment, a method has three steps. In the first step, a gate is formed on a substrate, the gate having two edges. In the second step, at least one spacer is formed, where each spacer is adjacent to an edge of the gate and has a triangular geometry. In the third step, an ion implantation is applied to form a graded lightly doped region within the substrate underneath each spacer, the region corresponding to the triangular geometry of the spacer.
摘要翻译：公开了用于具有三角形几何形状的渐变掺杂剂分布的间隔物的形成。在一个实施例中，方法具有三个步骤。在第一步骤中，栅极形成在衬底上，栅极具有两个边缘。在第二步骤中，形成至少一个间隔件，其中每个间隔件邻近门的边缘并具有三角形几何形状。在第三步骤中，施加离子注入以在每个间隔物下面的衬底内形成渐变的轻掺杂区域，该区域对应于间隔物的三角形几何形状。

6. 发明授权

US06046089A Selectively sized spacers 失效
标题翻译：选择尺寸的垫片
公开(公告)号：US06046089A
公开(公告)日：2000-04-04
申请号：US2727
申请日：1998-01-05
申请人： Mark I. Gardner , Fred N. Hause , Charles E. May
发明人： Mark I. Gardner , Fred N. Hause , Charles E. May
IPC分类号： H01L21/311 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/31116
摘要： The formation of selectively sized spacers is disclosed. One embodiment comprises a method including four steps. In the first step, at least one spacer for each of a plurality of gates is formed on a substrate, the plurality of gates including a first gate and at least one remaining gate, and each spacer adjacent to an edge of its corresponding gate. In the second step, a mask is applied to the first gate, including the spacers for the first gate. In the third step, the spacers for the remaining gates are etched. In the fourth step, the mask applied to the first gate, including the spacers for the first gate, is removed.
摘要翻译：公开了选择性尺寸的间隔物的形成。一个实施例包括一个包括四个步骤的方法。在第一步骤中，在衬底上形成用于多个栅极中的每一个的至少一个间隔物，所述多个栅极包括第一栅极和至少一个剩余栅极，并且每个间隔物邻近其对应栅极的边缘。在第二步骤中，将掩模施加到第一栅极，包括用于第一栅极的间隔物。在第三步骤中，蚀刻用于剩余栅极的间隔物。在第四步骤中，去除了包括用于第一栅极的间隔物的第一栅极的掩模。

7. 发明授权

US5981357A Semiconductor trench isolation with improved planarization methodology 失效
标题翻译：具有改进的平面化方法的半导体沟槽隔离
公开(公告)号：US5981357A
公开(公告)日：1999-11-09
申请号：US877000
申请日：1997-06-16
申请人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
发明人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
IPC分类号： H01L21/76 , H01L21/3105 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/31053 , Y10S148/05
摘要： An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches. The patterned stacked layers incorporate a polysilicon and/or oxide buffer which prevents deleterious migration of nitrogen from the overlying nitride layer to the underlying silicon mesa upper surface.
摘要翻译：提供隔离技术用于改善填充隔离区相对于相邻硅台面的整体平面度。隔离过程产生具有增强的机械和电性能的硅台面。通过重复填充隔离沟槽，图案化大面积隔离沟槽和重新填充隔离沟槽以呈现具有可以通过化学机械抛光容易去除的凹痕的上表面的步骤来执行平面度。通过利用堆叠在硅衬底上的独特的一组层来增强硅台面上表面，然后对衬底进行图案化以形成其上具有堆叠层的凸起的硅表面或台面。图案化的堆叠层包括不同组合物的独特组合，当被去除时，其离开相邻填充沟槽下方的硅台面上表面。图案化的堆叠层包含多晶硅和/或氧化物缓冲液，其可防止氮从上覆的氮化物层到底层的硅台面上表面的有害迁移。

8. 发明授权

US6051863A Transistor gate conductor having sidewall surfaces upon which a spacer having a profile that substantially prevents silicide bridging is formed 失效
标题翻译：具有侧壁表面的晶体管栅极导体形成具有基本上防止硅化物桥接的轮廓的间隔件
公开(公告)号：US6051863A
公开(公告)日：2000-04-18
申请号：US975582
申请日：1997-11-21
申请人： Fred N. Hause , Mark I. Gardner , Charles E. May
发明人： Fred N. Hause , Mark I. Gardner , Charles E. May
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/6659 , H01L29/665
摘要： A method is provided for fabricating a transistor gate conductor having opposed sidewall surfaces upon which dielectric spacers are formed such that the spacer profile substantially tapers toward the adjacent gate conductor sidewall surface as it approaches the base of the gate conductor. More particularly, formation of the sidewall spacers involves anisotropically etching a dielectric material deposited across a semiconductor topography in the presence of a passivant source to form a passivant upon portions of the dielectric material. The passivant primarily accumulates upon the upper portion of lateral surfaces of the dielectric material. An isotropic etch which occurs at the same rate in all directions is used to etch portions of the dielectric material not completely covered by the passivant. The resulting spacers have a varying thickness which decreases from top to bottom. Thus, when a silicide-forming metal is deposited, the metal accumulates at the peak of each spacer and is inhibited from being deposited upon the lower portions of the spacers, thereby preventing silicide bridging between the gate conductor and ensuing source/drain regions of the transistor.
摘要翻译：提供了一种用于制造具有相对侧壁表面的晶体管栅极导体的方法，在该侧壁表面上形成有电介质间隔物，使得当栅极导体侧壁表面接近栅极导体的基极时，间隔物轮廓基本上逐渐朝着相邻的栅极导体侧壁表面逐渐变细。更具体地说，侧壁间隔物的形成涉及各向异性蚀刻在钝化源的存在下横跨半导体形貌沉积的电介质材料，以在介电材料的一部分上形成钝化剂。钝化剂主要积聚在电介质材料的侧表面的上部。使用在所有方向上以相同速率发生的各向同性蚀刻来蚀刻未被钝化剂完全覆盖的介电材料的部分。所得的间隔物具有从顶部到底部减小的变化的厚度。因此，当沉积硅化物形成金属时，金属在每个间隔物的峰处积聚，并且被抑制沉积在间隔物的下部，从而防止栅极导体与随后的源极/漏极区之间的硅化物桥接晶体管。

9. 发明授权

US5904539A Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties 失效
标题翻译：半导体沟槽隔离工艺导致硅台面具有增强的机械和电学性能
公开(公告)号：US5904539A
公开(公告)日：1999-05-18
申请号：US619004
申请日：1996-03-21
申请人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
发明人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229 , Y10S148/05
摘要： An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches. The patterned stacked layers incorporate a polysilicon and/or oxide buffer which prevents deleterious migration of nitrogen from the overlying nitride layer to the underlying silicon mesa upper surface.
摘要翻译：提供隔离技术用于改善填充隔离区相对于相邻硅台面的整体平面度。隔离过程产生具有增强的机械和电性能的硅台面。通过重复填充隔离沟槽，图案化大面积隔离沟槽和重新填充隔离沟槽以呈现具有可以通过化学机械抛光容易去除的凹痕的上表面的步骤来执行平面度。通过利用堆叠在硅衬底上的独特的一组层来增强硅台面上表面，然后对衬底进行图案化以形成其上具有堆叠层的凸起的硅表面或台面。图案化的堆叠层包括不同组合物的独特组合，当被去除时，其离开相邻填充沟槽下方的硅台面上表面。图案化的堆叠层包含多晶硅和/或氧化物缓冲液，其可防止氮从上覆的氮化物层到底层的硅台面上表面的有害迁移。

10. 发明授权

US6156649A Method of forming uniform sheet resistivity salicide 失效
标题翻译：形成均匀的电阻率自对准硅胶的方法
公开(公告)号：US6156649A
公开(公告)日：2000-12-05
申请号：US60434
申请日：1998-04-14
申请人： Fred N. Hause , Robert Dawson , Charles E. May
发明人： Fred N. Hause , Robert Dawson , Charles E. May
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/665
摘要： A semiconductor process in which a first silicide is formed on silicon upper surfaces upon which a second silicide is selectively deposited. A refractory metal is blanket deposited on a semiconductor substrate. The semiconductor substrate is then heated to a first temperature to react portions of the refractory metal above the exposed silicon surfaces to form a first phase of a first silicide. The unreacted portions of the refractory metal then remove, typically with a wet etch process. The semiconductor substrate is then heated to a second temperature to form a second phase of the first silicide. The second temperature is typically greater than the first, and the resistivity of the second phase is less than a resistivity of the first phase. Thereafter, a second metal silicide is selectively deposited on the first silicide, preferably through the use of a chemical vapor deposition process. In one embodiment, the selectively deposited second silicide is reacted with the existing first silicide to form a composite silicide structure exhibiting uniform sheet resistivity independent of the dimensions of the underlying silicon structure.
摘要翻译：一种半导体工艺，其中第一硅化物形成在硅上表面上，在其上选择性地沉积第二硅化物。难熔金属被覆盖在半导体衬底上。然后将半导体衬底加热至第一温度，以使暴露的硅表面上方的难熔金属的部分反应，以形成第一硅化物的第一相。难熔金属的未反应部分通常用湿蚀刻工艺除去。然后将半导体衬底加热至第二温度以形成第一硅化物的第二相。第二温度通常大于第一温度，第二相的电阻率小于第一相的电阻率。此后，优选通过使用化学气相沉积工艺，在第一硅化物上选择性地沉积第二金属硅化物。在一个实施例中，选择性沉积的第二硅化物与现有的第一硅化物反应以形成独立于下面的硅结构的尺寸的均匀的薄层电阻的复合硅化物结构。

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