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1. 发明申请

US20050199912A1 Semiconductor memory with vertical memory transistors in a cell array arrangement with 1-2F2 cells 失效
标题翻译：具有垂直存储晶体管的半导体存储器，其具有1-2F2个单元阵列
公开(公告)号：US20050199912A1
公开(公告)日：2005-09-15
申请号：US11073214
申请日：2005-03-05
申请人： Franz Hofmann , Erhard Landgraf , Richard Luyken , Thomas Schulz , Michael Specht
发明人： Franz Hofmann , Erhard Landgraf , Richard Luyken , Thomas Schulz , Michael Specht
IPC分类号： H01L21/20 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L27/10 , H01L27/115 , H01L29/73 , H01L29/76 , H01L29/792
CPC分类号： H01L29/7926 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： The invention relates to a semiconductor memory having a multiplicity of memory cells, each of the memory cells having N (e.g., four) vertical memory transistors with trapping layers. Higher contact regions are formed in higher semiconductor regions extending obliquely with respect to the rows and columns of the cell array, the gate electrode generally being led to the step side areas of the higher semiconductor region. A storage density of 1-2F2 per bit can thus be achieved.
摘要翻译：本发明涉及一种具有多个存储单元的半导体存储器，每个存储器单元具有N（例如四个）垂直存储晶体管，具有捕获层。在相对于单元阵列的行和列倾斜地延伸的较高半导体区域中形成更高的接触区域，栅电极通常被引导到较高半导体区域的台阶侧区域。因此可以实现每位1-2F 2的存储密度。

2. 发明申请

US20050224888A1 Integrated circuit array 审中-公开
标题翻译：集成电路阵列
公开(公告)号：US20050224888A1
公开(公告)日：2005-10-13
申请号：US11116139
申请日：2005-04-27
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
IPC分类号： G11C13/02 , H01L29/78 , H01L51/00 , H01L51/30 , H01L29/76
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/17 , H01L27/283 , H01L51/0048 , H01L51/0052 , H01L51/0512
摘要： Integrated circuit array having field effect transistors (FETs) formed next to and/or above one another. The array has a substrate, a planarized first wiring plane with interconnects and first source/drain regions of the FETs, a planarized first insulator layer on the first wiring plane, a planarized gate region layer, which has patterned gate regions made of electrically conductive material and insulator material introduced therebetween, on the first insulated layer, a planarized second insulator layer on the gate region layer, holes formed through the second insulator layer, the gate regions, and the first insulator layer, a vertical nanoelement serving as a channel region in each of the holes, a second wiring plane with interconnects and second source/drain regions of the FETs, each nanoelement being arranged between the first and second wiring planes, and a gate insulating layer between the respective vertical nanoelement and the electrically conductive material of the gate regions.
摘要翻译：集成电路阵列具有形成在彼此之上和/或彼此之上的场效应晶体管（FET）。阵列具有衬底，具有互连的平坦化的第一布线面和FET的第一源极/漏极区，在第一布线平面上的平坦化的第一绝缘体层，平坦化的栅极区域层，其具有由导电材料制成的图案化栅极区域和介于其间的绝缘体材料，在所述第一绝缘层上，在所述栅极区域层上的平坦化的第二绝缘体层，穿过所述第二绝缘体层，所述栅极区域和所述第一绝缘体层形成的空穴，用作所述沟道区域中的沟道区域的垂直纳米元件每个孔，具有互连的第二布线面和FET的第二源极/漏极区，每个纳米元件布置在第一和第二布线平面之间，并且在相应的垂直纳米元件和导电材料之间的栅极绝缘层门区域。

3. 发明申请

US20050199942A1 Semiconductor memory with vertical memory transistors and method for fabricating it 有权
标题翻译：具有垂直存储晶体管的半导体存储器及其制造方法
公开(公告)号：US20050199942A1
公开(公告)日：2005-09-15
申请号：US11073205
申请日：2005-03-05
申请人： Franz Hofmann , Erhard Landgraf , Richard Luyken , Thomas Schulz , Michael Specht
发明人： Franz Hofmann , Erhard Landgraf , Richard Luyken , Thomas Schulz , Michael Specht
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/792
CPC分类号： H01L21/28282 , H01L29/66833 , H01L29/792 , H01L29/7923 , H01L29/7926
摘要： The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory generally includes a semiconductor layer arranged on a substrate surface that includes a normally positioned step between a deeper region and a higher region. The semiconductor memory further includes doped contact regions, channel regions, a trapping layer arranged on a gate oxide layer, and at least one gate electrode. The method for forming the memory cells includes patterning a semiconductor layer to form a deeper semiconductor region and a higher semiconductor region having a step positioned between the regions. The method further includes forming a first oxide layer and a trapping layer, and then removing portions of the trapping layer and the first oxide layer and applying a second oxide layer at least regions of a doped region, the trapping layer, and the step area, and applying a gate electrode to the second oxide layer and doping, at least in regions, of the deeper semiconductor region and the higher semiconductor region to form a deeper contact region and a higher contact region.
摘要翻译：本发明涉及具有多个存储单元的半导体存储器和用于形成存储单元的方法。半导体存储器通常包括布置在衬底表面上的半导体层，其包括较深区域和较高区域之间的正常定位的台阶。半导体存储器还包括掺杂接触区域，沟道区域，布置在栅极氧化物层上的俘获层和至少一个栅电极。形成存储单元的方法包括图案化半导体层以形成较深的半导体区域和具有位于该区域之间的台阶的较高半导体区域。该方法还包括形成第一氧化物层和俘获层，然后去除俘获层和第一氧化物层的部分，并且至少在掺杂区域，俘获层和台阶区域的区域上施加第二氧化物层，以及向所述第二氧化物层施加栅电极，并且至少在所述较深半导体区域和所述较高半导体区域的区域中掺杂以形成更深的接触区域和更高的接触区域。

4. 发明申请

US20060175666A1 Integrated circuit arrangement with low-resistance contacts and method for production thereof 有权
公开(公告)号：US20060175666A1
公开(公告)日：2006-08-10
申请号：US11324803
申请日：2006-01-03
申请人： Franz Hofmann , Richard Luyken , Wolfgang Roesner , Michael Specht
发明人： Franz Hofmann , Richard Luyken , Wolfgang Roesner , Michael Specht
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/41783 , H01L21/28518 , H01L29/41725 , H01L29/665 , H01L29/78 , Y10S438/964
摘要： An integrated circuit arrangement and fabrication method is presented. The integrated circuit arrangement contains a semiconductor and a metal electrode. The contact area between a semiconductor and the electrode is increased without increasing the lateral dimensions using partial regions of the semiconductor and/or of the electrode that extend through a transition layer between the semiconductor and electrode.

5. 发明授权

US07692246B2 Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement 有权
标题翻译： FinFET晶体管布置的制造方法和相应的FinFET晶体管布置
公开(公告)号：US07692246B2
公开(公告)日：2010-04-06
申请号：US11649470
申请日：2007-01-04
申请人： Lars Dreeskornfeld , Franz Hofmann , Johannes Richard Luyken , Michael Specht
发明人： Lars Dreeskornfeld , Franz Hofmann , Johannes Richard Luyken , Michael Specht
IPC分类号： H01L27/01
CPC分类号： H01L21/823412 , H01L21/823437 , H01L29/66818 , H01L29/7851
摘要： The present invention provides a FinFET transistor arrangement produced using a method with the steps: providing a substrate (106, 108); forming an active region (1) on the substrate a fin-like channel region (113b′; 113b″). Formation of the fin-like channel region (113b′; 113b″) has the following steps: forming a hard mask (S1-S4) on the active region (1); anisotropic etching of the active region (1) using the hard mask (S1-S4) forming STI trenches (G1-G5) having an STI oxide filling (9); polishing-back of the STI oxide filling (9); etching-back of the polished-back STI oxide filling (9); selective removal of components of the hard mask forming a modified hard mask (S1′-S4′); anisotropic etching of the active region (1) using the modified hard mask (S1′-S4′) forming widened STI trenches (G1′-G5′), the fin-like channel regions (113b′; 113b″) of the active region (1) remaining for each individual FinFET transistor.
摘要翻译：本发明提供一种使用以下步骤制造的FinFET晶体管布置：步骤：提供衬底（106,108）; 在所述衬底上形成鳍状沟道区（113b'; 113b“）上的有源区（1）。翅片状通道区域（113b'; 113b“）的形成步骤如下：在有源区域（1）上形成硬掩模（S1-S4）; 使用形成具有STI氧化物填充物（9）的STI沟槽（G1-G5）的硬掩模（S1-S4）对有源区域（1）进行各向异性蚀刻。 STI氧化物填充物（9）的抛光; 抛光后的STI氧化物填充物（9）的回蚀; 选择性地去除形成修改的硬掩模（S1'-S4'）的硬掩模的部件; 使用形成加宽的STI沟槽（G1'-G5'）的修改的硬掩模（S1'-S4'）对有源区（1）进行各向异性蚀刻，有源区的鳍状沟道区（113b'; 113b“）（1）保留每个单独的FinFET晶体管。

6. 发明申请

US20060267082A1 Semiconductor memory component 失效
标题翻译：半导体存储器组件
公开(公告)号：US20060267082A1
公开(公告)日：2006-11-30
申请号：US11438883
申请日：2006-05-23
申请人： Franz Hofmann , Richard Luyken , Wolfgang Roesner , Michael Specht , Martin Staedele
发明人： Franz Hofmann , Richard Luyken , Wolfgang Roesner , Michael Specht , Martin Staedele
IPC分类号： H01L29/76
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/1203
摘要： A semiconductor memory component comprises at least one memory cell. The memory cell comprises a semiconductor body comprised of a body region, a drain region and a source region, a gate dielectric, and a gate electrode. The body region comprises a first conductivity type and a depression between the source and drain regions, and the source and drain regions comprise a second conductivity type. The gate electrode is arranged at least partly in the depression and is insulated from the body, source, and drain regions by the gate dielectric. The body region further comprises a first continuous region with a first dopant concentration and a second continuous region with a second dopant concentration greater than the first dopant concentration. The first continuous region adjoins the drain region, the depression and the source region, and the second region is arranged below the first region and adjoins the first region.
摘要翻译：半导体存储器组件包括至少一个存储单元。存储单元包括由体区，漏区和源区组成的半导体本体，栅电介质和栅电极。主体区域包括第一导电类型和源极和漏极区域之间的凹陷，并且源极和漏极区域包括第二导电类型。栅电极至少部分地布置在凹陷中，并且通过栅极电介质与主体，源极和漏极区绝缘。体区还包括具有第一掺杂剂浓度的第一连续区域和具有大于第一掺杂剂浓度的第二掺杂剂浓度的第二连续区域。第一连续区域邻接漏极区域，凹陷部分和源极区域，并且第二区域布置在第一区域下方并与第一区域相邻。

7. 发明申请

US20050276093A1 Memory cell, memory cell arrangement, patterning arrangement, and method for fabricating a memory cell 审中-公开
标题翻译：存储单元，存储单元布置，图案化布置以及用于制造存储单元的方法
公开(公告)号：US20050276093A1
公开(公告)日：2005-12-15
申请号：US11119531
申请日：2005-04-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
IPC分类号： G11C13/02 , H01L21/8242 , H01L27/108 , H01L51/00 , H01L51/05 , H01L51/30 , G11C11/24
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0033 , G11C2213/16 , H01L27/10841 , H01L27/10864 , H01L27/10876 , H01L27/283 , H01L51/0048 , H01L51/0052 , H01L51/0512 , H01L51/057
摘要： A memory cell having a storage capacitor and a vertical switching transistorm, which has a semiconducting nanostructure which has grown on at least part of the storage capacitor and includes a semiconducting nanotube, a bundle of semiconducting nanotubes, or a semiconducting nanorod.
摘要翻译：具有存储电容器和垂直开关转置管的存储单元，其具有在至少部分存储电容器上生长的半导体纳米结构，并且包括半导体纳米管，半导体纳米管束或半导体纳米棒。

8. 发明申请

US20050186738A1 High-density NROM-FINFET 失效
标题翻译：高密度NROM-FINFET
公开(公告)号：US20050186738A1
公开(公告)日：2005-08-25
申请号：US11073017
申请日：2005-03-04
申请人： Franz Hofmann , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Michael Specht
发明人： Franz Hofmann , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Michael Specht
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L21/84 , H01L27/115 , H01L27/12 , H01L29/786 , H01L29/788 , H01L29/792 , H01R11/22 , H01R13/62
CPC分类号： H01L21/28273 , G11C16/0466 , H01L21/28282 , H01L21/845 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792 , Y10S257/903 , Y10S257/904 , Y10S257/905
摘要： Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence in the longitudinal direction of the rib. The rib has an essentially rectangular shape with an upper side of the rib and rib side faces lying opposite. A memory layer is configured for programming the memory cell, arranged on the upper side of the rib spaced apart by a first insulator layer, and projects in the normal direction of the one rib side face over one of the rib side faces so that the one rib side face and the upper side of the rib form an edge for injecting charge carriers from the channel region into the memory layer. A gate electrode is spaced apart from the one rib side face by a second insulator layer and from the memory layer by a third insulator layer, electrically insulated from the channel region, and configured to control its electrical conductivity.
摘要翻译：具有存储单元的半导体存储器，每个存储单元包括第一和第二导电掺杂的接触区域和布置在其间的沟道区域，所述沟道区域形成在由半导体材料制成的网状肋状物中，肋骨肋具有基本上矩形的形状，肋的上侧和肋侧面相对。存储层被配置为对存储单元进行编程，布置在由第一绝缘体层间隔开的肋的上侧，并且沿着一个肋侧面的一个肋侧面的法线方向突出，使得一个肋侧面和肋的上侧形成用于将电荷载流子从沟道区域注入到存储层中的边缘。栅电极通过第二绝缘体层与一个肋侧面间隔开，并且通过与沟道区电绝缘并且被配置为控制其导电性的第三绝缘体层与存储层隔开。

9. 发明申请

US20050157583A1 Method for the production of a memory cell, memory cell and memory cell arrangement 有权
标题翻译：用于生产存储器单元，存储单元和存储单元布置的方法
公开(公告)号：US20050157583A1
公开(公告)日：2005-07-21
申请号：US10999810
申请日：2004-11-29
申请人： Franz Hofmann , Richard Luyken , Michael Specht
发明人： Franz Hofmann , Richard Luyken , Michael Specht
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L21/84 , H01L27/115 , H01L27/12 , H01L29/788 , G11C8/02
CPC分类号： H01L21/28273 , G11C16/0416 , G11C16/0483 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/1203 , H01L29/66825 , H01L29/7881 , H01L29/7883
摘要： Memory cell having an auxiliary substrate, on which a first gate insulating layer is formed, a floating gate formed on the first gate insulating layer, an electrically insulating layer formed on the floating gate, a memory gate electrode formed on the electrically insulating layer, a substrate fixed to the memory gate electrode, a second gate insulating layer formed on a part of a surface of the auxiliary substrate, which surface is uncovered by partially removing the auxiliary substrate, a read gate electrode formed on the second gate insulating layer, and two source/drain regions located between a channel region essentially in and/or on a surface region of the remaining material of the auxiliary substrate that is free of the second gate insulating layer and the read gate electrode, the channel region being arranged in each case at least partly laterally overlapping the floating gate and the read gate electrode.
摘要翻译：具有辅助基板的存储单元，其上形成有第一栅极绝缘层，形成在第一栅极绝缘层上的浮动栅极，形成在浮动栅极上的电绝缘层，形成在电绝缘层上的存储栅电极，基板固定到存储栅电极，第二栅极绝缘层，形成在辅助基板的表面的一部分上，该表面通过部分去除辅助基板而被覆盖，形成在第二栅极绝缘层上的读取栅电极和两个源极/漏极区域位于基本上在辅助衬底的剩余材料的表面区域和/或栅极绝缘层之间的沟道区域之间，沟道区域分别布置在至少部分地侧向地重叠浮置栅极和读取栅电极。

10. 发明授权

US07709827B2 Vertically integrated field-effect transistor having a nanostructure therein 失效
标题翻译：其中具有纳米结构的垂直集成的场效应晶体管
公开(公告)号：US07709827B2
公开(公告)日：2010-05-04
申请号：US10533550
申请日：2003-10-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Johannes Richard Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Johannes Richard Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
IPC分类号： H01L21/8238
CPC分类号： H01L29/78642 , B82Y10/00 , H01L27/283 , H01L29/0673 , H01L29/0676 , H01L29/66439 , H01L29/66742 , H01L29/66787 , H01L29/775 , H01L51/0048 , H01L51/0052 , H01L51/0512
摘要： The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.
摘要翻译：本发明涉及垂直集成部件，部件布置和用于生产垂直集成部件的方法。垂直集成部件具有第一导电层，中间层，其部分地由第一导电层上的介电材料实现，中间层上的第二导电层和集成在中间层中的贯通保持件中的纳米结构。纳米结构的第一端部分耦合到第一导电层，第二端部分耦合到第二导电层。中间层包括在两个相邻的介电部分层之间的第三导电层，其厚度小于介电部分层中的至少一个的厚度。

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