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1. 发明授权

US5870404A Self-timed circuit having critical path timing detection 失效
标题翻译：具有关键路径定时检测的自定时电路
公开(公告)号：US5870404A
公开(公告)日：1999-02-09
申请号：US694120
申请日：1996-08-08
申请人： Frank D. Ferraiolo , John E. Gersbach , Charles J. Masenas, Jr. , Norman J. Rohrer , Bruce W. Singer
发明人： Frank D. Ferraiolo , John E. Gersbach , Charles J. Masenas, Jr. , Norman J. Rohrer , Bruce W. Singer
IPC分类号： G06F1/08 , G06K5/04 , G11B5/00
CPC分类号： G06F1/08
摘要： A self-timed circuit for use a clocked logic system is disclosed that comprises a timing detection device for detecting a timing margin of a critical path, the critical path being a path that limits the speed of the system. The circuit further comprises increase logic for increasing the speed of the system clock if the timing margin allows it, and decrease logic for decreasing the speed of the system clock if the timing margin indicates such a need. The increase and decrease logic comprise threshold generator and reset logic, and clock control logic.
摘要翻译：公开了一种用于使用时钟逻辑系统的自定时电路，其包括用于检测关键路径的定时裕度的定时检测装置，该关键路径是限制系统速度的路径。该电路还包括用于增加系统时钟的速度的增加逻辑，如果定时裕度允许的话，并且如果定时裕度表示这样的需要，则降低用于降低系统时钟速度的逻辑。增加和减少逻辑包括阈值发生器和复位逻辑以及时钟控制逻辑。

2. 发明授权

US5694087A Anti-latching mechanism for phase lock loops 失效
标题翻译：锁相环锁止机构
公开(公告)号：US5694087A
公开(公告)日：1997-12-02
申请号：US592902
申请日：1996-01-29
申请人： Frank D. Ferraiolo , John E. Gersbach , Masayuki Hayashi , Ilya I. Novof , Charles J. Masenas, Jr.
发明人： Frank D. Ferraiolo , John E. Gersbach , Masayuki Hayashi , Ilya I. Novof , Charles J. Masenas, Jr.
IPC分类号： H03L7/10 , H03L7/093
CPC分类号： H03L7/10
摘要： A protective circuit for a phase lock loop ensures that the VCO does not initiate a runaway condition when outputting a signal having a frequency higher than the feedback divider can respond to. During normal phase lock operation, a counter keeps track of the PLL input signal and is reset by the feedback divider. In the runaway condition the counter is not reset and triggers a control signal to the VCO. A second counter can be used to keep track of the feedback divider output and to reset the first counter. When the first counter far outruns the second counter the control signal is triggered.
摘要翻译：用于锁相环的保护电路确保当输出具有高于反馈分配器的频率的信号可以响应时，VCO不会发起失控状况。在正常锁相操作期间，计数器跟踪PLL输入信号，并由反馈分频器复位。在失控状态下，计数器不复位，并触发VCO的控制信号。第二个计数器可用于跟踪反馈分频器输出并复位第一个计数器。当第一个计数器远远超出第二个计数器时，触发控制信号。

3. 发明授权

US5694032A Band gap current reference circuit 失效
标题翻译：带隙电流参考电路
公开(公告)号：US5694032A
公开(公告)日：1997-12-02
申请号：US619447
申请日：1996-03-19
申请人： John E. Gersbach , Charles J. Masenas, Jr.
发明人： John E. Gersbach , Charles J. Masenas, Jr.
IPC分类号： G05F3/26
CPC分类号： G05F3/262
摘要： A circuit for delivering an accurate reference current independent of operating frequency that is implementable on-chip and that is relatively insensitive to process and temperature variations. A frequency source controls a rate of charge transfer via a switched capacitor to generate a constant current over different frequencies. A complimentary doped FET provides a band gap voltage imposed over a known resistance to generate the output current.
摘要翻译：用于传递独立于片上可实现且对于过程和温度变化相对不敏感的工作频率的精确参考电流的电路。频率源通过开关电容器控制电荷转移速率，以在不同频率上产生恒定电流。补充掺杂的FET提供施加在已知电阻上的带隙电压以产生输出电流。

4. 发明授权

US5534790A Current transition rate control circuit 失效
标题翻译：电流转换速率控制电路
公开(公告)号：US5534790A
公开(公告)日：1996-07-09
申请号：US227162
申请日：1994-04-13
申请人： Bachvan Huynh , Charles J. Masenas, Jr.
发明人： Bachvan Huynh , Charles J. Masenas, Jr.
IPC分类号： H03K17/16
CPC分类号： H03K17/163
摘要： A current transition rate control circuit is provided, comprising first and second data inputs; first and second charge/discharge circuits for receiving the first and second data inputs; a first reference voltage circuit for sending a first control signal and a second reference voltage circuit for sending a second control signal to, respectively, the first and second charge/discharge circuits; and first and second output transistors coupled, respectively, to the outputs of the first and second charge/discharge circuits. The circuit controls the switching speed of the output transistors to minimize current spikes on the output. The circuit may include a pre-driver circuit for (i) receiving a single data input and outputting the first and second data inputs, and (ii) receiving a circuit disabling signal and placing the circuit in a high impedance state which turns off both of the output transistors. A test circuit is also provided for deactivating the first and second data inputs and for shutting off current flow in the first and second reference voltage circuits so that leakage current in the circuit may be measured.
摘要翻译：提供了一种电流转换速率控制电路，包括第一和第二数据输入; 用于接收第一和第二数据输入的第一和第二充电/放电电路; 用于发送第一控制信号的第一参考电压电路和用于分别向第一和第二充电/放电电路发送第二控制信号的第二参考电压电路; 以及分别耦合到第一和第二充电/放电电路的输出的第一和第二输出晶体管。电路控制输出晶体管的开关速度，以最小化输出端的电流尖峰。电路可以包括用于（i）接收单个数据输入并输出第一和第二数据输入的预驱动器电路，以及（ii）接收电路禁用信号并将电路置于高阻抗状态，输出晶体管。还提供测试电路用于停用第一和第二数据输入并关闭第一和第二参考电压电路中的电流，从而可以测量电路中的漏电流。

5. 发明授权

US4555776A Voltage balancing circuit for memory systems 失效
标题翻译：用于存储器系统的电压平衡电路
公开(公告)号：US4555776A
公开(公告)日：1985-11-26
申请号：US369970
申请日：1982-04-19
申请人： Charles J. Masenas, Jr.
发明人： Charles J. Masenas, Jr.
IPC分类号： H03K19/018 , G11C11/414 , G11C11/416 , G11C7/00
CPC分类号： G11C11/416
摘要： A voltage balancing circuit, particularly suitable for bipolar memory arrays producing small signals, is provided which includes first and second conductive lines, a point of reference potential, a first device disposed between the first conductive line and the point of reference potential, a second device disposed between the second conductive line and the point of reference potential, first and second transistors, first means for coupling the first line through the first transistor to the second line, second means for coupling the second line through the second transistor to the first line, and means for supplying substantially equal signals to the control electrodes of the first and second transistors. When used in a memory array, the conductive lines are the bit/sense lines, the point of reference potential is a bit/sense line reference voltage and the equal signals for the control electrodes of the transistors are provided in response to a signal from a bit decoder.
摘要翻译：提供了特别适用于产生小信号的双极性存储器阵列的电压平衡电路，其包括第一和第二导线，参考点电位，设置在第一导线与参考电位之间的第一器件，第二器件设置在第二导线和参考点之间的第一和第二晶体管，用于将第一线通过第一晶体管耦合到第二线的第一装置，用于将第二线通过第二晶体管耦合到第一线的第二装置，以及用于向第一和第二晶体管的控制电极提供基本相等的信号的装置。当在存储器阵列中使用时，导线是位/检测线，参考点电位是位/检测线参考电压，并且响应于来自于...的信号提供晶体管的控制电极的相等信号位解码器。

6. 发明授权

US4404662A Method and circuit for accessing an integrated semiconductor memory 失效
标题翻译：用于访问集成半导体存储器的方法和电路
公开(公告)号：US4404662A
公开(公告)日：1983-09-13
申请号：US280396
申请日：1981-07-06
申请人： Charles J. Masenas, Jr.
发明人： Charles J. Masenas, Jr.
IPC分类号： G11C11/414 , G11C11/416 , G11C11/40
CPC分类号： G11C11/416
摘要： A memory system is provided having an array of cells, each of which may include first and second cross-coupled inverting NPN transistors and first and second PNP transistors for injecting charge into the first and second inverting transistors. A first bit/sense line of a bit/sense line pair is connected to the emitter of the first inverting transistor and a second bit/sense line of the pair is connected to the emitter of the second inverting transistor and a common word line is connected to the emitters of the first and second charge injecting transistors. To read a selected cell, all cells of the array are discharged through the word lines, the pair of bit/sense lines connected to the selected cell are electrically floated or isolated and the word line connected to the selected cell is energized by a word driver. The signal developed in the bit/sense lines connected to the selected cell is detected while the word line connected to the selected cell is being energized by the word driver.
摘要翻译：提供了具有单元阵列的存储器系统，每个单元可以包括第一和第二交叉耦合反相NPN晶体管，以及用于将电荷注入第一和第二反相晶体管的第一和第二PNP晶体管。位/检测线对的第一位/检测线连接到第一反相晶体管的发射极，并且该对的第二位/感测线连接到第二反相晶体管的发射极，并且连接公共字线到第一和第二电荷注入晶体管的发射极。为了读取所选择的单元，阵列的所有单元通过字线放电，连接到所选单元的一对位/检测线被浮置或隔离，并且连接到所选单元的字线由字驱动器。在连接到所选择的单元的字线被字驱动器激励的同时检测连接到所选单元的位/检测线中产生的信号。

7. 发明授权

US4376252A Bootstrapped driver circuit 失效
标题翻译：引导驱动电路
公开(公告)号：US4376252A
公开(公告)日：1983-03-08
申请号：US181318
申请日：1980-08-25
申请人： Charles J. Masenas, Jr.
发明人： Charles J. Masenas, Jr.
IPC分类号： H03K19/082 , H03K5/02 , H03K17/06 , H03K17/66 , H03K19/01 , H03K17/04 , H03K17/12 , H03K19/088
CPC分类号： H03K5/02
摘要： A driver circuit charges a capacitive load to a voltage substantially equal to the voltage or potential of the power supply of the circuit by first charging the capacitive load with current flowing through a drive transistor under the control of the power supply potential and, thereafter, at a predetermined time charging the capacitive load under the control of a precharged bootstrap capacitor. The driver circuit includes a transistor, acting as a pull-up device, connected between the power supply and the capacitive load and a series circuit including a charge source and switching means connected between the capacitive load and a control gate of the transistor. The switching means is coupled to the capacitive load so as to be responsive to the voltage at the load for directing charge from the charge source into the pull-up transistor at a predetermined time to raise the voltage at the capacitive load to substantially the potential of the power supply.
摘要翻译：驱动器电路通过在电源电位的控制下首先对流过驱动晶体管的电流对容性负载进行充电，然后将电容性负载充电到基本上等于电路电压或电位的电压，然后在在预充电自举电容器的控制下对电容性负载进行充电的预定时间。驱动器电路包括一个连接在电源和容性负载之间的上拉装置的晶体管，以及一个串联电路，包括一个连接在电容性负载和晶体管的控制栅之间的电荷源和开关装置。开关装置耦合到电容性负载，以便响应于负载处的电压，以在预定时间将电荷从电荷源引导到上拉晶体管中，以将电容负载处的电压升高到基本上为电源。

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