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1. 发明申请

US20110107589A1 PLANAR GROOVED POWER INDUCTOR STRUCTURE AND METHOD 有权
标题翻译：平面电力电力电感器结构与方法
公开(公告)号：US20110107589A1
公开(公告)日：2011-05-12
申请号：US13007551
申请日：2011-01-14
申请人： Francois Hebert , Tao Feng , Jun Lu
发明人： Francois Hebert , Tao Feng , Jun Lu
IPC分类号： H01F7/06
CPC分类号： H01F17/0033 , H01F1/344 , H01F41/046 , H01F2017/002 , Y10T29/4902
摘要： An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil.
摘要翻译：电感器可以包括平面铁氧体磁芯。第一组一个或多个凹槽形成在铁氧体磁芯的第一侧。在铁氧体磁芯的第二侧形成有第二组两个或多个凹槽。第一组和第二组中的凹槽被定向成使得第一组中的每个凹槽与第二组中的两个相应的凹槽重叠。第一多个通孔在铁氧体磁芯的第一和第二侧之间通过铁氧体磁芯连通。每个通孔位于第一组中的凹槽与第二组中的凹槽重叠的位置。导电材料设置在第一和第二组沟槽和通孔中以形成电感线圈。

2. 发明申请

US20090322461A1 PLANAR GROOVED POWER INDUCTOR STRUCTURE AND METHOD 有权
标题翻译：平面电力电力电感器结构与方法
公开(公告)号：US20090322461A1
公开(公告)日：2009-12-31
申请号：US12165423
申请日：2008-06-30
申请人： Francois Hebert , Tao Feng , Jun Lu
发明人： Francois Hebert , Tao Feng , Jun Lu
IPC分类号： H01F27/02
CPC分类号： H01F17/0033 , H01F1/344 , H01F41/046 , H01F2017/002 , Y10T29/4902
摘要： An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil.
摘要翻译：电感器可以包括平面铁氧体磁芯。第一组一个或多个凹槽形成在铁氧体磁芯的第一侧。在铁氧体磁芯的第二侧形成有第二组两个或多个凹槽。第一组和第二组中的凹槽被定向成使得第一组中的每个凹槽与第二组中的两个相应的凹槽重叠。第一多个通孔在铁氧体磁芯的第一和第二侧之间通过铁氧体磁芯连通。每个通孔位于第一组中的凹槽与第二组中的凹槽重叠的位置。导电材料设置在第一和第二组沟槽和通孔中以形成电感线圈。

3. 发明申请

US20090134964A1 Lead frame-based discrete power inductor 有权
标题翻译：引线框架分立功率电感
公开(公告)号：US20090134964A1
公开(公告)日：2009-05-28
申请号：US12011489
申请日：2008-01-25
申请人： Francois Hebert , Tao Feng , Xiaotian Zhang , Jun Lu
发明人： Francois Hebert , Tao Feng , Xiaotian Zhang , Jun Lu
IPC分类号： H01F5/00
CPC分类号： H01F17/062
摘要： A lead frame-based discrete power inductor is disclosed. The power inductor includes top and bottom lead frames, the leads of which form a coil around a single closed-loop magnetic core. The coil includes interconnections between inner and outer contact sections of the top and bottom lead frames, the magnetic core being sandwiched between the top and bottom lead frames. Ones of the leads of the top and bottom lead frames have a generally non-linear, stepped configuration such that the leads of the top lead frame couple adjacent leads of the bottom lead frame about the magnetic core to form the coil.
摘要翻译：公开了一种基于引线框架的分立功率电感器。功率电感器包括顶部和底部引线框架，其引线围绕单个闭环磁芯形成线圈。线圈包括顶部和底部引线框架的内部和外部接触部分之间的互连，磁芯夹在顶部和底部引线框架之间。顶部引线框架和底部引线框架的引线的一部分具有大致非线性的阶梯状构造，使得顶部引线框架的引线将底部引线框架的相邻引线围绕磁芯耦合以形成线圈。

4. 发明申请

US20090160045A1 WAFER LEVEL CHIP SCALE PACKAGING 有权
标题翻译： WAFER LEVEL CHIP SCALE包装
公开(公告)号：US20090160045A1
公开(公告)日：2009-06-25
申请号：US11963690
申请日：2007-12-21
申请人： Ming Sun , Tao Feng , Francois Hebert , Yueh-Se Ho
发明人： Ming Sun , Tao Feng , Francois Hebert , Yueh-Se Ho
IPC分类号： H01L23/06 , H01L21/304
CPC分类号： H01L21/6835 , H01L21/568 , H01L24/02 , H01L24/11 , H01L24/17 , H01L2221/68354 , H01L2224/0231 , H01L2224/0233 , H01L2224/0239 , H01L2224/0401 , H01L2224/04042 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01072 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H01L2924/00
摘要： A method for making back-to-front electrical connections in a wafer level chip scale packaging process is disclosed. A wafer containing a plurality of semiconductor chips is mounted on a package substrate. Each semiconductor chip in the plurality includes one or more electrodes on an exposed back side. Scribe lines between two or more adjacent chips on the wafer are removed to form relatively wide gaps. A conductive material is applied to the back side of the semiconductor chips and in the gaps. The conductive material in the gaps between two or more of the chips is then cut through leaving conductive material on the back side and on side walls of the two or more chips. As a result, the conductive material provides an electrical connection from the electrode on the back side of the chip to the front side of the chip.
摘要翻译：公开了一种用于在晶片级芯片级封装工艺中进行背对背电连接的方法。将包含多个半导体芯片的晶片安装在封装基板上。多个半导体芯片包括暴露背面的一个或多个电极。去除晶片上的两个或更多个相邻芯片之间的划痕线以形成较宽的间隙。将导电材料施加到半导体芯片的背面和间隙中。然后通过在两个或更多个芯片的背侧和侧壁上留下导电材料来切割两个或更多个芯片之间的间隙中的导电材料。结果，导电材料提供从芯片的背面上的电极到芯片的前侧的电连接。

5. 发明申请

US20090194880A1 WAFER LEVEL CHIP SCALE PACKAGE AND PROCESS OF MANUFACTURE 有权
标题翻译： WAFER LEVEL CHIP SCALE包装及其制造工艺
公开(公告)号：US20090194880A1
公开(公告)日：2009-08-06
申请号：US12023921
申请日：2008-01-31
申请人： Tao Feng , Francois Hebert , Ming Sun , Yueh-Se Ho
发明人： Tao Feng , Francois Hebert , Ming Sun , Yueh-Se Ho
IPC分类号： H01L23/48 , H01L21/304
CPC分类号： H01L29/7827 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/81 , H01L29/0657 , H01L29/41741 , H01L29/4175 , H01L29/45 , H01L29/49 , H01L29/7802 , H01L2224/02371 , H01L2224/03464 , H01L2224/0347 , H01L2224/0401 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06181 , H01L2224/06183 , H01L2224/16225 , H01L2224/16227 , H01L2224/81815 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.
摘要翻译：封装了功率晶圆级芯片级封装（CSP）和制造工艺。功率晶片级芯片级封装包括位于器件一侧的所有源极，栅极和漏极，方便用焊膏安装到印刷电路板（PCB）。

6. 发明申请

US20090160595A1 Compact Power Semiconductor Package and Method with Stacked Inductor and Integrated Circuit Die 有权
标题翻译：紧凑型功率半导体封装和堆叠电感和集成电路芯片的方法
公开(公告)号：US20090160595A1
公开(公告)日：2009-06-25
申请号：US12391251
申请日：2009-02-23
申请人： Tao Feng , Xiaolian Zhang , Francois Hebert , Ming Sun
发明人： Tao Feng , Xiaolian Zhang , Francois Hebert , Ming Sun
IPC分类号： H01F5/00 , H01L23/495 , H01L21/60
CPC分类号： H01L23/49861 , H01F17/0033 , H01F2027/2814 , H01L21/4832 , H01L21/563 , H01L23/495 , H01L23/4951 , H01L23/49548 , H01L23/49816 , H01L23/49827 , H01L24/48 , H01L24/49 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/48091 , H01L2224/49175 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/19107 , H01L2924/30107 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A power semiconductor package is disclosed with high inductance rating while exhibiting a reduced foot print. It has a bonded stack of power IC die at bottom, a power inductor at top and a circuit substrate, made of leadframe or printed circuit board, in the middle. The power inductor has a inductor core of closed magnetic loop. The circuit substrate has a first number of bottom half-coil forming conductive elements beneath the inductor core. A second number of top half-coil forming conductive elements, made of bond wires, three dimensionally formed interconnection plates or upper leadframe leads, are located atop the inductor core with both ends of each element connected to respective bottom half-coil forming conductive elements to jointly form an inductive coil enclosing the inductor core. A top encapsulant protectively encases the inductor core, the top half-coil forming conductive elements, the bottom half-coil forming conductive elements and the circuit substrate.
摘要翻译：公开了一种功率半导体封装，其具有高电感额定值，同时显示出减少的脚印。底部有一个电源IC芯片，顶部有一个功率电感器和一个由引线框或印刷电路板制成的电路基板。功率电感器具有闭合磁环的电感芯。电路衬底具有在电感器芯下方形成导电元件的第一数量的底部半线圈。由接合线，三维形成的互连板或上引线框引线构成的第二数量的上半线圈形成导电元件位于电感器芯的顶部，每个元件的两端连接到形成导电元件的相应底部半线圈，共同形成围绕电感器芯的感应线圈。顶部密封剂保护性地封装电感器芯，顶部半线圈形成导电元件，底部半线圈形成导电元件和电路衬底。

7. 发明申请

US20090134503A1 Semiconductor power device package having a lead frame-based integrated inductor 有权
标题翻译：具有引线框架的集成电感器的半导体功率器件封装
公开(公告)号：US20090134503A1
公开(公告)日：2009-05-28
申请号：US11986673
申请日：2007-11-23
申请人： Tao Feng , Xiaotian Zhang , Francois Hebert
发明人： Tao Feng , Xiaotian Zhang , Francois Hebert
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L23/495 , H01F17/0033 , H01F2027/2814 , H01L24/48 , H01L24/49 , H01L2224/05553 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2924/00014 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/10161 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A semiconductor power device package having a lead frame-based integrated inductor is disclosed. The semiconductor power device package includes a lead frame having a plurality of leads, a inductor core attached to the lead frame such that a plurality of lead ends are exposed through a window formed in the inductor core, a plurality of bonding wires, ones of the plurality of bonding wires coupling each of the plurality of lead ends to adjacent leads about the inductor core to form the inductor, and a power integrated circuit coupled to the inductor. In alternative embodiments, a top lead frame couples each of the plurality of lead ends to adjacent leads about the inductor core by means of a connection chip.
摘要翻译：公开了一种具有引线框架的集成电感器的半导体功率器件封装。半导体功率器件封装包括具有多个引线的引线框架，附接到引线框架的电感器芯，使得多个引线端通过形成在电感器芯中的窗体露出，多个接合线，多个接合线将多个引线端中的每一个连接到围绕电感器芯的相邻引线以形成电感器，以及耦合到电感器的功率集成电路。在替代实施例中，顶部引线框架通过连接芯片将多个引线端中的每一个耦合到围绕电感器芯的相邻引线。

8. 发明申请

US20080173969A1 Configuration of high-voltage semiconductor power device to achieve three dimensionalcharge coupling 有权
标题翻译：配置高压半导体功率器件实现三维电荷耦合
公开(公告)号：US20080173969A1
公开(公告)日：2008-07-24
申请号：US11656104
申请日：2007-01-22
申请人： Francois Hebert , Tao Feng
发明人： Francois Hebert , Tao Feng
IPC分类号： H01L29/423 , H01L21/28
CPC分类号： H01L29/7802 , H01L29/0653 , H01L29/66712 , H01L29/7395 , H01L29/7803 , H01L29/861 , H01L29/872
摘要： This invention discloses semiconductor device that includes a top region and a bottom region with an intermediate region disposed between said top region and said bottom region with a controllable current path traversing through the intermediate region. The semiconductor device further includes a trench with padded with insulation layer on sidewalls extended from the top region through the intermediate region toward the bottom region wherein the trench includes randomly and substantially uniformly distributed nano-nodules as charge-islands in contact with a drain region below the trench for electrically coupling with the intermediate region for continuously and uniformly distributing a voltage drop through the current path.
摘要翻译：本发明公开了一种半导体器件，其包括顶部区域和底部区域，其中间区域设置在所述顶部区域和所述底部区域之间，并具有穿过所述中间区域的可控电流通路。所述半导体器件还包括沟槽，该沟槽在从所述顶部区域延伸穿过所述中间区域朝向所述底部区域的侧壁上被填充有绝缘层，其中所述沟槽包括随机均匀分布的纳米结节，作为与下面的漏极区域接触的电荷岛用于与中间区域电耦合的沟槽，用于通过电流路径连续均匀地分配电压降。

9. 发明申请

US20090167477A1 Compact Inductive Power Electronics Package 有权
标题翻译：紧凑型感应电力电子封装
公开(公告)号：US20090167477A1
公开(公告)日：2009-07-02
申请号：US12397473
申请日：2009-03-04
申请人： Tao Feng , Xiaotian Zhang , Francois Hebert , Ming Sun
发明人： Tao Feng , Xiaotian Zhang , Francois Hebert , Ming Sun
IPC分类号： H01F5/00 , H01F41/00
CPC分类号： H01L23/495 , H01F3/14 , H01F17/0033 , H01F17/062 , H01F27/2828 , H01F2027/2814 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/16 , H01L2224/48091 , H01L2224/48465 , H01L2224/49175 , H01L2924/00014 , H01L2924/01019 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/3025 , Y10T29/49073 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00
摘要： An inductive power electronics package is disclosed. It has a circuit substrate with power inductor attached atop. The power inductor has inductor core of closed magnetic loop with an interior window. The closed magnetic loop can include air gap for inductance adjustment. The circuit substrate has bottom half-coil forming elements constituting a bottom half-coil beneath the inductor core. Also provided are top half-coil forming elements interconnected with the bottom half-coil forming elements to form an inductive coil enclosing the inductor core. An inner connection chip can be added in the interior window for interconnecting bottom half-coil forming elements with top half-coil forming elements. An outer connection chip can be added about the inductor core for interconnecting bottom half-coil forming elements with top half-coil forming elements outside the inductor core. A power Integrated Circuit can be attached to the top side of the circuit substrate as well.
摘要翻译：公开了感应电力电子封装。它有一个电路基板，带有功率电感器。功率电感器具有具有内部窗口的闭合磁环的电感器芯。封闭的磁环可以包括用于电感调节的气隙。电路基板具有构成电感器芯下方的下半线圈的底部半线圈形成元件。还提供了与底部半线圈形成元件互连以形成包围电感器芯的感应线圈的顶部半线圈形成元件。内部连接芯片可以添加到内部窗口中，用于将底部半线圈形成元件与顶部半线圈形成元件相互连接。外部连接芯片可以围绕电感器芯添加，用于将底部半线圈形成元件与电感器芯外部的顶部半线圈形成元件互连。功率集成电路也可以连接到电路基板的顶侧。

10. 发明申请

US20080242052A1 Method of forming ultra thin chips of power devices 审中-公开
标题翻译：形成功率器件超薄芯片的方法
公开(公告)号：US20080242052A1
公开(公告)日：2008-10-02
申请号：US11694888
申请日：2007-03-30
申请人： Tao Feng , Francois Hebert , Ming Sun , Yueh-Se Ho
发明人： Tao Feng , Francois Hebert , Ming Sun , Yueh-Se Ho
IPC分类号： H01L21/30
CPC分类号： H01L21/3043 , H01L21/78
摘要： A method for making thin semiconductor devices is disclosed. Starting from wafer with pre-fabricated front-side devices, the method includes: Thinning wafer central portion from its back-side to produce a thin region while preserving original wafer thickness in the wafer periphery for structural strength. Forming ohmic contact at wafer back-side. Separating and collecting pre-fabricated devices. This further includes: Releasably bonding wafer back-side onto single-sided dicing tape, in turn supported by a dicing frame. Providing a backing plate to match the thinned out wafer central portion. Sandwiching the dicing tape between wafer and backing plate then pressing the dicing tape to bond with the wafer. With a step-profiled chuck to support wafer back-side, the pre-fabricated devices are separated from each other and from the wafer periphery in one dicing operation with dicing depth slightly thicker than the wafer central portion. The separated thin semiconductor devices are then picked up and collected.
摘要翻译：公开了制造薄半导体器件的方法。从具有预制的前端器件的晶片开始，该方法包括：从其背面将晶片中心部分变薄以产生薄区域，同时在晶片周边保留原始晶片厚度以获得结构强度。在晶圆背面形成欧姆接触。分离和收集预制设备。这还包括：将晶片背面可释放地粘合到单面切割胶带上，然后由切割架支撑。提供背板以匹配变薄的晶片中心部分。将切割胶带夹在晶片和背板之间，然后按压切割胶带与晶片结合。利用阶梯型卡盘来支撑晶片背面，在一个切割操作中，预制的装置彼此分离并且与晶片周边分离，切割深度比晶片中心部分稍厚。然后拾取并收集分离的薄半导体器件。

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