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1. 发明授权

US06232639B1 Method and structure to reduce latch-up using edge implants 失效
标题翻译：使用边缘植入物减少闭锁的方法和结构
公开(公告)号：US06232639B1
公开(公告)日：2001-05-15
申请号：US09107900
申请日：1998-06-30
申请人： Faye D. Baker , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven J. Holmes , Robert K. Leidy , Edward J. Nowak , Steven H. Voldman
发明人： Faye D. Baker , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven J. Holmes , Robert K. Leidy , Edward J. Nowak , Steven H. Voldman
IPC分类号： H01L2976
CPC分类号： H01L21/823878 , H01L27/0921 , Y10S148/137
摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.
摘要翻译：本发明的优选实施例克服了现有技术的限制，并且提供了一种通过在阱边缘处形成植入物来增加CMOS器件的闩锁抗扰度的装置和方法。优选的方法使用混合抗蚀剂在N阱和/或P阱的边缘形成这些植入物。植入物减少了寄生晶体管中少数载流子的寿命，从而降低了寄生晶体管的增益。这降低了CMOS器件闭锁的倾向。优选实施例方法允许形成这些植入物，而不需要比现有技术方法更多的掩蔽步骤。此外，用于形成植入物的优选方法导致与孔的边缘自对准的植入物。

2. 发明授权

US6033949A Method and structure to reduce latch-up using edge implants 失效
标题翻译：使用边缘植入物减少闭锁的方法和结构
公开(公告)号：US6033949A
公开(公告)日：2000-03-07
申请号：US107813
申请日：1998-06-30
申请人： Faye D. Baker , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven J. Holmes , Robert K. Leidy , Edward J. Nowak , Steven H. Voldman
发明人： Faye D. Baker , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven J. Holmes , Robert K. Leidy , Edward J. Nowak , Steven H. Voldman
IPC分类号： H01L21/761 , G03F7/004 , H01L21/8238 , H01L27/08 , H01L27/092
CPC分类号： H01L21/823878 , H01L27/0921 , Y10S148/137
摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.
摘要翻译：本发明的优选实施例克服了现有技术的限制，并且提供了一种通过在阱边缘处形成植入物来增加CMOS器件的闩锁抗扰度的装置和方法。优选的方法使用混合抗蚀剂在N阱和/或P阱的边缘形成这些植入物。植入物减少了寄生晶体管中少数载流子的寿命，从而降低了寄生晶体管的增益。这降低了CMOS器件闭锁的倾向。优选实施例方法允许形成这些植入物，而不需要比现有技术方法更多的掩蔽步骤。此外，用于形成植入物的优选方法导致与孔的边缘自对准的植入物。

3. 发明授权

US5861330A Method and structure to reduce latch-up using edge implants 失效
公开(公告)号：US5861330A
公开(公告)日：1999-01-19
申请号：US852466
申请日：1997-05-07
申请人： Faye D. Baker , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven J. Holmes , Robert K. Leidy , Edward J. Nowak , Steven H. Voldman
发明人： Faye D. Baker , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven J. Holmes , Robert K. Leidy , Edward J. Nowak , Steven H. Voldman
IPC分类号： H01L21/761 , G03F7/004 , H01L21/8238 , H01L27/08 , H01L27/092
CPC分类号： H01L21/823878 , H01L27/0921 , Y10S148/137
摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.

4. 发明授权

US06256184B1 Method and apparatus for providing electrostatic discharge protection 有权
标题翻译：提供静电放电保护的方法和装置
公开(公告)号：US06256184B1
公开(公告)日：2001-07-03
申请号：US09334088
申请日：1999-06-16
申请人： Robert J. Gauthier Jr. , Edward J. Nowak , Steven H. Voldman , Richard Q. Williams
发明人： Robert J. Gauthier Jr. , Edward J. Nowak , Steven H. Voldman , Richard Q. Williams
IPC分类号： H02H322
CPC分类号： H01L27/0251 , H01L27/0266
摘要： An ESD protection method and apparatus are provided for an IC chip having an I/O pad and I/O circuitry coupled to the I/O pad. A low threshold voltage FET is coupled to the I/O pad in parallel with the I/O circuitry for protecting the IC chip from an ESD event on the I/O pad. The FET also is coupled to a first voltage terminal of the I/O circuitry for providing a shunting path for the ESD event, thereby effectuating the protecting of the IC chip from the ESD event on the I/O pad. A first control circuit is coupled to a gate of the FET for maintaining the gate at a voltage level below a threshold voltage of the FET, thereby maintaining the FET in an off state during normal operation of the IC chip. Preferably a second control circuit is coupled between the FET and the first voltage terminal and operates in conjunction with the first control circuit for maintaining the FET in an off state during normal operation of the IC chip. The first control circuit preferably comprises a short circuit between the gate of the FET and the first voltage terminal, an inverter coupled between the gate of the FET and a second voltage terminal or a negative bias generator coupled to the gate of the FET. The second control circuit preferably comprises a short circuit between the FET and the first voltage terminal or a diode coupled between the FET and the first voltage terminal.
摘要翻译：为具有耦合到I / O焊盘的I / O焊盘和I / O电路的IC芯片提供ESD保护方法和装置。低阈值电压FET与I / O电路并联耦合到I / O焊盘，以保护IC芯片免受I / O焊盘上的ESD事件。 FET还耦合到I / O电路的第一电压端子，用于为ESD事件提供分流路径，从而实现IC芯片免受I / O焊盘上的ESD事件的保护。第一控制电路耦合到FET的栅极，用于将栅极保持在低于FET阈值电压的电压电平，从而在IC芯片正常工作期间保持FET处于截止状态。优选地，第二控制电路耦合在FET和第一电压端子之间，并且与第一控制电路一起操作，以在IC芯片的正常操作期间将FET保持在截止状态。第一控制电路优选地包括在FET的栅极和第一电压端子之间的短路，耦合在FET的栅极和耦合到FET的栅极的第二电压端子或负偏压发生器之间的反相器。第二控制电路优选地包括FET和第一电压端子之间的短路或耦合在FET和第一电压端子之间的二极管。

5. 发明申请

US20090134463A1 SEMICONDUCTOR STRUCTURE AND SYSTEM FOR FABRICATING AN INTEGRATED CIRCUIT CHIP 有权
标题翻译：用于制造集成电路芯片的半导体结构和系统
公开(公告)号：US20090134463A1
公开(公告)日：2009-05-28
申请号：US12348344
申请日：2009-01-05
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, JR. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, JR. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
IPC分类号： H01L29/78
CPC分类号： H01L29/786 , H01L21/845 , H01L27/1211 , H01L29/4908 , H01L29/78615
摘要： A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa. The system for fabricating an integrated circuit chip enables: providing a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; and concurrently forming at least one fin-type field effect transistor and at least one thick-body device on the buried oxide layer.
摘要翻译：一种半导体结构和用于制造集成电路芯片的系统。半导体结构包括：半导体晶片上的掩埋氧化物层; 在所述掩埋氧化物层上的薄翅片结构，其中所述薄翅片结构包括半导体鳍片上的第一硬掩模，其中所述半导体鳍片设置在所述第一硬掩模和所述掩埋氧化物层的表面之间; 以及在所述掩埋氧化物层上的厚的台面结构，并且其中所述厚的台面结构包括半导体台面。用于制造集成电路芯片的系统能够：提供与半导体晶片直接机械接触的掩埋氧化物层; 并且在掩埋氧化物层上同时形成至少一个鳍式场效应晶体管和至少一个厚体器件。

6. 发明授权

US07163851B2 Concurrent Fin-FET and thick-body device fabrication 有权
标题翻译：并联Fin-FET和厚体器件制造
公开(公告)号：US07163851B2
公开(公告)日：2007-01-16
申请号：US10227995
申请日：2002-08-26
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
IPC分类号： H01L21/84
CPC分类号： H01L29/786 , H01L21/845 , H01L27/1211 , H01L29/4908 , H01L29/78615
摘要： The present invention provides methods for fabrication of fin-type field effect transistors (FinFETs) and thick-body devices on the same chip using common masks and steps to achieve greater efficiency than prior methods. The reduction in the number of masks and steps is achieved by using common masks and steps with several scaling strategies. In one embodiment, the structure normally associated with a FinFET is created on the side of a thick silicon mesa, the bulk of which is doped to connect with a body contact on the opposite side of the mesa. The invention also includes FinFETs, thick-body devices, and chips fabricated by the methods.
摘要翻译：本发明提供了使用公共掩模和步骤在相同芯片上制造鳍式场效应晶体管（FinFET）和厚体器件的方法，以实现比现有方法更高的效率。通过使用具有多种缩放策略的常用掩模和步骤来实现掩模和步骤数量的减少。在一个实施例中，通常与FinFET相关联的结构产生在厚硅台面的一侧，该厚硅台面的大部分被掺杂以与台面的相对侧上的身体接触连接。本发明还包括FinFET，厚体器件和通过这些方法制造的芯片。

7. 发明授权

US07473970B2 Concurrent fin-fet and thick body device fabrication 有权
标题翻译：并发鳍和厚体器件制造
公开(公告)号：US07473970B2
公开(公告)日：2009-01-06
申请号：US11481120
申请日：2006-07-05
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/786 , H01L21/845 , H01L27/1211 , H01L29/4908 , H01L29/78615
摘要： An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.
摘要翻译：集成电路芯片和半导体结构。集成电路芯片包括：包含半导体台面和掺杂体接触的厚体器件; 以及在半导体台面的第一侧壁上的场效应晶体管，其中所述掺杂体接触在所述半导体台面的第二侧壁上，并且其中所述半导体台面设置在所述场效应晶体管和所述掺杂体接触之间。半导体结构包括：半导体晶片上的掩埋氧化物层; 在所述掩埋氧化物层上的薄翅片结构，其中所述薄翅片结构包括半导体鳍片上的第一硬掩模，其中所述半导体鳍片设置在所述第一硬掩模和所述掩埋氧化物层的表面之间; 以及在所述掩埋氧化物层上的厚的台面结构，并且其中所述厚的台面结构包括半导体台面。

8. 发明授权

US07872310B2 Semiconductor structure and system for fabricating an integrated circuit chip 有权
标题翻译：用于制造集成电路芯片的半导体结构和系统
公开(公告)号：US07872310B2
公开(公告)日：2011-01-18
申请号：US12348344
申请日：2009-01-05
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
IPC分类号： H01L29/772
CPC分类号： H01L29/786 , H01L21/845 , H01L27/1211 , H01L29/4908 , H01L29/78615
摘要： A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa. The system for fabricating an integrated circuit chip enables: providing a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; and concurrently forming at least one fin-type field effect transistor and at least one thick-body device on the buried oxide layer.
摘要翻译：一种半导体结构和用于制造集成电路芯片的系统。半导体结构包括：半导体晶片上的掩埋氧化物层; 在所述掩埋氧化物层上的薄翅片结构，其中所述薄翅片结构包括半导体鳍片上的第一硬掩模，其中所述半导体鳍片设置在所述第一硬掩模和所述掩埋氧化物层的表面之间; 以及在所述掩埋氧化物层上的厚的台面结构，并且其中所述厚的台面结构包括半导体台面。用于制造集成电路芯片的系统能够：提供与半导体晶片直接机械接触的掩埋氧化物层; 并且在掩埋氧化物层上同时形成至少一个鳍式场效应晶体管和至少一个厚体器件。

9. 发明授权

US06171918B2 Depleted poly mosfet structure and method 失效
标题翻译：消耗多晶硅结构和方法
公开(公告)号：US06171918B2
公开(公告)日：2001-01-09
申请号：US09102413
申请日：1998-06-22
申请人： Jeffrey S. Brown , Robert J. Gauthier , Edward J. Nowak , Minh H. Tong , Steven H. Voldman
发明人： Jeffrey S. Brown , Robert J. Gauthier , Edward J. Nowak , Minh H. Tong , Steven H. Voldman
IPC分类号： H01L218238
CPC分类号： H01L29/6659 , H01L21/823842 , H01L29/665
摘要： A method for doping a poly depleted semiconductor transistor, the semiconductor transistor including a gate region, a source region adjacent the gate region and a drain region adjacent the gate region and opposite the source region, the method comprising steps of exposing the gate region to a first ion implantation and shielding the gate region from a second ion implantation step.
摘要翻译：一种用于掺杂多晶硅半导体晶体管的方法，所述半导体晶体管包括栅极区域，与栅极区域相邻的源极区域和与栅极区域相邻并与源极区域相对的漏极区域，所述方法包括以下步骤：将栅极区域暴露于第一离子注入和屏蔽栅极区域与第二离子注入步骤。

10. 发明授权

US06646305B2 Grounded body SOI SRAM cell 有权
标题翻译：接地体SOI SRAM单元
公开(公告)号：US06646305B2
公开(公告)日：2003-11-11
申请号：US09915061
申请日：2001-07-25
申请人： Fariborz Assaderaghi , Andres Bryant , Peter E. Cottrell , Robert J. Gauthier, Jr. , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
发明人： Fariborz Assaderaghi , Andres Bryant , Peter E. Cottrell , Robert J. Gauthier, Jr. , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L2701
CPC分类号： H01L27/1203 , H01L27/1104
摘要： A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to VDD.
摘要翻译：一种半导体存储器件，包括：在衬底绝缘体的顶部上具有薄硅层的SOI衬底; 以及包括四个NFET和位于薄硅层中的两个PFET的SRAM，每个NFET和PFET具有在源极区域和漏极区域之间的主体区域，其中两个NFET的主体电连接到地。另外，两个PFET的主体电连接到VDD。

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