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1. 发明授权

US07685553B2 System and method for global circuit routing incorporating estimation of critical area estimate metrics 失效
标题翻译：用于全局电路路由的系统和方法，其中包括关键面积估计度量的估计
公开(公告)号：US07685553B2
公开(公告)日：2010-03-23
申请号：US11733795
申请日：2007-04-11
申请人： Evanthia Papadopoulou , Ruchir Puri , Mervyn Y. Tan , Louise H. Trevillyan , Hua Xiang
发明人： Evanthia Papadopoulou , Ruchir Puri , Mervyn Y. Tan , Louise H. Trevillyan , Hua Xiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.
摘要翻译：电子电路布局细化方法和系统。在电路布局区域上定义了一个大小相同的瓷砖网格。电网的每个瓦片具有与放置在电路布局区域上的电路的关键面积估计相关联的相应临界面积估计量度。执行用于放置在电网的多个瓦片内的电路的全局电路布线。在对电路执行详细的电路布线之前执行分配给电网的各个瓦片的关键面积估计度量的估计。在估计关键区域估计度量之后，调整全局电路路由，以便改进分配给网格的至少一个瓦片的相应临界区域估计度量。然后生成经调整的全局电路布线。

2. 发明申请

US20080256502A1 SYSTEM AND METHOD FOR GLOBAL CIRCUIT ROUTING INCORPORATING ESTIMATION OF CRITICAL AREA ESTIMATE METRICS 失效
标题翻译：全球电路路由系统与方法，适用于关键领域估算的估计
公开(公告)号：US20080256502A1
公开(公告)日：2008-10-16
申请号：US11733795
申请日：2007-04-11
申请人： Evanthia Papadopoulou , Ruchir Puri , Mervyn Y. Tan , Louise H. Trevillyan , Hua Xiang
发明人： Evanthia Papadopoulou , Ruchir Puri , Mervyn Y. Tan , Louise H. Trevillyan , Hua Xiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.
摘要翻译：电子电路布局细化方法和系统。在电路布局区域上定义了一个大小相同的瓷砖网格。电网的每个瓦片具有与放置在电路布局区域上的电路的关键面积估计相关联的相应临界面积估计量度。执行用于放置在电网的多个瓦片内的电路的全局电路布线。在对电路执行详细的电路布线之前执行分配给电网的各个瓦片的关键面积估计度量的估计。在估计关键区域估计度量之后，调整全局电路路由，以便改进分配给网格的至少一个瓦片的相应临界区域估计度量。然后生成经调整的全局电路布线。

3. 发明申请

US20080168414A1 METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR DISPLAYING AND MODIFYING THE CRITICAL AREA OF AN INTEGRATED CIRCUIT DESIGN. 失效
标题翻译：用于显示和修改集成电路设计关键领域的方法，装置和计算机程序产品。
公开(公告)号：US20080168414A1
公开(公告)日：2008-07-10
申请号：US11620059
申请日：2007-01-05
申请人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.
摘要翻译：一种用于可视地指示有助于定义的关键区域图案的设计的一个或多个边缘之间的交互的方法，装置和计算机程序产品。

4. 发明授权

US07752589B2 Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design 失效
标题翻译：用于显示和修改集成电路设计的关键区域的方法，装置和计算机程序产品
公开(公告)号：US07752589B2
公开(公告)日：2010-07-06
申请号：US11620059
申请日：2007-01-05
申请人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.
摘要翻译：一种用于可视地指示有助于定义的关键区域图案的设计的一个或多个边缘之间的交互的方法，装置和计算机程序产品。

5. 发明授权

US07661080B2 Method and apparatus for net-aware critical area extraction 失效
标题翻译：网络关键区域提取的方法和装置
公开(公告)号：US07661080B2
公开(公告)日：2010-02-09
申请号：US11626576
申请日：2007-01-24
申请人： Evanthia Papadopoulou , Sarah Braasch , Mervyn Y. Tan
发明人： Evanthia Papadopoulou , Sarah Braasch , Mervyn Y. Tan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： In one embodiment, the present invention is a method and apparatus for net-aware critical area extraction. One embodiment of the inventive method for determining the critical area of an integrated circuit includes modeling a net corresponding to the integrated circuit as a graph, where the net is made up of a plurality of interconnected shapes spanning one or more layers of the integrated circuit. All generators for opens are then defined and identified. The Voronoi diagram of the identified generators is computed, and the critical area is computed in accordance with the Voronoi diagram.
摘要翻译：在一个实施例中，本发明是一种用于网络感知关键区域提取的方法和装置。用于确定集成电路的关键区域的本发明方法的一个实施例包括将对应于集成电路的网络建模为图，其中网络由跨越集成电路的一个或多个层的多个互连形状组成。然后定义和识别所有用于打开的发生器。计算识别的发电机的Voronoi图，并根据Voronoi图计算临界面积。

6. 发明申请

US20080178137A1 METHOD AND APPARATUS FOR NET-AWARE CRITICAL AREA EXTRACTION 失效
标题翻译：网络关键领域提取的方法和装置
公开(公告)号：US20080178137A1
公开(公告)日：2008-07-24
申请号：US11626576
申请日：2007-01-24
申请人： Evanthia Papadopoulou , Sarah Braasch , Mervyn Y. Tan
发明人： Evanthia Papadopoulou , Sarah Braasch , Mervyn Y. Tan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： In one embodiment, the present invention is a method and apparatus for net-aware critical area extraction. One embodiment of the inventive method for determining the critical area of an integrated circuit includes modeling a net corresponding to the integrated circuit as a graph, where the net is made up of a plurality of interconnected shapes spanning one or more layers of the integrated circuit. All generators for opens are then defined and identified. The Voronoi diagram of the identified generators is computed, and the critical area is computed in accordance with the Voronoi diagram.
摘要翻译：在一个实施例中，本发明是一种用于网络感知关键区域提取的方法和装置。用于确定集成电路的关键区域的本发明方法的一个实施例包括将对应于集成电路的网络建模为图，其中网络由跨越集成电路的一个或多个层的多个互连形状组成。然后定义和识别所有用于打开的发生器。计算识别的发电机的Voronoi图，并根据Voronoi图计算临界面积。

7. 发明授权

US07240306B2 Integrated circuit layout critical area determination using Voronoi diagrams and shape biasing 有权
标题翻译：使用Voronoi图和形状偏置的集成电路布局临界区域确定
公开(公告)号：US07240306B2
公开(公告)日：2007-07-03
申请号：US10906553
申请日：2005-02-24
申请人： Robert J. Allen , Peter K. Chan , Evanthia Papadopoulou , Sarah C. Prue , Mervyn Y. Tan
发明人： Robert J. Allen , Peter K. Chan , Evanthia Papadopoulou , Sarah C. Prue , Mervyn Y. Tan
IPC分类号： G06F17/50 , G06F19/00 , G06F17/10 , G06F11/00 , G06K9/03 , G06K9/52
CPC分类号： G06F17/5081
摘要： Method, system and program product for determining a critical area in a region of an integrated circuit layout using Voronoi diagrams and shape biasing. The method includes the steps of generating a biased Voronoi diagram based on a layout geometry of the region and incorporating a shape bias; and determining the critical area for the region using the biased Voronoi diagram.
摘要翻译：用于使用Voronoi图和形状偏置来确定集成电路布局的区域中的临界区域的方法，系统和程序产品。该方法包括以下步骤：基于该区域的布局几何形状并结合形状偏差产生偏置Voronoi图; 并使用偏倚的Voronoi图确定该地区的关键区域。

8. 发明申请

US20090031266A1 IC DESIGN MODELING ALLOWING DIMENSION-DEPENDENT RULE CHECKING 失效
标题翻译： IC设计建模允许尺寸依赖规则检查
公开(公告)号：US20090031266A1
公开(公告)日：2009-01-29
申请号：US12186769
申请日：2008-08-06
申请人： Evanthia Papadopoulou , Daniel N. Maynard
发明人： Evanthia Papadopoulou , Daniel N. Maynard
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.
摘要翻译：一种用于对IC设计进行建模的方法，系统和程序产品，以一致的方式包括诸如局部宽度和IC形状间隔的尺寸。特别地，本发明使用Voronoi图的核心部分将形状的边缘划分成间隔，并且为每个间隔分配至少一个维度，例如局部宽度和间隔。尺寸分配可以作为针对宽度和间距设置的任何期望的定义，例如数值或连续尺寸依赖的设计规则。设计规则检查以尺寸为依据的间距规则，以宽度和间距的任意功能形式给出是可能的。本发明的应用可以在VLSI形状的宽度和间距例如相对于单个边缘，相邻边缘，相邻形状和/或针对IC设计的多于一个层中的边缘发挥作用的任何地方进行。

9. 发明申请

US20090031263A1 METHOD AND SYSTEM FOR ANALYZING AN INTEGRATED CIRCUIT BASED ON SAMPLE WINDOWS SELECTED USING AN OPEN DETERMINISTIC SEQUENCING TECHNIQUE 有权
标题翻译：基于使用开放式确定性测序技术选择的样本窗口分析集成电路的方法和系统
公开(公告)号：US20090031263A1
公开(公告)日：2009-01-29
申请号：US11828728
申请日：2007-07-26
申请人： Sarah C. Braasch , Jason D. Hibbeler , Rouwaida N. Kanj , Daniel N. Maynard , Sani R. Nassif , Evanthia Papadopoulou
发明人： Sarah C. Braasch , Jason D. Hibbeler , Rouwaida N. Kanj , Daniel N. Maynard , Sani R. Nassif , Evanthia Papadopoulou
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in an integrated circuit layout. Then, the value of the particular attribute is determined for each sample window and the results are accumulated in order to infer an overall value for that particular attribute for the entire integrated circuit layout. This sequencing technique has the advantage of allowing additional sample windows to be added and/or the sizes and shapes of the windows to be varied without hindering the quality of the sample.
摘要翻译：这里公开的是用于分析集成电路以确定该集成电路中的特定属性（即，物理或电气特性）的值的系统和相关方法的实施例。在实施例中，使用开放确定性测序技术来选择表示集成电路布局中的样本窗口中心的点序列。然后，为每个采样窗口确定特定属性的值，并累积结果，以推断整个集成电路布局的该特定属性的总体值。这种测序技术具有允许添加附加样品窗口和/或改变窗口的尺寸和形状而不妨碍样品质量的优点。

10. 发明授权

US07577927B2 IC design modeling allowing dimension-dependent rule checking 失效
标题翻译： IC设计建模允许维度依赖的规则检查
公开(公告)号：US07577927B2
公开(公告)日：2009-08-18
申请号：US12186764
申请日：2008-08-06
申请人： Evanthia Papadopoulou , Daniel N. Maynard
发明人： Evanthia Papadopoulou , Daniel N. Maynard
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.
摘要翻译：一种用于对IC设计进行建模的方法，系统和程序产品，以一致的方式包括诸如局部宽度和IC形状间隔的尺寸。特别地，本发明使用Voronoi图的核心部分将形状的边缘划分成间隔，并且为每个间隔分配至少一个维度，例如局部宽度和间隔。尺寸分配可以作为针对宽度和间距设置的任何期望的定义，例如数值或连续尺寸依赖的设计规则。设计规则检查以尺寸为依据的间距规则，以宽度和间距的任意功能形式给出是可能的。本发明的应用可以在VLSI形状的宽度和间距例如相对于单个边缘，相邻边缘，相邻形状和/或针对IC设计的多于一个层中的边缘发挥作用的任何地方进行。

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