会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Coupling capacitor and semiconductor memory device using the same
    • 耦合电容器和使用其的半导体存储器件
    • US07602043B2
    • 2009-10-13
    • US11461344
    • 2006-07-31
    • Eun-Cheol LeeWon-Suk YangJin-Woo LeeTae-Young Chung
    • Eun-Cheol LeeWon-Suk YangJin-Woo LeeTae-Young Chung
    • H01L27/06H01L27/08
    • H01L28/91G11C11/4091
    • A coupling capacitor and a semiconductor memory device using the same are provided. In an embodiment, each memory cell of the semiconductor memory device includes a coupling capacitor so that a storage capacitor can store at least 2 bits of data. The coupling capacitor has a capacitance having a predetermined ratio with respect to the capacitance of the storage capacitor. For this, the coupling capacitor is formed by substantially the same fabrication process as the storage capacitor. The predetermined ratio is obtained by choosing an appropriate number of individual capacitors, each with the same capacitance of the storage capacitor, to comprise the coupling capacitor. Also, the coupling capacitor is disposed on an interlayer insulating layer that buries a bit line in a cell region and a sense amplifier in a sense amplifier region.
    • 提供耦合电容器和使用该耦合电容器的半导体存储器件。 在一个实施例中,半导体存储器件的每个存储单元包括耦合电容器,使得存储电容器可以存储至少2位的数据。 耦合电容器具有相对于存储电容器的电容具有预定比率的电容。 为此,耦合电容器通过与存储电容器基本上相同的制造工艺来形成。 通过选择适当数量的各个具有相同电容的存储电容器的单个电容器来获得预定比率,以包括耦合电容器。 此外,耦合电容器设置在掩埋单元区域中的位线和读出放大器区域中的读出放大器的层间绝缘层上。
    • 5. 发明申请
    • Semiconductor devices including transistors having recessed channels and methods of fabricating the same
    • 包括具有凹陷通道的晶体管的半导体器件及其制造方法
    • US20080001230A1
    • 2008-01-03
    • US11704872
    • 2007-02-09
    • Jin-Woo LeeTae-Young ChungSung-Hee Han
    • Jin-Woo LeeTae-Young ChungSung-Hee Han
    • H01L29/78H01L21/336
    • H01L29/78H01L21/823437H01L21/823481H01L29/4236H01L29/42376H01L29/66621
    • Semiconductor devices including an isolation layer on a semiconductor substrate are provided. The isolation layer defines an active region of the semiconductor substrate. The device further includes an upper gate electrode crossing over the active region and extending to the isolation layer and lower active gate electrode. The lower active gate electrode includes a first active gate electrode extending from the upper gate electrode to the active region and a second active gate electrode below the first active gate electrode and having a greater width than a width of the first active gate electrode. The device further includes a lower field gate electrode that extends from the upper gate electrode to the isolation layer and has a bottom surface that is at a lower level than a bottom surface of the active gate electrode such that the sidewalls of the active region are covered below the lower active gate electrode. Related methods of fabricating semiconductor devices are also provided herein.
    • 提供包括半导体衬底上的隔离层的半导体器件。 隔离层限定半导体衬底的有源区。 该器件还包括与有源区交叉并延伸到隔离层和下活性栅电极的上栅电极。 下有源栅电极包括从上栅极延伸到有源区的第一有源栅电极和位于第一有源栅电极下方并且具有比第一有源栅电极的宽度更大的宽度的第二有源栅电极。 该器件还包括一个从上部栅电极延伸到隔离层的下部栅极电极,并且具有一底部表面,该底表面处于与该有源栅极电极的底表面相比较低的位置,使得该有源区域的侧壁被覆盖 在下部有源栅电极下方。 本文还提供了制造半导体器件的相关方法。
    • 8. 发明授权
    • Methods of fabricating semiconductor devices including transistors having recessed channels
    • 制造包括具有凹槽的晶体管的半导体器件的方法
    • US07666743B2
    • 2010-02-23
    • US11704872
    • 2007-02-09
    • Jin-Woo LeeTae-Young ChungSung-Hee Han
    • Jin-Woo LeeTae-Young ChungSung-Hee Han
    • H01L21/336
    • H01L29/78H01L21/823437H01L21/823481H01L29/4236H01L29/42376H01L29/66621
    • Semiconductor devices including an isolation layer on a semiconductor substrate are provided. The isolation layer defines an active region of the semiconductor substrate. The device further includes an upper gate electrode crossing over the active region and extending to the isolation layer and lower active gate electrode. The lower active gate electrode includes a first active gate electrode extending from the upper gate electrode to the active region and a second active gate electrode below the first active gate electrode and having a greater width than a width of the first active gate electrode. The device further includes a lower field gate electrode that extends from the upper gate electrode to the isolation layer and has a bottom surface that is at a lower level than a bottom surface of the active gate electrode such that the sidewalls of the active region are covered below the lower active gate electrode. Related methods of fabricating semiconductor devices are also provided herein.
    • 提供包括半导体衬底上的隔离层的半导体器件。 隔离层限定了半导体衬底的有源区。 该器件还包括与有源区交叉并延伸到隔离层和下活性栅电极的上栅电极。 下有源栅电极包括从上栅极延伸到有源区的第一有源栅电极和位于第一有源栅电极下方并且具有比第一有源栅电极的宽度更大的宽度的第二有源栅电极。 该器件还包括一个从上部栅电极延伸到隔离层的下部栅极电极,并且具有一底部表面,该底表面处于与该有源栅极电极的底表面相比较低的位置,使得该有源区域的侧壁被覆盖 在下部有源栅电极下方。 本文还提供了制造半导体器件的相关方法。