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1. 发明授权

US07923331B2 Method of fabricating recess channel transistor having locally thick dielectrics and related devices 有权
标题翻译：制造具有局部厚电介质和相关器件的凹槽沟道晶体管的方法
公开(公告)号：US07923331B2
公开(公告)日：2011-04-12
申请号：US12232020
申请日：2008-09-10
申请人： Sung-Hee Han , Jin-Woo Lee , Tae-Young Chung , Ja-Young Lee
发明人： Sung-Hee Han , Jin-Woo Lee , Tae-Young Chung , Ja-Young Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/3247 , H01L29/1037 , H01L29/42376 , H01L29/66553 , H01L29/66621 , H01L29/78
摘要： Provided are a method of fabricating a recess channel transistor and a related semiconductor device. The method may include forming a first gate trench on a substrate, forming a dielectric spacer on a sidewall of the first gate trench, forming a second gate trench on the substrate under the first gate trench, and forming a gate electrode to fill the trenches. The dielectric spacer may remain between the gate electrode and the substrate.
摘要翻译：提供一种制造凹槽通道晶体管和相关半导体器件的方法。该方法可以包括在衬底上形成第一栅极沟槽，在第一栅极沟槽的侧壁上形成电介质间隔物，在第一栅极沟槽下面的衬底上形成第二栅极沟槽，以及形成栅电极以填充沟槽。电介质隔离物可以保留在栅电极和衬底之间。

2. 发明申请

US20090127609A1 Method of fabricating recess channel transistor having locally thick dielectrics and related devices 有权
标题翻译：制造具有局部厚电介质和相关器件的凹槽沟道晶体管的方法
公开(公告)号：US20090127609A1
公开(公告)日：2009-05-21
申请号：US12232020
申请日：2008-09-10
申请人： Sung-Hee Han , Jin-Woo Lee , Tae-Young Chung , Ja-Young Lee
发明人： Sung-Hee Han , Jin-Woo Lee , Tae-Young Chung , Ja-Young Lee
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L21/3247 , H01L29/1037 , H01L29/42376 , H01L29/66553 , H01L29/66621 , H01L29/78
摘要： Provided are a method of fabricating a recess channel transistor and a related semiconductor device. The method may include forming a first gate trench on a substrate, forming a dielectric spacer on a sidewall of the first gate trench, forming a second gate trench on the substrate under the first gate trench, and forming a gate electrode to fill the trenches. The dielectric spacer may remain between the gate electrode and the substrate.
摘要翻译：提供一种制造凹槽通道晶体管和相关半导体器件的方法。该方法可以包括在衬底上形成第一栅极沟槽，在第一栅极沟槽的侧壁上形成电介质间隔物，在第一栅极沟槽下面的衬底上形成第二栅极沟槽，以及形成栅电极以填充沟槽。电介质隔离物可以保留在栅电极和衬底之间。

3. 发明申请

US20080296670A1 Semiconductor Devices Including Transistors Having a Recessed Channel Region and Methods of Fabricating the Same 审中-公开
标题翻译：包括具有嵌入式通道区域的晶体管的半导体器件及其制造方法
公开(公告)号：US20080296670A1
公开(公告)日：2008-12-04
申请号：US12128190
申请日：2008-05-28
申请人： Ja-Young Lee , Jin-Woo Lee , Sung-Hee Han , Tai-Su Park , Hyun-Sook Byun
发明人： Ja-Young Lee , Jin-Woo Lee , Sung-Hee Han , Tai-Su Park , Hyun-Sook Byun
IPC分类号： H01L49/00 , H01L21/26
CPC分类号： H01L29/66621 , H01L21/26586 , H01L29/78
摘要： Some embodiments of the present invention provide semiconductor devices including a gate trench in an active region of a semiconductor substrate and a gate electrode in the gate trench. A low-concentration impurity region is provided in the active region adjacent to a sidewall of the gate trench. A high-concentration impurity region is provided between the low-concentration impurity region and the sidewall of the gate trench and along the sidewall of the gate trench. Related methods of fabricating semiconductor devices are also provided herein.
摘要翻译：本发明的一些实施例提供半导体器件，其包括半导体衬底的有源区中的栅极沟槽和栅极沟槽中的栅电极。在与栅极沟槽的侧壁相邻的有源区域中提供低浓度杂质区域。在低浓度杂质区域和栅极沟槽的侧壁之间并且沿着栅极沟槽的侧壁设置高浓度杂质区域。本文还提供了制造半导体器件的相关方法。

4. 发明授权

US09281362B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09281362B2
公开(公告)日：2016-03-08
申请号：US14286441
申请日：2014-05-23
申请人： Ja-Young Lee , Se-myeong Jang
发明人： Ja-Young Lee , Se-myeong Jang
IPC分类号： H01L29/06 , H01L21/762 , H01L27/108 , H01L27/115
CPC分类号： H01L29/0649 , H01L21/76229 , H01L27/10894 , H01L27/10897 , H01L27/11531
摘要： According to an example embodiment, a semiconductor device includes a substrate having a cell array region and a peripheral circuit region. The substrate includes first active regions defined by a first trench isolation region in the cell array region, a second active region defined by a second trench isolation region in the peripheral circuit region, and at least one deep trench isolation region. The first active regions may be aligned to extend longitudinally in a first direction in the cell array region. The at least one deep trench isolation region is recessed in the substrate to a level lower than those of other points of a bottom surface of the second trench isolation region in the peripheral circuit region. The at least one deep trench isolation region includes at least one point that is spaced apart in the first direction from a corresponding one of the first active regions.
摘要翻译：根据示例性实施例，半导体器件包括具有单元阵列区域和外围电路区域的衬底。衬底包括由电池阵列区域中的第一沟槽隔离区域限定的第一有源区，由外围电路区域中的第二沟槽隔离区限定的第二有源区和至少一个深沟槽隔离区。第一有源区可以对齐以在单元阵列区域中沿第一方向纵向延伸。所述至少一个深沟槽隔离区域在所述衬底中凹陷到比所述外围电路区域中的所述第二沟槽隔离区域的底表面的其它点的电平低的水平。所述至少一个深沟槽隔离区域包括在第一方向上与相应的第一有源区域间隔开的至少一个点。

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