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1. 发明授权

US07749396B2 Method of manufacturing fine features for thin film transistors 有权
标题翻译：制造薄膜晶体管精细特征的方法
公开(公告)号：US07749396B2
公开(公告)日：2010-07-06
申请号：US11388731
申请日：2006-03-24
申请人： Eugene M. Chow , William S. Wong , Michael Chabinyc , Ana Claudia Arias
发明人： Eugene M. Chow , William S. Wong , Michael Chabinyc , Ana Claudia Arias
IPC分类号： H01B13/00 , C23F1/00
CPC分类号： H01L29/4908 , H01L27/124 , H01L27/1292
摘要： A process for fabricating fine features such as small gate electrodes on a transistor. The process involves the jet-printing of a mask and the plating of a metal to fabricate sub-pixel and standard pixel size features in one layer. Printing creates a small sub-pixel size gap mask for plating a fine feature. A second printed mask may be used to protect the newly formed gate and etch standard pixel size lines connecting the small gates.
摘要翻译：一种在晶体管上制造诸如小栅电极的精细特征的工艺。该方法涉及一种掩模的喷墨印刷和金属镀层，以在一层中制造亚像素和标准像素尺寸特征。打印创建一个小的子像素大小的间隙掩模，用于电镀精细特征。可以使用第二印刷掩模来保护新形成的栅极并蚀刻连接小栅极的标准像素尺寸线。

2. 发明授权

US07524768B2 Method using monolayer etch masks in combination with printed masks 失效
标题翻译：使用单层蚀刻掩模与印刷掩模组合的方法
公开(公告)号：US07524768B2
公开(公告)日：2009-04-28
申请号：US11388718
申请日：2006-03-24
申请人： Eugene M. Chow , William S. Wong , Michael Chabinyc , Jeng Ping Lu , Ana Claudia Arias
发明人： Eugene M. Chow , William S. Wong , Michael Chabinyc , Jeng Ping Lu , Ana Claudia Arias
IPC分类号： H01L21/302
CPC分类号： H01L21/302 , H01L21/0271 , H01L21/0273 , H01L27/124 , H01L27/1288 , H01L27/1292 , H01L29/66765
摘要： A method to pattern films into dimensions smaller than the printed pixel mask size. A printed mask is deposited on a thin film on a substrate. The second mask layer is selectively deposited onto the film, but not to the printed mask. A third mask is then printed onto the substrate to pattern a portion of the second mask. Certain solvents are then used to remove the printed mask but not the mask layer on the thin film. The mask layer is then used to form a pattern on the thin film in combination with etching. The features formed in the thin film are smaller than the smallest dimension of the printed mask. The coated mask layer can be a self-assembled mono-layer or other material that selectively binds to the thin film.
摘要翻译：将薄膜图案尺寸小于印刷像素掩模尺寸的方法。印刷的掩模沉积在基底上的薄膜上。第二掩模层选择性地沉积在膜上，而不是印刷在掩模上。然后将第三掩模印刷到基底上以对第二掩模的一部分进行图案化。然后使用某些溶剂去除印刷的掩模，而不是薄膜上的掩模层。然后将掩模层与蚀刻结合在薄膜上形成图案。形成在薄膜中的特征小于印刷掩模的最小尺寸。涂覆的掩模层可以是选择性地结合薄膜的自组装单层或其它材料。

3. 发明授权

US07964440B2 Phase-separated composite films and methods of preparing the same 有权
标题翻译：相分离复合膜及其制备方法
公开(公告)号：US07964440B2
公开(公告)日：2011-06-21
申请号：US11015795
申请日：2004-12-20
申请人： Alberto Salleo , Ana Claudia Arias , William S. Wong
发明人： Alberto Salleo , Ana Claudia Arias , William S. Wong
IPC分类号： H01L51/40
CPC分类号： B82Y30/00 , H01L27/28 , H01L51/0004 , H01L51/0015
摘要： Composite films formed from blends of semiconducting and insulating materials that phase separate on patterned substrates are provided. Phase separation provides isolated and encapsulated areas of semiconductor on the substrate. Processes for preparing and using such composite films are also provided, along with devices including such composite films.
摘要翻译：提供由在图案化衬底上相分离的半导体和绝缘材料的共混物形成的复合膜。相分离在衬底上提供隔离和封装的半导体区域。还提供了制备和使用这种复合膜的方法以及包括这种复合膜的装置。

4. 发明授权

US07514114B2 Detecting defective ejector in digital lithography system 失效
标题翻译：在数字光刻系统中检测有缺陷的喷射器
公开(公告)号：US07514114B2
公开(公告)日：2009-04-07
申请号：US11218416
申请日：2005-09-01
申请人： William S. Wong , Steven E. Ready , Ana Claudia Arias
发明人： William S. Wong , Steven E. Ready , Ana Claudia Arias
IPC分类号： C23C16/52 , B05D5/12
CPC分类号： B41J29/393
摘要： A digital lithography system prints a large-area electronic device by dividing the overall device printing process into a series of discrete feature printing sub-processes, where each feature printing sub-process involves printing both a predetermined portion (feature) of the device in a designated substrate area, and an associated test pattern in a designated test area that is remote from the feature. At the end of each feature printing sub-process, the test pattern is analyzed, e.g., using a camera and associated imaging system, to verify that the test pattern has been successfully printed. A primary ejector is used until an unsuccessfully printed test pattern is detected, at which time a secondary (reserve) ejector replaces the primary ejector and reprints the feature associated with the defective test pattern. When multiple printheads are used in parallel, analysis of the test pattern is used to efficiently identify the location of a defective ejector.
摘要翻译：数字光刻系统通过将整个设备打印过程划分成一系列离散特征打印子过程来打印大面积电子设备，其中每个特征打印子过程涉及将设备的预定部分（特征）打印在一个指定的基板区域以及远离该特征的指定测试区域中的关联测试图案。在每个特征打印子过程结束时，分析测试图案，例如使用相机和相关联的成像系统来验证测试图案是否已被成功打印。使用初级喷射器，直到检测到未成功打印的测试图案，此时次要（预留）喷射器取代主喷射器并重印与缺陷测试图案相关的特征。当并行使用多个打印头时，使用测试图案的分析来有效地识别有缺陷的喷射器的位置。

5. 发明申请

US20100252927A1 Pattern-Print Thin-Film Transistors with Top Gate Geometry 有权
标题翻译：带顶栅几何图案印刷薄膜晶体管
公开(公告)号：US20100252927A1
公开(公告)日：2010-10-07
申请号：US12817127
申请日：2010-06-16
申请人： William S. Wong , Rene A. Lujan , Eugene M. Chow
发明人： William S. Wong , Rene A. Lujan , Eugene M. Chow
IPC分类号： H01L29/45
CPC分类号： H01L29/41733 , H01L27/124 , H01L27/1285 , H01L27/1288 , H01L27/1292 , H01L29/42384 , H01L29/4908 , H01L29/66757
摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.
摘要翻译：公开了一种自对准薄膜顶栅晶体管及其制造方法。通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。在其上形成半导体层和绝缘层。然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。在感光材料的显影之后，沉积栅极金属层。然后再次通过数字光刻法在器件上形成第二印刷图案掩模。蚀刻和去除感光材料离开自对准顶栅电极。

6. 发明授权

US07344928B2 Patterned-print thin-film transistors with top gate geometry 有权
标题翻译：具有顶栅几何形状的图案印刷薄膜晶体管
公开(公告)号：US07344928B2
公开(公告)日：2008-03-18
申请号：US11193847
申请日：2005-07-28
申请人： William S. Wong , Rene A. Lujan , Eugene M. Chow
发明人： William S. Wong , Rene A. Lujan , Eugene M. Chow
IPC分类号： H01L21/84
CPC分类号： H01L29/41733 , H01L27/124 , H01L27/1285 , H01L27/1288 , H01L27/1292 , H01L29/42384 , H01L29/4908 , H01L29/66757
摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.
摘要翻译：公开了一种自对准薄膜顶栅晶体管及其制造方法。通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。在其上形成半导体层和绝缘层。然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。在感光材料的显影之后，沉积栅极金属层。然后再次通过数字光刻法在器件上形成第二印刷图案掩模。蚀刻和去除感光材料离开自对准顶栅电极。

7. 发明申请

US20080121884A1 Patterned-Print Thin-Film Transistors with Top Gate Geometry 有权
标题翻译：带顶栅几何图案印刷薄膜晶体管
公开(公告)号：US20080121884A1
公开(公告)日：2008-05-29
申请号：US12018794
申请日：2008-01-23
申请人： William S. Wong , Rene A. Lujan , Eugene M. Chow
发明人： William S. Wong , Rene A. Lujan , Eugene M. Chow
IPC分类号： H01L29/04
CPC分类号： H01L29/41733 , H01L27/124 , H01L27/1285 , H01L27/1288 , H01L27/1292 , H01L29/42384 , H01L29/4908 , H01L29/66757
摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.
摘要翻译：公开了一种自对准薄膜顶栅晶体管及其制造方法。通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。在其上形成半导体层和绝缘层。然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。在感光材料的显影之后，沉积栅极金属层。然后再次通过数字光刻法在器件上形成第二印刷图案掩模。蚀刻和去除感光材料离开自对准顶栅电极。

8. 发明授权

US10066829B2 Electronic fabric 有权
公开(公告)号：US10066829B2
公开(公告)日：2018-09-04
申请号：US15139648
申请日：2016-04-27
申请人： William S. Wong , John S. Morreale
发明人： William S. Wong , John S. Morreale
IPC分类号： F21V33/00 , H05K1/03 , H05K1/18 , F21Y115/10 , F21Y107/70 , H05K1/11 , A41D27/08 , A41D1/00
摘要： An electronic fabric can include a first fabric layer, a second fabric layer, and a plurality of electronic devices. The first fabric layer can include a first set of conductive wires extending longitudinally in a first direction. The second fabric layer can define a plurality of apertures, can include a second set of conductive wires extending longitudinally in a second direction, and can be coupled to the first fabric layer such that each of the first set of conductive wires is arranged at a location of one of the plurality of apertures. Each electronic device can have a first terminal electrically coupled with one of the first set of conductive wires and a second terminal electrically coupled to one of the second set of conductive wires. The first terminal can be electrically coupled with the one of the first set of conductive wires through one of the plurality of apertures.

9. 发明授权

US08492876B2 Geometry and design for conformal electronics 有权
标题翻译：适形电子学的几何和设计
公开(公告)号：US08492876B2
公开(公告)日：2013-07-23
申请号：US12253390
申请日：2008-10-17
申请人： William S. Wong , Brent S. Krusor , Robert A. Street
发明人： William S. Wong , Brent S. Krusor , Robert A. Street
IPC分类号： H01L29/06
CPC分类号： H05K3/0044 , G02F2201/56 , H01L27/14603 , H01L27/14692 , H01L27/14812 , H01L29/78603
摘要： A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being located to allow the two-dimensional substrate to be shaped, the cuts having at least one stress relief feature, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure, the stress relief features arranged to alleviate stress in the three-dimensional structure. A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being arranged to as to increase a radius of curvature to meet a stress relief parameter when the substrate is shaped, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure. A three-dimensional electronic device having an electronic device formed on a flexible substrate, the flexible substrate formed into a three-dimensional structure, wedged-shaped portions removed from the substrate to allow the substrate to be formed into the three-dimensional structure, and a stress relief feature arranged adjacent to the wedge-shaped portions.
摘要翻译：形成三维电子器件的方法包括在二维柔性基板上形成至少一个电子器件，该电子器件根据三维结构形成，切割二维柔性基片，切割被设置成允许二维基底成形，切口具有至少一个应力消除特征，并且成形二维柔性基底以形成三维结构，应力消除特征被设置为减轻二维基底中的应力三维结构。形成三维电子器件的方法包括在二维柔性基板上形成至少一个电子器件，该电子器件根据三维结构形成，切割二维柔性基片，切割被布置成当基底成形时增加曲率半径以满足应力消除参数，并且将二维柔性基底成形以形成三维结构。一种具有形成在柔性基板上的电子器件的三维电子器件，形成为三维结构的柔性衬底，从衬底移除楔形部分以使衬底形成三维结构;以及紧邻楔形部分布置的应力消除特征。

10. 发明授权

US08411075B2 Large area electronic sheet and pixel circuits with disordered semiconductors for sensor actuator interface 有权
标题翻译：用于传感器执行器接口的大面积电子薄片和具有无序半导体的像素电路
公开(公告)号：US08411075B2
公开(公告)日：2013-04-02
申请号：US12206690
申请日：2008-09-08
申请人： Sanjiv Sambandan , William S. Wong , Robert A. Street
发明人： Sanjiv Sambandan , William S. Wong , Robert A. Street
IPC分类号： G06F3/038 , G06G5/00
CPC分类号： G06F3/038
摘要： A pixel circuit including a first transistor; a second transistor, the first transistor and the second transistor serially coupled between a first power supply terminal and a second power supply terminal; and a first capacitor coupled between a gate of the first transistor and a gate of the second transistor, and an electronic sheet including the same.
摘要翻译：一种像素电路，包括第一晶体管; 第二晶体管，第一晶体管和第二晶体管，串联耦合在第一电源端子和第二电源端子之间; 以及耦合在所述第一晶体管的栅极和所述第二晶体管的栅极之间的第一电容器以及包括所述第一晶体管的电子薄片。

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