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1. 发明授权

US07514114B2 Detecting defective ejector in digital lithography system 失效
标题翻译：在数字光刻系统中检测有缺陷的喷射器
公开(公告)号：US07514114B2
公开(公告)日：2009-04-07
申请号：US11218416
申请日：2005-09-01
申请人： William S. Wong , Steven E. Ready , Ana Claudia Arias
发明人： William S. Wong , Steven E. Ready , Ana Claudia Arias
IPC分类号： C23C16/52 , B05D5/12
CPC分类号： B41J29/393
摘要： A digital lithography system prints a large-area electronic device by dividing the overall device printing process into a series of discrete feature printing sub-processes, where each feature printing sub-process involves printing both a predetermined portion (feature) of the device in a designated substrate area, and an associated test pattern in a designated test area that is remote from the feature. At the end of each feature printing sub-process, the test pattern is analyzed, e.g., using a camera and associated imaging system, to verify that the test pattern has been successfully printed. A primary ejector is used until an unsuccessfully printed test pattern is detected, at which time a secondary (reserve) ejector replaces the primary ejector and reprints the feature associated with the defective test pattern. When multiple printheads are used in parallel, analysis of the test pattern is used to efficiently identify the location of a defective ejector.
摘要翻译：数字光刻系统通过将整个设备打印过程划分成一系列离散特征打印子过程来打印大面积电子设备，其中每个特征打印子过程涉及将设备的预定部分（特征）打印在一个指定的基板区域以及远离该特征的指定测试区域中的关联测试图案。在每个特征打印子过程结束时，分析测试图案，例如使用相机和相关联的成像系统来验证测试图案是否已被成功打印。使用初级喷射器，直到检测到未成功打印的测试图案，此时次要（预留）喷射器取代主喷射器并重印与缺陷测试图案相关的特征。当并行使用多个打印头时，使用测试图案的分析来有效地识别有缺陷的喷射器的位置。

2. 发明授权

US07964440B2 Phase-separated composite films and methods of preparing the same 有权
标题翻译：相分离复合膜及其制备方法
公开(公告)号：US07964440B2
公开(公告)日：2011-06-21
申请号：US11015795
申请日：2004-12-20
申请人： Alberto Salleo , Ana Claudia Arias , William S. Wong
发明人： Alberto Salleo , Ana Claudia Arias , William S. Wong
IPC分类号： H01L51/40
CPC分类号： B82Y30/00 , H01L27/28 , H01L51/0004 , H01L51/0015
摘要： Composite films formed from blends of semiconducting and insulating materials that phase separate on patterned substrates are provided. Phase separation provides isolated and encapsulated areas of semiconductor on the substrate. Processes for preparing and using such composite films are also provided, along with devices including such composite films.
摘要翻译：提供由在图案化衬底上相分离的半导体和绝缘材料的共混物形成的复合膜。相分离在衬底上提供隔离和封装的半导体区域。还提供了制备和使用这种复合膜的方法以及包括这种复合膜的装置。

3. 发明授权

US07524768B2 Method using monolayer etch masks in combination with printed masks 失效
标题翻译：使用单层蚀刻掩模与印刷掩模组合的方法
公开(公告)号：US07524768B2
公开(公告)日：2009-04-28
申请号：US11388718
申请日：2006-03-24
申请人： Eugene M. Chow , William S. Wong , Michael Chabinyc , Jeng Ping Lu , Ana Claudia Arias
发明人： Eugene M. Chow , William S. Wong , Michael Chabinyc , Jeng Ping Lu , Ana Claudia Arias
IPC分类号： H01L21/302
CPC分类号： H01L21/302 , H01L21/0271 , H01L21/0273 , H01L27/124 , H01L27/1288 , H01L27/1292 , H01L29/66765
摘要： A method to pattern films into dimensions smaller than the printed pixel mask size. A printed mask is deposited on a thin film on a substrate. The second mask layer is selectively deposited onto the film, but not to the printed mask. A third mask is then printed onto the substrate to pattern a portion of the second mask. Certain solvents are then used to remove the printed mask but not the mask layer on the thin film. The mask layer is then used to form a pattern on the thin film in combination with etching. The features formed in the thin film are smaller than the smallest dimension of the printed mask. The coated mask layer can be a self-assembled mono-layer or other material that selectively binds to the thin film.
摘要翻译：将薄膜图案尺寸小于印刷像素掩模尺寸的方法。印刷的掩模沉积在基底上的薄膜上。第二掩模层选择性地沉积在膜上，而不是印刷在掩模上。然后将第三掩模印刷到基底上以对第二掩模的一部分进行图案化。然后使用某些溶剂去除印刷的掩模，而不是薄膜上的掩模层。然后将掩模层与蚀刻结合在薄膜上形成图案。形成在薄膜中的特征小于印刷掩模的最小尺寸。涂覆的掩模层可以是选择性地结合薄膜的自组装单层或其它材料。

4. 发明授权

US07749396B2 Method of manufacturing fine features for thin film transistors 有权
标题翻译：制造薄膜晶体管精细特征的方法
公开(公告)号：US07749396B2
公开(公告)日：2010-07-06
申请号：US11388731
申请日：2006-03-24
申请人： Eugene M. Chow , William S. Wong , Michael Chabinyc , Ana Claudia Arias
发明人： Eugene M. Chow , William S. Wong , Michael Chabinyc , Ana Claudia Arias
IPC分类号： H01B13/00 , C23F1/00
CPC分类号： H01L29/4908 , H01L27/124 , H01L27/1292
摘要： A process for fabricating fine features such as small gate electrodes on a transistor. The process involves the jet-printing of a mask and the plating of a metal to fabricate sub-pixel and standard pixel size features in one layer. Printing creates a small sub-pixel size gap mask for plating a fine feature. A second printed mask may be used to protect the newly formed gate and etch standard pixel size lines connecting the small gates.
摘要翻译：一种在晶体管上制造诸如小栅电极的精细特征的工艺。该方法涉及一种掩模的喷墨印刷和金属镀层，以在一层中制造亚像素和标准像素尺寸特征。打印创建一个小的子像素大小的间隙掩模，用于电镀精细特征。可以使用第二印刷掩模来保护新形成的栅极并蚀刻连接小栅极的标准像素尺寸线。

5. 发明申请

US20120322214A1 METHOD AND STRUCTURE FOR ESTABLISHING CONTACTS IN THIN FILM TRANSISTOR DEVICES 有权
标题翻译：在薄膜晶体管器件中建立接触的方法和结构
公开(公告)号：US20120322214A1
公开(公告)日：2012-12-20
申请号：US13594507
申请日：2012-08-24
申请人： Jürgen H. Daniel , Ana Claudia Arias , Michael Chabinyc
发明人： Jürgen H. Daniel , Ana Claudia Arias , Michael Chabinyc
IPC分类号： H01L21/336
CPC分类号： H01L51/0558 , H01L29/1606 , H01L29/78684 , H01L29/7869 , H01L51/0003 , H01L51/0037 , H01L51/052 , H01L51/0541 , H01L51/0545 , H01L51/0562
摘要： The roughness and structural height of printed metal lines is used to pin a fluid. This fluid deposits a top contact material which is connected to the bottom printed contacts through pinholes in the hydrophobic polymer layer. This results in a sandwich-like contact structure achieved in a self-aligned deposition process and having improved source-drain contact for all-additive printed circuits. In one form, the present technique is used for thin film transistor applications, but it may be applied to electrodes in general.
摘要翻译：印刷金属线的粗糙度和结构高度用于固定流体。该流体通过疏水性聚合物层中的针孔沉积顶部接触材料，其通过针孔连接到底部印刷的触点。这导致在自对准沉积工艺中实现的夹层状接触结构，并且具有改进的用于全部添加印刷电路的源极 - 漏极接触。在一种形式中，本技术用于薄膜晶体管应用，但通常可以应用于电极。

6. 发明申请

US20120007079A1 Thin Film Field Effect Transistor with Dual Semiconductor Layers 有权
标题翻译：具有双半导体层的薄膜场效应晶体管
公开(公告)号：US20120007079A1
公开(公告)日：2012-01-12
申请号：US13239078
申请日：2011-09-21
申请人： Sanjiv Sambandan , Ana Claudia Arias , Gregory Lewis Whiting
发明人： Sanjiv Sambandan , Ana Claudia Arias , Gregory Lewis Whiting
IPC分类号： H01L29/04 , H01L29/786
CPC分类号： H01L29/78696 , H01L29/42384 , H01L29/78606 , H01L29/78645
摘要： A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is provided in a thin semiconductor layer closest to the gate terminal. An electric field is established in the thin semiconductor layer. At sufficient field strength, the electric field extends into the second semiconductor layer, which is in contact with the source and drain terminals. At sufficient field strength a channel is established in the second semiconductor layer, permitting current to flow between source and drain terminals. Above a certain gate voltage, there is sufficient free charge is induced in the first semiconductor layer so that the field does not extend into the second semiconductor, effectively shutting off current between source and drain. Single-device transition detection (as well as other applications) may be obtained.
摘要翻译：公开了薄膜场效应晶体管，其提供改进的基于时间的信道稳定性。场效应晶体管包括由绝缘体隔开的第一和第二无序半导体层。在一个实施例中，载流子注入端子设置在最靠近栅极端子的薄半导体层中。在薄半导体层中形成电场。在足够的场强下，电场延伸到与源极和漏极端子接触的第二半导体层。在足够的场强下，在第二半导体层中建立通道，允许电流在源极和漏极端子之间流动。在一定的栅极电压之上，在第一半导体层中感应出足够的自由电荷，使得场不延伸到第二半导体中，有效地关闭源极和漏极之间的电流。可以获得单器件转换检测（以及其他应用）。

7. 发明授权

US08049406B2 Optoelectronic devices and a method for producing the same 有权
标题翻译：光电器件及其制造方法
公开(公告)号：US08049406B2
公开(公告)日：2011-11-01
申请号：US10474814
申请日：2002-04-12
申请人： J. Devin Mackenzie , Ana Claudia Arias , Richard Henry Friend , Wilhelm Huck
发明人： J. Devin Mackenzie , Ana Claudia Arias , Richard Henry Friend , Wilhelm Huck
IPC分类号： C09K11/06 , H01L51/54
CPC分类号： H01L51/5088 , B82Y30/00 , H01L27/32 , H01L51/5012 , H01L51/5262 , Y10S428/917
摘要： A light-emissive device comprising a light-emissive material provided between first and second electrodes such that charge carriers can move between the first and second electrodes and the light-emissive material, wherein the device includes a layer of a polymer blend provided between the first and second electrodes, phase separation of the polymers in the polymer blend having been induced in at least a portion of the polymer blend so as to control the propagation of light emitted by the light-emissive material in a predetermined direction.
摘要翻译：一种发光装置，包括设置在第一和第二电极之间的发光材料，使得电荷载体可以在第一和第二电极与发光材料之间移动，其中该装置包括提供在第一和第二电极之间的聚合物共混物层和第二电极，聚合物共混物中的聚合物的相分离已经在聚合物共混物的至少一部分中被诱导，以便控制由发光材料在预定方向上发射的光的传播。

8. 发明申请

US20100148232A1 SURFACE TREATMENT OF HYDROPHOBIC FERROELECTRIC POLYMERS FOR PRINTING 有权
标题翻译：用于印刷的疏水性电解聚合物的表面处理
公开(公告)号：US20100148232A1
公开(公告)日：2010-06-17
申请号：US12334370
申请日：2008-12-12
申请人： Tse Nga Ng , Ana Claudia Arias , Jurgen H. Daniel
发明人： Tse Nga Ng , Ana Claudia Arias , Jurgen H. Daniel
IPC分类号： H01L23/48 , B05D5/12 , B05D3/06 , H01L29/66 , H01L21/02
CPC分类号： H01L51/0005 , H01L27/1292 , H01L27/283 , H01L51/0012 , H01L51/0022 , H01L51/0036 , H01L51/0043 , H01L51/052 , H01L51/0545 , H01L51/0558 , H05K3/1208 , H05K3/125 , H05K3/381 , H05K2203/013 , H05K2203/087 , H05K2203/095 , H05K2203/1173
摘要： An embodiment is a method and apparatus to treat surface of polymer for printing. Surface of a polymer having a surface energy modified for a time period to control a feature characteristic and/or provide a hysteresis behavior. A material is printed on the surface to form a circuit pattern having at least one of the controlled feature characteristic and the hysteresis behavior.
摘要翻译：一个实施方案是用于处理聚合物表面以进行印刷的方法和设备。具有表面能改变一段时间以控制特征特征和/或提供滞后行为的聚合物的表面。将材料印刷在表面上以形成具有受控特征特征和滞后特性中的至少一个的电路图案。

9. 发明申请

US20140094003A1 Printed Material Constrained By Well Structures And Devices Including Same 有权
标题翻译：由结构和包括相同的设备约束的打印材料
公开(公告)号：US20140094003A1
公开(公告)日：2014-04-03
申请号：US14094677
申请日：2013-12-02
申请人： Jurgen H. Daniel , Ana Claudia Arias
发明人： Jurgen H. Daniel , Ana Claudia Arias
IPC分类号： H01L29/66
CPC分类号： H01L21/02288 , H01L21/02488 , H01L21/02521 , H01L21/02623 , H01L21/02628 , H01L21/38 , H01L27/1292 , H01L29/66742 , H01L29/66772 , H01L29/78684 , H01L29/7869 , H01L51/0004
摘要： A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g., an operative transistor.
摘要翻译：第一图案化接触层，例如栅电极，形成在绝缘衬底上。至少在第一图案化接触层上形成绝缘层和功能层。在功能层上形成第二图案化接触层，例如源/漏电极。绝缘材料然后选择性地沉积在第二图案化接触层的至少一部分上以形成第一和第二壁结构，使得第二图案化接触层的至少一部分被暴露，第一和第二壁结构在其间限定了一个阱。导电或半导体材料例如通过喷墨印刷沉积在阱内，使得第一和第二壁结构限制导电或半导体材料并防止相邻器件的扩展和电短路。导电或半导体材料与第二图案化接触层的暴露部分电接触以形成例如有效晶体管。

10. 发明授权

US08624330B2 Thin film transistors and high fill factor pixel circuits and methods for forming same 有权
标题翻译：薄膜晶体管和高填充因子像素电路及其形成方法
公开(公告)号：US08624330B2
公开(公告)日：2014-01-07
申请号：US12324207
申请日：2008-11-26
申请人： Jurgen H. Daniel , Ana Claudia Arias
发明人： Jurgen H. Daniel , Ana Claudia Arias
IPC分类号： H01L29/66
CPC分类号： H01L29/51 , H01L29/786 , H01L51/0529
摘要： A method and structures to achieve improved TFTs and high fill-factor pixel circuits are provided. This system relies on the fact that jet-printed lines have print accuracy, which means the location and the definition of the printed lines and dots is high. The edge of a printed line is well defined if the printing conditions are optimized. This technique utilizes the accurate definition and placement of the edges of printed lines of conductors and insulators to define small features and improved structures.
摘要翻译：提供了一种实现改进的TFT和高填充因子像素电路的方法和结构。该系统依赖于喷墨印刷线具有打印精度的事实，这意味着打印线和点的位置和定义很高。如果打印条件得到优化，印刷线的边缘就被很好地定义。该技术利用导线和绝缘体的印刷线的边缘的精确定义和放置来定义小特征和改进的结构。

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