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1. 再颁专利

USRE40623E1 Method and apparatus for identifying integrated circuits 失效
标题翻译：用于识别集成电路的方法和装置
公开(公告)号：USRE40623E1
公开(公告)日：2009-01-20
申请号：US09998594
申请日：2001-11-16
申请人： Leland R. Nevill
发明人： Leland R. Nevill
IPC分类号： G06K19/06
CPC分类号： H01L23/544 , H01L2223/54413 , H01L2223/54473 , H01L2223/5448 , H01L2223/54486 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and method for identifying same is described. The integrated circuit includes a programmable identification circuit for storing electronic identification information. The integrated circuit also includes an optical identification mark displaying a machine-readable optical identification code which corresponds with the electronic identification information stored in the identification circuit. The data encoded in the optical identification code may be identical with that of the electronic identification information. Alternatively, a look-up table or other correlating means may be employed to associate the optical identification code with the electronic identification information. The integrated circuit is packaged in a housing, and another optical identification mark is placed on an external surface of the housing. This second optical identification mark displays a machine-readable optical identification code which is identical or correlated to the electronic identification information stored in the identification circuit and/or the optical identification code displayed by the optical identification mark on the integrated circuit. Consequently, convenient and traceable identification of individual integrated circuits is provided during and after manufacture.
摘要翻译：描述用于识别它的集成电路和方法。集成电路包括用于存储电子识别信息的可编程识别电路。集成电路还包括显示与存储在识别电路中的电子识别信息相对应的机器可读光学识别码的光学识别标记。在光学识别码中编码的数据可以与电子识别信息的数据相同。或者，可以使用查找表或其他相关装置来将光学识别码与电子识别信息相关联。集成电路封装在外壳中，另一个光学识别标记放置在外壳的外表面上。该第二光学识别标记显示与存储在识别电路中的电子识别信息和/或由集成电路上的光学识别标记显示的光学识别码相同或相关的机器可读光学识别码。因此，在制造期间和之后提供了单个集成电路的方便和可追踪的识别。

2. 发明授权

US07323896B2 Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer 失效
标题翻译：用于从半导体晶片上的其它IC隔离短路集成电路（IC）的装置和方法
公开(公告)号：US07323896B2
公开(公告)日：2008-01-29
申请号：US11607162
申请日：2006-12-01
申请人： Warren M. Farnworth , William K. Waller , Leland R. Nevill , Raymond J. Beffa , Eugene H. Cloud
发明人： Warren M. Farnworth , William K. Waller , Leland R. Nevill , Raymond J. Beffa , Eugene H. Cloud
IPC分类号： G01R31/26
CPC分类号： G01R31/025 , G01R31/2884
摘要： A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.
摘要翻译：用于将形成在半导体晶片的表面上的短路集成电路（IC）与形成在晶片上的与短路IC互连的其他IC隔离的电路包括用于感测短路IC的短路IC内的控制电路电路。控制电路可以以各种方式感测短路，包括感测由短路IC吸引的过电流，以及感测短路IC内的异常低或高电压。短路IC内的开关电路响应于控制电路感测短路而选择性地将短路IC与晶片上的其它IC隔离。结果，如果晶片处于探针测试之下，例如，在短路IC隔离的同时，其它IC上的测试可以不中断地继续。

3. 发明授权

US07315179B2 System for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer 失效
标题翻译：用于从半导体晶片上的其它IC隔离短路集成电路（IC）的系统
公开(公告)号：US07315179B2
公开(公告)日：2008-01-01
申请号：US11607272
申请日：2006-12-01
申请人： Warren M. Farnworth , William K. Waller , Leland R. Nevill , Raymond J. Beffa , Eugene H. Cloud
发明人： Warren M. Farnworth , William K. Waller , Leland R. Nevill , Raymond J. Beffa , Eugene H. Cloud
IPC分类号： G01R31/26
CPC分类号： G01R31/025 , G01R31/2884
摘要： A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.
摘要翻译：用于将形成在半导体晶片的表面上的短路集成电路（IC）与形成在晶片上的与短路IC互连的其他IC隔离的电路包括用于感测短路IC的短路IC内的控制电路电路。控制电路可以以各种方式感测短路，包括感测由短路IC吸引的过电流，以及感测短路IC内的异常低或高电压。短路IC内的开关电路响应于控制电路感测短路而选择性地将短路IC与晶片上的其它IC隔离。结果，如果晶片处于探针测试之下，例如，在短路IC隔离的同时，其它IC上的测试可以不中断地继续。

4. 发明授权

US06836003B2 Integrated circuit package alignment feature 失效
标题翻译：集成电路封装对准功能
公开(公告)号：US06836003B2
公开(公告)日：2004-12-28
申请号：US09819874
申请日：2001-03-28
申请人： David J. Corisis , Tracy Reynolds , Michael Slaughter , Daniel Cram , Leland R. Nevill , Jerrold L. King
发明人： David J. Corisis , Tracy Reynolds , Michael Slaughter , Daniel Cram , Leland R. Nevill , Jerrold L. King
IPC分类号： H01L23495
CPC分类号： G01R31/2851 , G01R1/0408 , G01R31/2884 , H01L23/4951 , H01L23/544 , H01L24/48 , H01L24/49 , H01L2223/54473 , H01L2223/54486 , H01L2224/05554 , H01L2224/05599 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/85399 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H05K3/303 , H05K2201/10568 , H05K2201/10689 , H05K2201/10696 , H05K2203/167 , Y02P70/613 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2924/00012
摘要： An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially encapsulated in insulating material. The lead frame has the alignment feature therein. The alignment feature includes a cut out on the lead frame taking the form of a semicircle, protuberance, apertures, or slots. Alternatively, the alignment feature includes a removably coupled tab. After testing of the integrated circuit has been completed, the alignment tab is removed from the integrated circuit. The alignment feature can also be provided on a heat spreader which is attached to a side of or within the lead frame package.
摘要翻译：提供了具有与引线框一体的对准特征的集成电路。集成电路包括与半导体管芯耦合的引线框架，并部分封装在绝缘材料中。引线框架具有其中的对准特征。对准特征包括在引线框架上切割出半圆形，突起，孔或槽的形式。或者，对准特征包括可移除地耦合的突片。集成电路测试完成后，对准标签从集成电路中取出。对准特征也可以设置在附着于引线框架封装的一侧或内部的散热器上。

5. 发明授权

US06420195B1 Method of aligning and testing a semiconductor chip package 有权
标题翻译：半导体芯片封装对准和测试方法
公开(公告)号：US06420195B1
公开(公告)日：2002-07-16
申请号：US09190545
申请日：1998-11-12
申请人： Jerrold L. King , Leland R. Nevill
发明人： Jerrold L. King , Leland R. Nevill
IPC分类号： G01R3126
CPC分类号： H05K3/303 , G01R31/2851 , G01R31/2884 , H05K2201/10568 , H05K2201/10689 , H05K2203/0195 , Y02P70/613
摘要： An improved semiconductor chip package capable of independently aligning with testing equipment during the manufacturing phase of electrical testing. Independent alignment is realized by directly connecting the semiconductor chip package to the test alignment apparatus by fitting together two substantially conforming surfaces, one on the chip package and one on the alignment apparatus. The conforming surfaces are arranged so that only one matable position is achievable. The substantially conforming surfaces equate to three substantially conical indentations on the chip package and three substantially hemispherical protrusions or protuberances of substantially conforming size and depth extending from the alignment apparatus. Once fitted, the three protrusions suspend the semiconductor chip in a substantially horizontal plane so that electrical test contacts, also substantially in a horizontal plane, may be easily contacted with the conductive leads extending generally horizontally and co-planar from the semiconductor chip.
摘要翻译：改进的半导体芯片封装，能够在电气测试制造阶段与测试设备独立对齐。通过将两个基本上一致的表面（一个在芯片封装上）和一个在对准装置上装配在一起，将半导体芯片封装直接连接到测试对准装置，实现独立对准。配合表面被布置成仅可实现一个可配合的位置。基本上一致的表面等于芯片封装上的三个基本上圆锥形的凹陷，以及从对准装置延伸的基本上一致的尺寸和深度的三个基本上半球形的突起或突起。一旦安装，三个突起将半导体芯片悬挂在基本上水平的平面中，使得电测试接触（也基本上在水平面）可以容易地与从半导体芯片大致水平并共面延伸的导电引线接触。

6. 发明授权

US06246108B1 Integrated circuit package including lead frame with electrically isolated alignment feature 有权
标题翻译：集成电路封装，包括带电隔离对准功能的引线框架
公开(公告)号：US06246108B1
公开(公告)日：2001-06-12
申请号：US09374176
申请日：1999-08-12
申请人： David J. Corisis , Tracy Reynolds , Michael Slaughter , Daniel Cram , Leland R. Nevill , Jerrold L. King
发明人： David J. Corisis , Tracy Reynolds , Michael Slaughter , Daniel Cram , Leland R. Nevill , Jerrold L. King
IPC分类号： H01L2348
CPC分类号： G01R31/2851 , G01R1/0408 , G01R31/2884 , H01L23/4951 , H01L23/544 , H01L24/48 , H01L24/49 , H01L2223/54473 , H01L2223/54486 , H01L2224/05554 , H01L2224/05599 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/85399 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H05K3/303 , H05K2201/10568 , H05K2201/10689 , H05K2201/10696 , H05K2203/167 , Y02P70/613 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2924/00012
摘要： An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially encapsulated in insulating material. The lead frame has the alignment feature therein. The alignment feature includes a cut out on the lead frame taking the form of a semi-circle, protuberance, apertures, or slots. Alternatively, the alignment feature includes a removably coupled tab. After testing of the integrated circuit has been completed, the alignment tab is removed from the integrated circuit. The alignment feature can also be provided on a heat spreader which is attached to a side of or within the lead frame package.
摘要翻译：提供了具有与引线框一体的对准特征的集成电路。集成电路包括与半导体管芯耦合的引线框架，并部分封装在绝缘材料中。引线框架具有其中的对准特征。对准特征包括在引线框架上切割成半圆形，突起，孔或槽的形式。或者，对准特征包括可移除地耦合的突片。集成电路测试完成后，对准标签从集成电路中取出。对准特征也可以设置在附着于引线框架封装的一侧或内部的散热器上。

7. 发明授权

US6048744A Integrated circuit package alignment feature 失效
标题翻译：集成电路封装对准功能
公开(公告)号：US6048744A
公开(公告)日：2000-04-11
申请号：US929843
申请日：1997-09-15
申请人： David J. Corisis , Tracy Reynolds , Michael Slaughter , Daniel Cram , Leland R. Nevill , Jerrold L. King
发明人： David J. Corisis , Tracy Reynolds , Michael Slaughter , Daniel Cram , Leland R. Nevill , Jerrold L. King
IPC分类号： G01R1/04 , G01R31/28 , H01L23/495 , H01L23/544 , H05K3/30 , G01R31/26 , H01L21/44 , H01L21/48 , H01L21/50 , H01L21/66
CPC分类号： G01R31/2851 , H01L23/4951 , H01L23/544 , H05K3/303 , G01R1/0408 , G01R31/2884 , H01L2223/54473 , H01L2223/54486 , H01L2224/05554 , H01L2224/05599 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/85399 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H05K2201/10568 , H05K2201/10689 , H05K2201/10696 , H05K2203/167 , Y02P70/613
摘要： An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially encapsulated in insulating material. The lead frame has the alignment feature therein. The alignment feature includes a cut out on the lead frame taking the form of a semi-circle, protuberance, apertures, or slots. Alternatively, the alignment feature includes a removably coupled tab. After testing of the integrated circuit has been completed, the alignment tab is removed from the integrated circuit. The alignment feature can also be provided on a heat spreader which is attached to a side of or within the lead frame package.
摘要翻译：提供了具有与引线框一体的对准特征的集成电路。集成电路包括与半导体管芯耦合的引线框架，并部分封装在绝缘材料中。引线框架具有其中的对准特征。对准特征包括在引线框架上切割成半圆形，突起，孔或槽的形式。或者，对准特征包括可移除地耦合的突片。集成电路测试完成后，对准标签从集成电路中取出。对准特征也可以设置在附着于引线框架封装的一侧或内部的散热器上。

8. 发明授权

US5982682A Self-test circuit for memory integrated circuits 失效
标题翻译：存储器集成电路自检电路
公开(公告)号：US5982682A
公开(公告)日：1999-11-09
申请号：US41859
申请日：1998-03-12
申请人： Leland R. Nevill , Ray Beffa , Warren M. Farnworth , Gene Cloud
发明人： Leland R. Nevill , Ray Beffa , Warren M. Farnworth , Gene Cloud
IPC分类号： G11C7/06 , G11C7/12 , G11C11/4091 , G11C11/4094 , G11C29/10 , G11C29/14 , G11C29/34 , G11C29/36 , G11C29/50 , G11C29/00
CPC分类号： G11C29/10 , G11C11/4091 , G11C11/4094 , G11C29/14 , G11C29/34 , G11C29/36 , G11C29/50 , G11C7/065 , G11C7/12 , G11C11/401
摘要： A sense amplifier senses and stores data from a memory cell in an array of memory cells arranged in rows and columns. The sense amplifier includes a sense circuit having a pair of first and second complementary digit lines which senses a voltage differential between the first and second complementary digit lines and in response to the sensed voltage differential drives the first and second complementary digit lines to voltage levels corresponding to complementary logic states. An isolation circuit is coupled between the pair of first and second complementary digit lines of the sense amplifier and a pair of first and second complementary digit lines associated with a column of memory cells. The isolation circuit is operable to couple the first complementary digit line of the sense amplifier to the first complementary digit line of the column of memory cells and the second complementary digit line of the sense amplifier to the secondary complementary digit line of the column of memory cells. A switch circuit is operable to couple the first complementary digit line of the sense amplifier to the second complementary digit line of the column of memory cells, and the second complementary digit line of the sense amplifier to the first complementary digit line of the column of memory cells. An equilibration circuit is coupled between the pair of complementary digit lines of the column of memory cells and is operable to equalize the voltage level on the digit lines to a predetermined level.
摘要翻译：读出放大器将存储单元中的数据传感并存储在以行和列排列的存储单元阵列中。感测放大器包括感测电路，该感测电路具有一对第一和第二互补数字线，其感测第一和第二互补数字线之间的电压差，并且响应于感测到的电压差将第一和第二互补数字线驱动到相应的电压电平互补逻辑状态。隔离电路耦合在读出放大器的一对第一和第二互补数字线之间，以及与一列存储器单元相关联的一对第一和第二互补数字线。隔离电路可操作以将读出放大器的第一互补数字线耦合到存储器单元列的第一互补数字线和读出放大器的第二互补数字线到存储器单元列的次互补数字线。开关电路可操作以将读出放大器的第一互补数字线耦合到存储器单元列的第二互补数字线，并将读出放大器的第二互补数字线耦合到存储器列的第一互补数字线细胞。平衡电路耦合在存储器单元列的一对互补数字线之间，并且可操作以将数字线上的电压电平均衡到预定电平。

9. 发明授权

US5935264A Method and apparatus for determining a set of tests for integrated circuit testing 失效
公开(公告)号：US5935264A
公开(公告)日：1999-08-10
申请号：US872240
申请日：1997-06-10
申请人： Leland R. Nevill , Than Huu Nguyen , Bruce J. Ford, Jr. , Gregory A. Barnett
发明人： Leland R. Nevill , Than Huu Nguyen , Bruce J. Ford, Jr. , Gregory A. Barnett
IPC分类号： G01R31/28 , G01R31/3183 , G01R31/319
CPC分类号： G01R31/31835 , G01R31/287 , G01R31/318307 , G01R31/319 , G01R31/31903
摘要： The present invention is directed to a system comprised of a computer, at least one integrated circuit tester, a communications link enabling communications between the integrated circuit tester and the computer, and a computer-readable medium. The computer-readable medium contains a sequence of instructions that, when executed, create a set of tests for integrated circuit testing. The set of tests may include only those tests that are calculated to be statistically significant. A second set of tests may be created that includes only those tests that are calculated to be statistically insignificant. The computer monitors the test results and moves tests between the two sets to ensure that only statistically significant tests are in the first group and that only statistically insignificant tests are in the second group.

10. 发明授权

US5903163A Apparatus and method of controlling the environmental temperature near semiconductor devices under test 失效
标题翻译：在被测试的半导体器件附近控制环境温度的设备和方法
公开(公告)号：US5903163A
公开(公告)日：1999-05-11
申请号：US773019
申请日：1996-12-24
申请人： Mark A. Tverdy , Leland R. Nevill
发明人： Mark A. Tverdy , Leland R. Nevill
IPC分类号： G01R31/28 , G01R31/26
CPC分类号： G01R31/2849
摘要： An apparatus and method for controlling the environmental conditions surrounding an integrated circuit device during performance testing is disclosed. The apparatus includes a housing having an inlet and outlet, a test assembly having a plurality of device test sites, a heat transfer medium source connected to the inlet, a negative pressure source connected to the outlet to promote flow of the heat transfer medium from the inlet to the outlet, and at least one flow resistance member positioned between the test sites and the outlet to control the flow of the heat transfer medium proximate to the test sites. In a preferred embodiment the flow resistance member is integral with the test assembly and the test sites have at least one flow path through each of the test sites serving as the flow resistance member and sized to provide for a uniform flow field in the vicinity of the test sites. In the practice of the invention, the resistance member is positioned such that upon the application of a negative pressure on the outlet of the housing a uniform flow and pressure field develops in the vicinity of the test sites and devices.
摘要翻译：公开了一种用于在性能测试期间控制集成电路器件周围的环境条件的装置和方法。该装置包括具有入口和出口的壳体，具有多个装置测试位置的测试组件，连接到入口的传热介质源，连接到出口的负压源，以促进传热介质从到出口的入口以及位于测试位置和出口之间的至少一个流动阻力构件，以控制靠近测试位置的传热介质的流动。在优选实施例中，流动阻力构件与测试组件成一体，并且测试位置具有至少一个通过每个测试位置的流动路径，用作流动阻力构件，并且其尺寸设置成在测试站点。在本发明的实践中，电阻构件被定位成使得当在壳体的出口上施加负压时，在测试位置和设备附近产生均匀的流动和压力场。

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