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1. 发明授权

US07160775B2 Method of discharging a semiconductor device 有权
标题翻译：放电半导体器件的方法
公开(公告)号：US07160775B2
公开(公告)日：2007-01-09
申请号：US10912825
申请日：2004-08-06
申请人： Erwin J. Prinz , Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Robert F. Steimle , Craig T. Swift , Bruce E. White
发明人： Erwin J. Prinz , Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Robert F. Steimle , Craig T. Swift , Bruce E. White
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , G11C16/0475 , G11C16/14 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332
摘要： In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.
摘要翻译：在一个实施例中，一种用于放电半导体器件的方法包括提供半导体衬底，在半导体衬底上形成空穴阻挡电介质层，在空穴阻挡介电层上形成纳米团簇，在纳米团簇上形成电荷俘获层，并施加电场到纳米团簇放电半导体器件。施加紫外线（UV）光时可能会发生电场。在一个实施例中，空穴阻挡介电层包括形成厚度大于约50埃的空穴阻挡介电层。

2. 发明授权

US06958265B2 Semiconductor device with nanoclusters 有权
标题翻译：具有纳米团簇的半导体器件
公开(公告)号：US06958265B2
公开(公告)日：2005-10-25
申请号：US10663621
申请日：2003-09-16
申请人： Robert F. Steimle , Ramachandran Muralidhar , Wayne M. Paulson , Rajesh A. Rao , Bruce E. White, Jr. , Erwin J. Prinz
发明人： Robert F. Steimle , Ramachandran Muralidhar , Wayne M. Paulson , Rajesh A. Rao , Bruce E. White, Jr. , Erwin J. Prinz
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/115 , H01L29/423
CPC分类号： B82Y10/00 , H01L21/28273 , H01L27/115 , H01L29/42332
摘要： A process of forming a device with nanoclusters. The process includes forming nanoclusters (e.g. silicon nanocrystals) and forming an oxidation barrier layer over the nanoclusters to inhibit oxidizing agents from oxidizing the nanoclusters during a subsequent formation of a dielectric of the device. At least a portion of the oxidation barrier layer is removed after the formation of the dielectric. In one example, the device is a memory wherein the nanoclusters are utilized as charge storage locations for charge storage transistors of the memory. In this example, the oxidation barrier layer protects the nanoclusters from oxidizing agents due to the formation of gate dielectric for high voltage transistors of the memory.
摘要翻译：用纳米团簇形成装置的方法。该方法包括形成纳米团簇（例如硅纳米晶体）并在纳米簇上形成氧化阻挡层，以在随后形成器件的电介质期间抑制氧化剂氧化纳米团簇。在形成电介质后，去除至少一部分氧化阻挡层。在一个示例中，该器件是其中纳米团簇用作存储器的电荷存储晶体管的电荷存储位置的存储器。在该实施例中，氧化阻挡层由于形成用于存储器的高压晶体管的栅极电介质而保护纳米团簇免受氧化剂的影响。

3. 发明授权

US07364969B2 Semiconductor fabrication process for integrating formation of embedded nonvolatile storage device with formation of multiple transistor device types 有权
标题翻译：用于集成嵌入式非易失性存储器件的形成与形成多个晶体管器件类型的半导体制造工艺
公开(公告)号：US07364969B2
公开(公告)日：2008-04-29
申请号：US11172728
申请日：2005-07-01
申请人： Erwin J. Prinz , Ramachandran Muralidhar
发明人： Erwin J. Prinz , Ramachandran Muralidhar
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , H01L21/823857 , Y10S438/962
摘要： A semiconductor fabrication process includes forming polysilicon nanocrystals on a tunnel oxide overlying a first region of a substrate. A second dielectric is deposited overlying the first region and a second region. Without providing any protective layer overlying the second dielectric in the first region, an additional thermal oxidation step is performed without oxidizing the nanocrystals. A gate electrode film is then deposited over the second dielectric and patterned to form first and second gate electrodes. The second dielectric may be an annealed, CVD oxide. The additional thermal oxidation may include forming by dry oxidation a third dielectric overlying a third region of the semiconductor substrate. The dry oxidation produces a interfacial silicon oxide underlying the second dielectric in the second region. An upper surface of a fourth region of the substrate may then be exposed and a fourth dielectric formed on the upper surface in the fourth region.
摘要翻译：半导体制造工艺包括在覆盖衬底的第一区域的隧道氧化物上形成多晶硅纳米晶体。沉积第二电介质覆盖在第一区域和第二区域上。在不提供覆盖第一区域中的第二电介质的任何保护层的情况下，进行额外的热氧化步骤而不氧化纳米晶体。然后将栅极电极膜沉积在第二电介质上并被图案化以形成第一和第二栅电极。第二电介质可以是退火的CVD氧化物。额外的热氧化可以包括通过干式氧化形成覆盖在半导体衬底的第三区域上的第三电介质。干燥氧化在第二区域中产生第二电介质下面的界面氧化硅。然后可以暴露基板的第四区域的上表面，并在第四区域的上表面上形成第四电介质。

4. 发明授权

US06791883B2 Program and erase in a thin film storage non-volatile memory 有权
标题翻译：在薄膜存储非易失性存储器中编程和擦除
公开(公告)号：US06791883B2
公开(公告)日：2004-09-14
申请号：US10178658
申请日：2002-06-24
申请人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
发明人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
IPC分类号： G11C1600
CPC分类号： G11C16/0466
摘要： A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.
摘要翻译：具有薄膜电介质存储元件的非易失性存储器通过热载流子注入（HCI）编程并通过隧道擦除。这种存储器的存储单元的典型结构是硅，氧化物，氮化物，氧化物和硅（SONOS）。热载波注入为SONOS提供相对快速的编程，而隧道提供擦除，避免了通常伴随热载流子注入进行编程的热孔擦除（HHE）类型擦除的困难。 HHE对电介质的破坏性更大，导致可靠性问题。 HHE还具有相对较窄的擦除区域，可能不完全匹配HCI编程的模式，从而导致不完整的擦除。隧道擦除有效地覆盖整个区域，所以不用担心不完全擦除。虽然隧道擦除比HHE慢，但擦除时间在系统操作中通常不如编程时间那么重要。

5. 发明授权

US06295229B1 Semiconductor device and method of operating it 有权
标题翻译：半导体器件及其操作方法
公开(公告)号：US06295229B1
公开(公告)日：2001-09-25
申请号：US09351742
申请日：1999-07-08
申请人： Kuo-Tung Chang , Erwin J. Prinz , Craig T. Swift
发明人： Kuo-Tung Chang , Erwin J. Prinz , Craig T. Swift
IPC分类号： G11C1604
CPC分类号： G11C16/0433 , G11C16/12
摘要： A semiconductor device (70) includes a memory cell having a select transistor (67) and a storage transistor (65) having a relatively uniform tunnel dielectric thickness under both the floating gate (651) of the storage transistor and the select gate (671) of the select transistor (67). The select transistor (67) is adjacent to the drain region (68) for the memory cell to nearly eliminate a drain disturb problem. During programming, the control gate (652) is at a negative potential, and the drain region (68) is at a positive potential. The drain potential is sufficiently low to not degrade the tunnel dielectric layer (42) of the select transistor (67). During erase, a positive potential is applied to the control gate (652). The relatively uniform tunnel dielectric layer (42) thickness of the select transistor (67) allows for a faster operating device by increasing the read current of the memory device.
摘要翻译：半导体器件（70）包括具有在存储晶体管的浮动栅极（651）和选择栅极（671）两者下具有相对均匀的隧道电介质厚度的选择晶体管（67）和存储晶体管（65）的存储单元，的选择晶体管（67）。选择晶体管（67）与用于存储单元的漏极区域（68）相邻，几乎消除了漏极干扰问题。在编程期间，控制栅极（652）处于负电位，漏区（68）处于正电位。漏极电位足够低以不降低选择晶体管（67）的隧道介电层（42）。在擦除期间，向控制栅极施加正电位（652）。选择晶体管（67）的相对均匀的隧道介电层（42）的厚度通过增加存储器件的读取电流而允许更快的操作器件。

6. 发明授权

US07732278B2 Split gate memory cell and method therefor 有权
标题翻译：分闸存储单元及其方法
公开(公告)号：US07732278B2
公开(公告)日：2010-06-08
申请号：US12254294
申请日：2008-10-20
申请人： Erwin J. Prinz , Michael A. Sadd , Robert F. Steimle
发明人： Erwin J. Prinz , Michael A. Sadd , Robert F. Steimle
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42328 , H01L29/42332
摘要： A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.
摘要翻译：分离栅极存储单元具有选择栅极，控制栅极和电荷存储结构。选择栅极包括位于控制栅极上方的第一部分和不位于控制栅极上方的第二部分。在一个示例中，选择栅极的第一部分具有与控制栅极的侧壁对齐并与电荷存储结构的侧壁对准的侧壁。在一个示例中，控制栅极具有p型导电性。在一个示例中，门可以通过热载流子注入操作来编程，并且可以通过隧道操作来擦除。

7. 发明申请

US20080261367A1 METHOD FOR PROCESS INTEGRATION OF NON-VOLATILE MEMORY CELL TRANSISTORS WITH TRANSISTORS OF ANOTHER TYPE 有权
标题翻译：非易失性存储单元晶体管与其他类型晶体管的集成方法
公开(公告)号：US20080261367A1
公开(公告)日：2008-10-23
申请号：US11738003
申请日：2007-04-20
申请人： Erwin J. Prinz , Mehul D. Shroff
发明人： Erwin J. Prinz , Mehul D. Shroff
IPC分类号： H01L21/8232
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11546 , H01L29/7833
摘要： A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method includes forming a gate dielectric layer on the HV and LV regions. A tunnel oxide layer is formed over the substrate in the NVM region and the gate dielectric in the HV and LV regions. A first polysilicon layer is formed over the tunnel dielectric layer and gate dielectric layer. The first polysilicon layer is patterned to form NVM floating gates. An ONO layer is formed over the first polysilicon layer. A single etch removal step is used to form gates for the HV transistors from the first polysilicon layer while removing the first polysilicon layer from the LV region.
摘要翻译：提供一种制造具有非易失性存储单元晶体管和另一种晶体管的半导体器件的方法。在该方法中，提供具有NVM区域，高电压（HV）区域和低电压（LV））区域的衬底。该方法包括在HV和LV区域上形成栅极电介质层。隧道氧化物层形成在NVM区域中的衬底上，HV和LV区域中的栅极电介质。第一多晶硅层形成在隧道介电层和栅介质层上。图案化第一多晶硅层以形成NVM浮动栅极。在第一多晶硅层上形成ONO层。单个蚀刻去除步骤用于从第一多晶硅层形成用于HV晶体管的栅极，同时从LV区域移除第一多晶硅层。

8. 发明授权

US06816414B1 Nonvolatile memory and method of making same 有权
标题翻译：非易失存储器及其制作方法
公开(公告)号：US06816414B1
公开(公告)日：2004-11-09
申请号：US10631142
申请日：2003-07-31
申请人： Erwin J. Prinz
发明人： Erwin J. Prinz
IPC分类号： G11C1604
CPC分类号： B82Y10/00 , G11C16/0425 , G11C16/0458 , G11C16/0491 , G11C16/14 , G11C2216/06 , H01L21/28273 , H01L29/42332 , H01L29/66825 , H01L29/7887
摘要： A method of discharging a charge storage location of a transistor of a non-volatile memory includes applying first and second voltages to a control gate and a well region, respectively, of the transistor. The first voltage is applied to the control gate of the transistor, wherein the control gate has at least a portion located adjacent to a select gate of the transistor. The transistor includes a charge storage location having nanoclusters disposed within dielectric material of a structure of the transistor located below the control gate. Lastly, a second voltage is applied to the well region located below the control gate. Applying the first voltage and the second voltage generates a voltage differential across the structure for discharging electrons from the nanoclusters of the charge storage location.

9. 发明授权

US5981340A Method of building an EPROM cell without drain disturb and reduced select gate resistance 失效
标题翻译：构建EPROM单元而无漏极干扰和降低选择栅极电阻的方法
公开(公告)号：US5981340A
公开(公告)日：1999-11-09
申请号：US939397
申请日：1997-09-29
申请人： Kuo-Tung Chang , Erwin J. Prinz , Craig T. Swift
发明人： Kuo-Tung Chang , Erwin J. Prinz , Craig T. Swift
IPC分类号： G11C16/04 , H01L27/115 , H01L21/336
CPC分类号： H01L27/115 , G11C16/0433
摘要： A semiconductor device (70) includes a memory cell having a select transistor (67) and a storage transistor (65) having a relatively uniform tunnel dielectric thickness under both the floating gate (651) of the storage transistor and the select gate (671) of the select transistor (67). The select transistor (67) is adjacent to the drain region (68) for the memory cell to nearly eliminate a drain disturb problem. During programming, the control gate (652) is at a negative potential, and the drain region (68) is at a positive potential. The drain potential is sufficiently low to not degrade the tunnel dielectric layer (42) of the select transistor (67). During erase, a positive potential is applied to the control gate (652). The relatively uniform tunnel dielectric layer (42) thickness of the select transistor (67) allows for a faster operating device by increasing the read current of the memory device.
摘要翻译：半导体器件（70）包括具有在存储晶体管的浮动栅极（651）和选择栅极（671）两者下具有相对均匀的隧道电介质厚度的选择晶体管（67）和存储晶体管（65）的存储单元，的选择晶体管（67）。选择晶体管（67）与用于存储单元的漏极区域（68）相邻，几乎消除了漏极干扰问题。在编程期间，控制栅极（652）处于负电位，漏区（68）处于正电位。漏极电位足够低以不降低选择晶体管（67）的隧道介电层（42）。在擦除期间，向控制栅极施加正电位（652）。选择晶体管（67）的相对均匀的隧道介电层（42）的厚度通过增加存储器件的读取电流而允许更快的操作器件。

10. 发明申请

US20100240156A1 METHOD FOR PROVIDING A NON-VOLATILE MEMORY 有权
标题翻译：提供非易失性存储器的方法
公开(公告)号：US20100240156A1
公开(公告)日：2010-09-23
申请号：US12405308
申请日：2009-03-17
申请人： Mohammed Suhail , Ko-Min Chang , Peter J. Kuhn , Erwin J. Prinz
发明人： Mohammed Suhail , Ko-Min Chang , Peter J. Kuhn , Erwin J. Prinz
IPC分类号： H01L21/66
CPC分类号： G11C29/06 , G11C16/04 , G11C29/50 , G11C29/50004 , G11C29/50016 , G11C2029/0403
摘要： Testing a non volatile memory by exposing the non volatile memory to particle radiation (e.g. xenon ions) to emulate memory cell damage due to data state changing events of a non volatile memory cell. After the exposing, the memory cells are subjected to tests and the results of the tests are used to develop reliability indications of the non volatile memory. Integrated circuits with non volatile memories of the same design are provided. Reliability representations of the integrated circuits can be made with respect to a number of data state charging events based on the exposure and subsequent tests.
摘要翻译：通过将非易失性存储器暴露于粒子辐射（例如氙离子）来测试非易失性存储器，以模拟由非易失性存储器单元的数据状态改变事件引起的存储器单元损坏。在曝光之后，对存储器单元进行测试，并且测试结果用于开发非易失性存储器的可靠性指示。提供了具有相同设计的非易失性存储器的集成电路。集成电路的可靠性表示可以基于曝光和随后的测试相对于多个数据状态充电事件进行。

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