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1. 发明授权

US6121164A Method for forming low compressive stress fluorinated ozone/TEOS oxide film 失效
标题翻译：形成低压应力氟化臭氧/ TEOS氧化膜的方法
公开(公告)号：US6121164A
公开(公告)日：2000-09-19
申请号：US957058
申请日：1997-10-24
申请人： Ellie Yieh , Xin Zhang , Bang Nguyen , Stuardo Robles , Peter Lee
发明人： Ellie Yieh , Xin Zhang , Bang Nguyen , Stuardo Robles , Peter Lee
IPC分类号： C23C16/40 , H01L21/316 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02131 , C23C16/402 , H01L21/02274 , H01L21/02362 , H01L21/31629
摘要： A method and apparatus for forming a halogen-doped silicon oxide film, preferably a fluorinated silicon glass (FSG) film, having compressive stress less than about -5.times.10.sup.8 dynes/cm.sup.2. In a specific embodiment, the FSG film is formed by a sub-atmospheric CVD thermal process at a pressure of between about 60-650 torr. The relatively thin film, besides having a low dielectric constant and good gap fill capability, has low compressive stress, and is particularly suitable for use as an intermetal (IMD) layer.
摘要翻译：用于形成压电应力小于约-5×10 8达因/ cm 2的卤素掺杂氧化硅膜，优选氟化硅玻璃（FSG）膜的方法和装置。在一个具体的实施方案中，FSG膜通过在大约60-650托之间的压力下的低于大气压的CVD热处理形成。除了具有低介电常数和良好的间隙填充能力之外，相对薄的膜具有低的压缩应力，并且特别适合用作金属间（IMD）层。

2. 发明授权

US06599574B1 Method and apparatus for forming a dielectric film using helium as a carrier gas 失效
标题翻译：使用氦气作为载气形成电介质膜的方法和装置
公开(公告)号：US06599574B1
公开(公告)日：2003-07-29
申请号：US08627631
申请日：1996-04-04
申请人： Ellie Yieh , Paul Gee , Li-Qun Xia , Francimar Campana , Shankar Venkataranan , Dana Tribula , Bang Nguyen
发明人： Ellie Yieh , Paul Gee , Li-Qun Xia , Francimar Campana , Shankar Venkataranan , Dana Tribula , Bang Nguyen
IPC分类号： C23C1600
CPC分类号： H01L21/02129 , C23C16/401 , H01L21/02271 , H01L21/02274 , H01L21/31625 , Y10S438/905 , Y10S438/906
摘要： The present invention relates to the deposition of dielectric layers, and more specifically to a method and apparatus for forming dielectric layers such as borophosphosilicate glass (BPSG) having improved film uniformity, higher deposition rate, superior gap fill/reflow capability, and smoother surface morphology. The method forms a dielectric layer with a process using helium carrier gas that produces substantially less downstream residue than conventional methods and apparatus, thereby reducing the need for chamber cleaning and increasing throughput of processed wafers. The present invention utilizes helium instead of nitrogen as carrier gas in a process for forming a dielectric layer such as BPSG to provide various unexpected benefits. According to one aspect, the present invention forms a dielectric film on a substrate, and prolongs a period between chamber cleanings in a system by using helium which produces substantially less downstream and upstream residue than a process using nitrogen. The method includes introducing a process gas containing silicon, oxygen, and first dopant atoms into the chamber; using helium as the carrier gas in the system; and processing more substrates between cleanings than a process using nitrogen as carrier gas. A further aspect of the invention includes annealing the dielectric films formed on the substrates at a lower temperature than required by the process using nitrogen as carrier gas.
摘要翻译：本发明涉及电介质层的沉积，更具体地涉及一种用于形成介电层的方法和装置，例如具有改进的膜均匀性，较高沉积速率，优异的间隙填充/回流能力和更平滑的表面形态的硼磷硅酸盐玻璃（BPSG）。该方法形成具有使用氦载气的方法的电介质层，其产生比常规方法和设备基本上更少的下游残留物，从而减少对室清洁的需要并增加处理的晶片的生产量。本发明在形成诸如BPSG的介电层的工艺中使用氦代替氮作为载气，以提供各种意想不到的好处。根据一个方面，本发明在衬底上形成介电膜，并且通过使用产生比使用氮的方法显着更少的下游和上游残留物的氦来延长系统中的室清洁之间的时间。该方法包括将含有硅，氧和第一掺杂剂原子的工艺气体引入室中; 使用氦气作为系统中的载气; 并且在清洗之前处理比使用氮气作为载气的工艺更多的衬底。本发明的另一方面包括在比使用氮作为载气的方法所要求的温度更低的温度下退火形成在基板上的电介质膜。

3. 发明授权

US6099647A Methods and apparatus for forming ultra-shallow doped regions using doped silicon oxide films 有权
标题翻译：使用掺杂氧化硅膜形成超浅掺杂区域的方法和装置
公开(公告)号：US6099647A
公开(公告)日：2000-08-08
申请号：US409763
申请日：1999-09-30
申请人： Ellie Yieh , Li-Qun Xia , Paul Gee , Bang Nguyen
发明人： Ellie Yieh , Li-Qun Xia , Paul Gee , Bang Nguyen
IPC分类号： C23C16/40 , C23C16/44 , C23C16/509 , C23C16/52 , H01L21/225 , H01L21/31 , H01L21/316 , H01L21/336 , H01L21/762 , C23C16/00
CPC分类号： C23C16/401 , C23C16/402 , C23C16/4405 , C23C16/4412 , C23C16/5096 , C23C16/52 , H01L21/02129 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/02301 , H01L21/02312 , H01L21/02315 , H01L21/0234 , H01L21/02362 , H01L21/2255 , H01L21/31625 , H01L21/76237 , H01L29/66575
摘要： The present invention provides systems, methods and apparatus for high temperature (at least about 500-800.degree. C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.
摘要翻译：本发明提供用于半导体晶片的高温（至少约500-800℃）处理的系统，方法和装置。本发明的系统，方法和装置允许多个工艺步骤在相同的腔室中原位进行，以减少总处理时间，并确保对高宽比装置的高质量处理。在同一个室内执行多个工艺步骤也可以增加工艺参数的控制并减少设备损坏。特别地，本发明可以提供用于形成具有厚度均匀性，良好间隙填充能力，高密度，低湿度和其它所需特性的介电膜的高温沉积，加热和有效清洁。

4. 发明授权

US5994209A Methods and apparatus for forming ultra-shallow doped regions using doped silicon oxide films 失效
公开(公告)号：US5994209A
公开(公告)日：1999-11-30
申请号：US748094
申请日：1996-11-13
申请人： Ellie Yieh , Li-Qun Xia , Paul Gee , Bang Nguyen
发明人： Ellie Yieh , Li-Qun Xia , Paul Gee , Bang Nguyen
IPC分类号： C23C16/40 , C23C16/44 , C23C16/509 , C23C16/52 , H01L21/225 , H01L21/31 , H01L21/316 , H01L21/336 , H01L21/762 , H01L21/24 , H01L21/40
CPC分类号： C23C16/401 , C23C16/402 , C23C16/4405 , C23C16/4412 , C23C16/5096 , C23C16/52 , H01L21/02129 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/02301 , H01L21/02312 , H01L21/02315 , H01L21/0234 , H01L21/02362 , H01L21/2255 , H01L21/31625 , H01L21/76237 , H01L29/66575
摘要： The present invention provides systems, methods and apparatus for high temperature (at least about 500-800.degree. C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.

5. 发明授权

US5356722A Method for depositing ozone/TEOS silicon oxide films of reduced surface sensitivity 失效
标题翻译：沉积表面灵敏度降低的臭氧/ TEOS氧化硅膜的方法
公开(公告)号：US5356722A
公开(公告)日：1994-10-18
申请号：US896296
申请日：1992-06-10
申请人： Bang Nguyen , Ellie Yieh , Maria Galiano
发明人： Bang Nguyen , Ellie Yieh , Maria Galiano
IPC分类号： H01L21/205 , C23C16/40 , C23C16/452 , H01L21/314 , H01L21/316 , C23C16/00
CPC分类号： H01L21/02164 , C23C16/402 , C23C16/452 , H01L21/02271 , H01L21/02304 , H01L21/3144 , H01L21/31612
摘要： A process for depositing void-free silicon oxide layers over stepped topography comprising depositing a first silicon oxide seed layer which is doped with nitrogen from a plasma of tetraethoxysilane and a nitrogen-containing gas, and depositing thereover a silicon oxide layer from a mixture of tetraethoxysilane, ozone and oxygen at low temperatures to produce a silicon oxide layer having improved properties.
摘要翻译：一种用于在阶梯形地貌上沉积无空隙氧化硅层的方法，包括从四乙氧基硅烷和含氮气体的等离子体中沉积氮掺杂的第一氧化硅晶种层，并从四乙氧基硅烷的混合物沉积氧化硅层，臭氧和氧在低温下产生具有改进性能的氧化硅层。

6. 发明授权

US06405232B1 Leading bit prediction with in-parallel correction 有权
标题翻译：带并行校正的前端位预测
公开(公告)号：US06405232B1
公开(公告)日：2002-06-11
申请号：US09377139
申请日：1999-08-19
申请人： Daniel W. Green , Atul Dhablania , Jeffrey A. Lohman , Bang Nguyen
发明人： Daniel W. Green , Atul Dhablania , Jeffrey A. Lohman , Bang Nguyen
IPC分类号： G06F9302
CPC分类号： G06F7/74 , G06F5/012 , G06F7/485
摘要： For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of adding or subtracting two floating point numbers. In one embodiment, the logic circuitry includes: (1) an adder that receives the two floating point numbers and, based on a received instruction, adds or subtracts the two floating point numbers to yield a denormal sum or difference thereof, (2) a leading bit predictor that receives the two floating point numbers and performs logic operations thereon to yield predictive shift data denoting an extent to which the denormal sum or difference is required to be shifted to normalize the denormal sum or difference, the predictive shift data subject to being erroneous and (3) predictor corrector logic that receives the two floating point numbers and performs logic operations thereon to yield shift compensation data denoting an extent to which the predictive shift is erroneous. The denormal sum or difference, predictive shift data and shift compensation data are providable to a shifter to allow the denormal sum or difference to be normalized.
摘要翻译：用于具有能够管理浮点符号的非规范化数字的浮点单元（FPU）的处理器，用于加上或减去两个浮点数的逻辑电路和方法。在一个实施例中，逻辑电路包括：（1）接收两个浮点数的加法器，并且基于接收到的指令，加或减两个浮点数以产生其异常和或差，（2）a 接收两个浮点数并执行其上的逻辑运算的前导位预测器产生预测移位数据，该预测移位数据表示需要将非正交求和或差异移位到正规化异常和/ 错误和（3）预测器校正器逻辑，其接收两个浮点数并执行其上的逻辑运算以产生表示预测偏移错误程度的移位补偿数据。可以向移位器提供反正态和或差，预测移位数据和移位补偿数据，以允许正则化的归一化或不均匀。

7. 发明申请

US20060288156A1 OSD deterministic object fragmentation optimization in a disc drive 有权
标题翻译： OSD驱动器中的OSD确定性对象碎片优化
公开(公告)号：US20060288156A1
公开(公告)日：2006-12-21
申请号：US11154307
申请日：2005-06-16
申请人： Wilson Fish , Bang Nguyen , Jack Mobley
发明人： Wilson Fish , Bang Nguyen , Jack Mobley
IPC分类号： G06F13/28
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0676 , G11B20/1217 , G11B27/329 , G11B2020/1267 , G11B2020/1295 , G11B2220/20 , G11B2220/2516
摘要： An apparatus comprises a storage medium, an arm for positioning a recording head adjacent to the storage medium, and a controller for receiving objects and for selecting blocks on the storage medium to be written by the recoding head based on information in the objects. A method for storing objects is also provided. In another aspect, the invention provides a method for writing data in data storage devices. The method comprises: receiving access commands for objects, selecting blocks on a storage medium to be written by a recording head based on information in the objects, and writing data from the objects to the selected blocks.
摘要翻译：一种装置包括存储介质，用于定位与存储介质相邻的记录头的臂，以及用于接收对象并根据对象中的信息从存储介质上选择要由记录头写入的块的控制器。还提供了一种用于存储对象的方法。另一方面，本发明提供一种在数据存储装置中写入数据的方法。该方法包括：基于对象中的信息，接收对象的访问命令，选择要由记录头写入的存储介质上的块，以及将数据从对象写入所选择的块。

8. 发明授权

US06757812B1 Leading bit prediction with in-parallel correction 有权
标题翻译：带并行校正的前端位预测
公开(公告)号：US06757812B1
公开(公告)日：2004-06-29
申请号：US10166415
申请日：2002-06-10
申请人： Daniel W. Green , Atul Dhablania , Jeffrey A. Lohman , Bang Nguyen
发明人： Daniel W. Green , Atul Dhablania , Jeffrey A. Lohman , Bang Nguyen
IPC分类号： G06F9302
CPC分类号： G06F7/74 , G06F5/012 , G06F7/485
摘要： For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of adding or subtracting two floating point numbers. In one embodiment, the logic circuitry includes: (1) an adder that receives the two floating point numbers and, based on a received instruction, adds or subtracts the two floating point numbers to yield a denormal sum or difference thereof, (2) a leading bit predictor that receives the two floating point numbers and performs logic operations thereon to yield predictive shift data denoting an extent to which the denormal sum or difference is required to be shifted to normalize the denormal sum or difference, the predictive shift data subject to being erroneous and (3) predictor corrector logic that receives the two floating point numbers and performs logic operations thereon to yield shift compensation data denoting an extent to which the predictive shift is erroneous. The denormal sum or difference, predictive shift data and shift compensation data are providable to a shifter to allow the denormal sum or difference to be normalized.
摘要翻译：用于具有能够管理浮点符号的非规范化数字的浮点单元（FPU）的处理器，用于加上或减去两个浮点数的逻辑电路和方法。在一个实施例中，逻辑电路包括：（1）接收两个浮点数的加法器，并且基于接收到的指令，加或减两个浮点数以产生其异常和或差，（2）a 接收两个浮点数并执行其上的逻辑运算的前导位预测器产生预测移位数据，该预测移位数据表示需要将非正交求和或差异移位到正规化异常和/ 错误和（3）预测器校正器逻辑，其接收两个浮点数并执行其上的逻辑运算以产生表示预测偏移错误程度的移位补偿数据。可以向移位器提供反正态和或差，预测移位数据和移位补偿数据，以允许正则化的归一化或不均匀。

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