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    • 1. 发明授权
    • Method and apparatus for forming a dielectric film using helium as a carrier gas
    • 使用氦气作为载气形成电介质膜的方法和装置
    • US06599574B1
    • 2003-07-29
    • US08627631
    • 1996-04-04
    • Ellie YiehPaul GeeLi-Qun XiaFrancimar CampanaShankar VenkatarananDana TribulaBang Nguyen
    • Ellie YiehPaul GeeLi-Qun XiaFrancimar CampanaShankar VenkatarananDana TribulaBang Nguyen
    • C23C1600
    • H01L21/02129C23C16/401H01L21/02271H01L21/02274H01L21/31625Y10S438/905Y10S438/906
    • The present invention relates to the deposition of dielectric layers, and more specifically to a method and apparatus for forming dielectric layers such as borophosphosilicate glass (BPSG) having improved film uniformity, higher deposition rate, superior gap fill/reflow capability, and smoother surface morphology. The method forms a dielectric layer with a process using helium carrier gas that produces substantially less downstream residue than conventional methods and apparatus, thereby reducing the need for chamber cleaning and increasing throughput of processed wafers. The present invention utilizes helium instead of nitrogen as carrier gas in a process for forming a dielectric layer such as BPSG to provide various unexpected benefits. According to one aspect, the present invention forms a dielectric film on a substrate, and prolongs a period between chamber cleanings in a system by using helium which produces substantially less downstream and upstream residue than a process using nitrogen. The method includes introducing a process gas containing silicon, oxygen, and first dopant atoms into the chamber; using helium as the carrier gas in the system; and processing more substrates between cleanings than a process using nitrogen as carrier gas. A further aspect of the invention includes annealing the dielectric films formed on the substrates at a lower temperature than required by the process using nitrogen as carrier gas.
    • 本发明涉及电介质层的沉积,更具体地涉及一种用于形成介电层的方法和装置,例如具有改进的膜均匀性,较高沉积速率,优异的间隙填充/回流能力和更平滑的表面形态的硼磷硅酸盐玻璃(BPSG) 。 该方法形成具有使用氦载气的方法的电介质层,其产生比常规方法和设备基本上更少的下游残留物,从而减少对室清洁的需要并增加处理的晶片的生产量。 本发明在形成诸如BPSG的介电层的工艺中使用氦代替氮作为载气,以提供各种意想不到的好处。 根据一个方面,本发明在衬底上形成介电膜,并且通过使用产生比使用氮的方法显着更少的下游和上游残留物的氦来延长系统中的室清洁之间的时间。 该方法包括将含有硅,氧和第一掺杂剂原子的工艺气体引入室中; 使用氦气作为系统中的载气; 并且在清洗之前处理比使用氮气作为载气的工艺更多的衬底。 本发明的另一方面包括在比使用氮作为载气的方法所要求的温度更低的温度下退火形成在基板上的电介质膜。
    • 6. 发明授权
    • Leading bit prediction with in-parallel correction
    • 带并行校正的前端位预测
    • US06405232B1
    • 2002-06-11
    • US09377139
    • 1999-08-19
    • Daniel W. GreenAtul DhablaniaJeffrey A. LohmanBang Nguyen
    • Daniel W. GreenAtul DhablaniaJeffrey A. LohmanBang Nguyen
    • G06F9302
    • G06F7/74G06F5/012G06F7/485
    • For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of adding or subtracting two floating point numbers. In one embodiment, the logic circuitry includes: (1) an adder that receives the two floating point numbers and, based on a received instruction, adds or subtracts the two floating point numbers to yield a denormal sum or difference thereof, (2) a leading bit predictor that receives the two floating point numbers and performs logic operations thereon to yield predictive shift data denoting an extent to which the denormal sum or difference is required to be shifted to normalize the denormal sum or difference, the predictive shift data subject to being erroneous and (3) predictor corrector logic that receives the two floating point numbers and performs logic operations thereon to yield shift compensation data denoting an extent to which the predictive shift is erroneous. The denormal sum or difference, predictive shift data and shift compensation data are providable to a shifter to allow the denormal sum or difference to be normalized.
    • 用于具有能够管理浮点符号的非规范化数字的浮点单元(FPU)的处理器,用于加上或减去两个浮点数的逻辑电路和方法。 在一个实施例中,逻辑电路包括:(1)接收两个浮点数的加法器,并且基于接收到的指令,加或减两个浮点数以产生其异常和或差,(2)a 接收两个浮点数并执行其上的逻辑运算的前导位预测器产生预测移位数据,该预测移位数据表示需要将非正交求和或差异移位到正规化异常和/ 错误和(3)预测器校正器逻辑,其接收两个浮点数并执行其上的逻辑运算以产生表示预测偏移错误程度的移位补偿数据。 可以向移位器提供反正态和或差,预测移位数据和移位补偿数据,以允许正则化的归一化或不均匀。
    • 7. 发明授权
    • Leading bit prediction with in-parallel correction
    • 带并行校正的前端位预测
    • US06757812B1
    • 2004-06-29
    • US10166415
    • 2002-06-10
    • Daniel W. GreenAtul DhablaniaJeffrey A. LohmanBang Nguyen
    • Daniel W. GreenAtul DhablaniaJeffrey A. LohmanBang Nguyen
    • G06F9302
    • G06F7/74G06F5/012G06F7/485
    • For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of adding or subtracting two floating point numbers. In one embodiment, the logic circuitry includes: (1) an adder that receives the two floating point numbers and, based on a received instruction, adds or subtracts the two floating point numbers to yield a denormal sum or difference thereof, (2) a leading bit predictor that receives the two floating point numbers and performs logic operations thereon to yield predictive shift data denoting an extent to which the denormal sum or difference is required to be shifted to normalize the denormal sum or difference, the predictive shift data subject to being erroneous and (3) predictor corrector logic that receives the two floating point numbers and performs logic operations thereon to yield shift compensation data denoting an extent to which the predictive shift is erroneous. The denormal sum or difference, predictive shift data and shift compensation data are providable to a shifter to allow the denormal sum or difference to be normalized.
    • 用于具有能够管理浮点符号的非规范化数字的浮点单元(FPU)的处理器,用于加上或减去两个浮点数的逻辑电路和方法。 在一个实施例中,逻辑电路包括:(1)接收两个浮点数的加法器,并且基于接收到的指令,加或减两个浮点数以产生其异常和或差,(2)a 接收两个浮点数并执行其上的逻辑运算的前导位预测器产生预测移位数据,该预测移位数据表示需要将非正交求和或差异移位到正规化异常和/ 错误和(3)预测器校正器逻辑,其接收两个浮点数并执行其上的逻辑运算以产生表示预测偏移错误程度的移位补偿数据。 可以向移位器提供反正态和或差,预测移位数据和移位补偿数据,以允许正则化的归一化或不均匀。