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1. 发明授权

US07491342B2 Bonded semiconductor substrate manufacturing method thereof 有权
标题翻译：其半导体衬底的制造方法
公开(公告)号：US07491342B2
公开(公告)日：2009-02-17
申请号：US10550761
申请日：2004-04-02
申请人： Eiji Kamiyama , Takeo Katoh , Jea Gun Park
发明人： Eiji Kamiyama , Takeo Katoh , Jea Gun Park
IPC分类号： B44C1/22 , C03C15/00 , C03C25/68 , H01L21/30 , H01L21/46
CPC分类号： H01L21/30608 , H01L21/76254
摘要： The present invention provides a bonded substrate fabricated to have its final active layer thickness of 200 nm or lower by performing the etching by only 1 nm to 1 μm with a solution having an etching effect on a surface of an active layer of a bonded substrate which has been prepared by bonding two substrates after one of them having been ion-implanted and then cleaving off a portion thereof by heat treatment. SC-1 solution is used for performing the etching. A polishing, a hydrogen annealing and a sacrificial oxidation may be respectively applied to the active layer before and/or after the etching. The film thickness of this active layer can be made uniform over the entire surface area and the surface roughness of the active layer can be reduced as well.
摘要翻译：本发明提供了一种键合衬底，其通过用键合衬底的有源层的表面上具有蚀刻效果的溶液进行仅1nm至1μm的蚀刻而使其最终有源层厚度为200nm以下的结合衬底，已经通过在其中一个被离子注入之后将两个基板接合，然后通过热处理来分离其一部分来制备。 SC-1溶液用于进行蚀刻。在蚀刻之前和/或之后，可以在有源层上分别施加抛光，氢退火和牺牲氧化。该有源层的膜厚度可以在整个表面积上均匀，并且活性层的表面粗糙度也可以降低。

2. 发明申请

US20060118935A1 Laminated semiconductor substrate process for producing the same 有权
标题翻译：用于制造其的层叠半导体衬底工艺
公开(公告)号：US20060118935A1
公开(公告)日：2006-06-08
申请号：US10550761
申请日：2004-04-02
申请人： Eiji Kamiyama , Takeo Katoh , Jea Park
发明人： Eiji Kamiyama , Takeo Katoh , Jea Park
IPC分类号： H01L21/30 , H01L23/06
CPC分类号： H01L21/30608 , H01L21/76254
摘要： The present invention provides a bonded substrate fabricated to have its final active layer thickness of 200 nm or lower by performing the etching by only 1 nm to 1 μm with a solution having an etching effect on a surface of an active layer of a bonded substrate which has been prepared by bonding two substrates after one of them having been ion-implanted and then cleaving off a portion thereof by heat treatment. SC-1 solution is used for performing the etching. A polishing, a hydrogen annealing and a sacrificial oxidation may be respectively applied to the active layer before and/or after the etching. The film thickness of this active layer can be made uniform over the entire surface area and the surface roughness of the active layer can be reduced as well.
摘要翻译：本发明提供了一种键合衬底，其通过用键合衬底的有源层的表面上具有蚀刻效果的溶液进行仅1nm至1μm的蚀刻而使其最终有源层厚度为200nm以下的结合衬底，已经通过在其中一个被离子注入之后将两个基板接合，然后通过热处理来分离其一部分来制备。 SC-1溶液用于进行蚀刻。在蚀刻之前和/或之后，可以在有源层上分别施加抛光，氢退火和牺牲氧化。该有源层的膜厚度可以在整个表面积上均匀，并且活性层的表面粗糙度也可以降低。

3. 发明授权

US08379196B2 Method for judging whether semiconductor wafer is non-defective wafer by using laser scattering method 有权
标题翻译：通过使用激光散射法判断半导体晶片是否为缺陷晶片的方法
公开(公告)号：US08379196B2
公开(公告)日：2013-02-19
申请号：US12792148
申请日：2010-06-02
申请人： Eiji Kamiyama , Takashi Nakayama , Takeo Katoh
发明人： Eiji Kamiyama , Takashi Nakayama , Takeo Katoh
IPC分类号： G01N21/00
CPC分类号： G01N21/9501
摘要： A semiconductor wafer whose number of LPDs per wafer is equal to or smaller than a predetermined number is sorted out, and a judgment as to whether a semiconductor wafer is a non-defective wafer is made visually based on a haze map of the semiconductor wafer subjected to the sorting. Moreover, a semiconductor wafer whose number of LPDs per wafer is equal to or smaller than a predetermined number is sorted out. Then, from the semiconductor wafers subjected to the sorting, a semiconductor wafer whose in-plane standard deviation and in-plane average value of the haze signals in a wafer plane have a specific relationship is sorted out, and this semiconductor wafer is judged to be a non-defective wafer. In this way, a method for judging whether a semiconductor wafer is a non-defective wafer or a defective wafer, the method that can make a judgment more uniform and accurate without dependence on the difference in the S/N ratio between inspection apparatuses using a laser scattering method, is provided.
摘要翻译：对每个晶片的LPD的数量等于或小于预定数量的半导体晶片进行整理，并且根据半导体晶片的雾度图来视觉地判断半导体晶片是否为非缺陷晶片到排序。此外，整理出每个晶片的LPD的数量等于或小于预定数量的半导体晶片。然后，从进行分选的半导体晶片中，将晶片面内的雾度信号的面内标准偏差和面内平均值具有特定关系的半导体晶片整理出来，将该半导体晶片判定为无缺陷晶片。以这种方式，用于判断半导体晶片是否为缺陷晶片或缺陷晶片的方法，可以使得判断更均匀和准确而不依赖于使用a的检查装置之间的S / N比的差异的方法提供激光散射法。

4. 发明申请

US20100309461A1 METHOD FOR JUDGING WHETHER SEMICONDUCTOR WAFER IS NON-DEFECTIVE WAFER BY USING LASER SCATTERING METHOD 有权
标题翻译：通过使用激光散射方法判断半导体波形是非缺陷波形的方法
公开(公告)号：US20100309461A1
公开(公告)日：2010-12-09
申请号：US12792148
申请日：2010-06-02
申请人： Eiji Kamiyama , Takashi Nakayama , Takeo Katoh
发明人： Eiji Kamiyama , Takashi Nakayama , Takeo Katoh
IPC分类号： G01N21/00
CPC分类号： G01N21/9501
摘要： A semiconductor wafer whose number of LPDs per wafer is equal to or smaller than a predetermined number is sorted out, and a judgment as to whether a semiconductor wafer is a non-defective wafer is made visually based on a haze map of the semiconductor wafer subjected to the sorting. Moreover, a semiconductor wafer whose number of LPDs per wafer is equal to or smaller than a predetermined number is sorted out. Then, from the semiconductor wafers subjected to the sorting, a semiconductor wafer whose in-plane standard deviation and in-plane average value of the haze signals in a wafer plane have a specific relationship is sorted out, and this semiconductor wafer is judged to be a non-defective wafer. In this way, a method for judging whether a semiconductor wafer is a non-defective wafer or a defective wafer, the method that can make a judgment more uniform and accurate without dependence on the difference in the S/N ratio between inspection apparatuses using a laser scattering method, is provided.
摘要翻译：对每个晶片的LPD的数量等于或小于预定数量的半导体晶片进行整理，并且根据半导体晶片的雾度图来视觉地判断半导体晶片是否为非缺陷晶片到排序。此外，整理出每个晶片的LPD的数量等于或小于预定数量的半导体晶片。然后，从进行分选的半导体晶片中，将晶片面内的雾度信号的面内标准偏差和面内平均值具有特定关系的半导体晶片整理出来，将该半导体晶片判定为无缺陷晶片。以这种方式，用于判断半导体晶片是否为缺陷晶片或缺陷晶片的方法，可以使得判断更均匀和准确而不依赖于使用a的检查装置之间的S / N比的差异的方法提供激光散射法。

5. 发明申请

US20050242396A1 SOI structure having a sige layer interposed between the silicon and the insulator 有权
标题翻译：具有介于硅和绝缘体之间的奇特层的SOI结构
公开(公告)号：US20050242396A1
公开(公告)日：2005-11-03
申请号：US11150292
申请日：2005-06-13
申请人： Jeagun Park , Kenji Tomizawa , Gonsub Lee , Eiji Kamiyama
发明人： Jeagun Park , Kenji Tomizawa , Gonsub Lee , Eiji Kamiyama
IPC分类号： H01L21/336 , H01L21/762 , H01L29/786 , H01L27/01
CPC分类号： H01L29/66772 , H01L21/76243 , H01L21/76254 , H01L21/76259 , H01L29/78687
摘要： A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.
摘要翻译：一种半导体结构以及在硅与绝缘体之间插入硅锗（SiGe）层的绝缘体上硅（SOI）结构的制造方法。根据一种制造方法，在第一衬底上依次外延生长第一SiGe层，硅层和第二SiGe层，然后在第二SiGe层上形成绝缘层。然后，将杂质离子注入位于第一SiGe层下面的第一衬底的预定位置以形成杂质注入区。第二基板结合到第一基板上的绝缘层。在沿着杂质注入区域分离第一衬底并除去之后，去除残留在分离区域表面上的第一SiGe层，以使硅层的表面露出。

6. 发明申请

US20110194753A1 IMAGE DATA PROCESSING METHOD AND IMAGE CREATING METHOD 有权
标题翻译：图像数据处理方法和图像创建方法
公开(公告)号：US20110194753A1
公开(公告)日：2011-08-11
申请号：US13022062
申请日：2011-02-07
申请人： Eiji Kamiyama , Shin Uchino
发明人： Eiji Kamiyama , Shin Uchino
IPC分类号： G06K9/00
CPC分类号： G06T5/002 , G01N21/8851 , G01N21/9501 , G01N2021/8864 , G06T2207/10004 , G06T2207/30148
摘要： [Problem] Provided is a method of processing image data capable of, at the time of measuring a wafer in a circumferential direction thereof using a surface inspection device employing a laser scattering method to create a Haze map, reducing or removing occurrence of a noise resulting from change in detection sensitivity of the device. Further, provided is a method of creating an image by using the method of processing an image data.[Solving Means] There is provided a method of processing image data, including the steps of: measuring a haze value corresponding to each position on a wafer surface by using a wafer surface inspection device; and, subjecting image data formed by the haze value corresponding to each position on the wafer surface to an image data process along a direction in which the haze value is measured, to remove a noise component. Further, there is provided a method of creating an image, in which a Haze map after the image data process is created using the image data processed through the method of processing the image data.
摘要翻译： [问题]提供一种处理图像数据的方法，该图像数据能够使用采用激光散射法的表面检查装置在圆周方向上测量晶片以产生雾度图，从而减少或消除所产生的噪声的发生从设备的检测灵敏度的变化。此外，提供了通过使用处理图像数据的方法来创建图像的方法。提供一种处理图像数据的方法，包括以下步骤：通过使用晶片表面检查装置测量与晶片表面上的每个位置相对应的雾度值; 并且将对应于晶片表面上的每个位置的雾度值形成的图像数据沿着测量雾度值的方向进行图像数据处理，以消除噪声分量。此外，提供了一种创建图像的方法，其中使用通过处理图像数据的方法处理的图像数据来创建图像数据处理之后的雾度图。

7. 发明申请

US20100221877A1 METHOD OF MANUFACTURING A SOI STRUCTURE HAVING A SIGE LAYER INTERPOSED BETWEEN THE SILICON AND THE INSULATOR 有权
标题翻译：制造具有硅和绝缘体之间的信号层的SOI结构的方法
公开(公告)号：US20100221877A1
公开(公告)日：2010-09-02
申请号：US12759480
申请日：2010-04-13
申请人： Jeagun Park , Kenji Tomizawa , Gonsub Lee , Eiji Kamiyama
发明人： Jeagun Park , Kenji Tomizawa , Gonsub Lee , Eiji Kamiyama
IPC分类号： H01L21/762
CPC分类号： H01L29/66772 , H01L21/76243 , H01L21/76254 , H01L21/76259 , H01L29/78687
摘要： A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.
摘要翻译：一种半导体结构以及在硅与绝缘体之间插入硅锗（SiGe）层的绝缘体上硅（SOI）结构的制造方法。根据一种制造方法，在第一衬底上依次外延生长第一SiGe层，硅层和第二SiGe层，然后在第二SiGe层上形成绝缘层。然后，将杂质离子注入位于第一SiGe层下面的第一衬底的预定位置以形成杂质注入区。第二基板结合到第一基板上的绝缘层。在沿着杂质注入区域分离第一衬底并去除之后，去除残留在分离区域表面上的第一SiGe层，以使硅层的表面露出。

8. 发明申请

US20080213989A1 SILICON WAFER FOR MANUFACTURING SOI WAFER, SOI WAFER, AND METHOD FOR MANUFACTURING SOI WAFER 失效
标题翻译：用于制造SOI波形的硅波形，SOI波形和制造SOI波形的方法
公开(公告)号：US20080213989A1
公开(公告)日：2008-09-04
申请号：US12118928
申请日：2008-05-12
申请人： Eiji Kamiyama , Seiichi Nakamura , Tetsuya Nakai
发明人： Eiji Kamiyama , Seiichi Nakamura , Tetsuya Nakai
IPC分类号： H01L21/425
CPC分类号： H01L21/76243 , Y10S438/978
摘要： A silicon wafer includes a principal face for forming electronic devices; an end region; and a tapered region which is located between the principal face and the end region, in which the thickness of the silicon wafer is gradually reduced, and which has a slope that makes an angle of greater than zero degree and less than 9.5 degrees or an angle of greater than 19 degrees with the principal face. An SOI wafer prepared by forming a buried oxide layer in a silicon wafer includes a principal face, end region, and tapered region that are substantially the same as those described above. A method for manufacturing an SOI wafer includes the steps of implanting oxygen ions into a silicon wafer; and heat-treating the resulting silicon wafer such that a buried oxide layer is formed in the silicon wafer.
摘要翻译：硅晶片包括用于形成电子器件的主面; 末端区域以及位于主面和端部区域之间的锥形区域，其中硅晶片的厚度逐渐减小，并且具有大于零度且小于9.5度的角度的倾斜度或角度与主面大于19度。通过在硅晶片中形成掩埋氧化物层制备的SOI晶片包括与上述基本相同的主面，端部区域和锥形区域。一种制造SOI晶片的方法包括将氧离子注入到硅晶片中的步骤; 并对所得到的硅晶片进行热处理，使得在硅晶片中形成掩埋氧化物层。

9. 发明申请

US20070228522A1 SOI substrate, silicon substrate therefor and it's manufacturing method 有权
标题翻译： SOI衬底，硅衬底及其制造方法
公开(公告)号：US20070228522A1
公开(公告)日：2007-10-04
申请号：US11331216
申请日：2006-01-13
申请人： Eiji Kamiyama
发明人： Eiji Kamiyama
IPC分类号： H01L21/425
CPC分类号： H01L21/76243
摘要： A silicon wafer includes a principal face for forming electronic devices; an end region; and a tapered region which is located between the principal face and the end region, in which the thickness of the silicon wafer is gradually reduced, and which has a slope that makes an angle of greater than zero degree and less than 9.5 degrees or an angle of greater than 19 degrees with the principal face. An SOI wafer prepared by forming a buried oxide layer in a silicon wafer includes a principal face, end region, and tapered region that are substantially the same as those described above. A method for manufacturing an SOI wafer includes the steps of implanting oxygen ions into a silicon wafer; and heat-treating the resulting silicon wafer such that a buried oxide layer is formed in the silicon wafer.
摘要翻译：硅晶片包括用于形成电子器件的主面; 末端区域以及位于主面和端部区域之间的锥形区域，其中硅晶片的厚度逐渐减小，并且具有大于零度且小于9.5度的角度的倾斜度或角度与主面大于19度。通过在硅晶片中形成掩埋氧化物层制备的SOI晶片包括与上述基本相同的主面，端部区域和锥形区域。一种制造SOI晶片的方法包括将氧离子注入到硅晶片中的步骤; 并对所得到的硅晶片进行热处理，使得在硅晶片中形成掩埋氧化物层。

10. 发明授权

US5597744A Method of producing a silicon carbide semiconductor device 失效
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：US5597744A
公开(公告)日：1997-01-28
申请号：US516298
申请日：1995-08-17
申请人： Eiji Kamiyama , Kazuhiro Fusegawa , Nosho Toyama
发明人： Eiji Kamiyama , Kazuhiro Fusegawa , Nosho Toyama
IPC分类号： H01L21/04 , H01L29/45 , H01L21/265
CPC分类号： H01L29/66068 , H01L21/0485 , H01L29/45 , Y10S148/148 , Y10S438/931
摘要： Electrodes 16a and 16b composed of metal nitride made of either one of TiN, ZrN, HfN, VN and TaN are formed on an N-type source region 12 and drain region 13 of a P-type SiC substrate 11, respectively, Nitrogen-rich layers 12a and 13a are formed in surface layer portions of the regions 12 and 13 which the electrodes composed of metal nitride 16a and 16b contact respectively. The nitrogen-rich layer allows the contact resistivity of the electrode to be made small, A metal nitride composed of either one of TiN, ZrN, HfN, VN and TaN is interposed between a gate electrode 15 of Mo and an interconnection of Al 17c to prevent the reaction of the gate electrode and the interconnection.
摘要翻译：分别在P型SiC基板11的N型源极区域12和漏极区域13上形成由TiN，ZrN，HfN，VN和TaN中的任一种构成的金属氮化物构成的电极16a和16b，富氮层12a和13a形成在由金属氮化物16a和16b组成的电极分别接触的区域12和13的表层部分中。富氮层允许电极的接触电阻小，由TiN，ZrN，HfN，VN和TaN中的任一种构成的金属氮化物插入在Mo的栅电极15和Al 17c的互连与防止栅电极与互连的反应。

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