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1. 发明申请

US20130028011A1 MAGNETORESISTIVE DEVICE AND MAGNETIC MEMORY 有权
标题翻译：磁性器件和磁性存储器
公开(公告)号：US20130028011A1
公开(公告)日：2013-01-31
申请号：US13424769
申请日：2012-03-20
申请人： Eiji KITAGAWA , Naoharu SHIMOMURA , Hiroaki Yoda , Junichi ITO , Minoru AMANO , Chikayoshi KAMATA , Keiko ABE
发明人： Eiji KITAGAWA , Naoharu SHIMOMURA , Hiroaki Yoda , Junichi ITO , Minoru AMANO , Chikayoshi KAMATA , Keiko ABE
IPC分类号： G11C11/16
CPC分类号： G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C19/0808
摘要： A magnetoresistive device of an embodiment includes: first and second devices each including, a first magnetic layer having a changeable magnetization perpendicular to a film plane, a second magnetic layer having a fixed and perpendicular magnetization, and a nonmagnetic layer interposed between the first and second magnetic layers, the first and second devices being disposed in parallel on a first face of an interconnect layer; and a TMR device including a third magnetic layer having perpendicular magnetic anisotropy and having a changeable magnetization, a fourth magnetic layer having a fixed magnetization parallel to a film plane, and a tunnel barrier layer interposed between the third and fourth magnetic layers, the TMR device being disposed on a second face of the interconnect layer, and the third magnetic layer being magnetostatically coupled to the first magnetic layers of the first and second devices.
摘要翻译：实施例的磁阻装置包括：第一和第二装置，每个包括：具有垂直于膜平面的可变磁化的第一磁性层，具有固定和垂直磁化的第二磁性层，以及介于第一和第二磁化层之间的非磁性层磁性层，所述第一和第二装置平行布置在互连层的第一面上; 以及包括具有垂直磁各向异性并且具有可变磁化的第三磁性层的TMR器件，具有与膜平面平行的固定磁化强度的第四磁性层和介于第三和第四磁性层之间的隧道势垒层，TMR器件布置在所述互连层的第二面上，并且所述第三磁性层被静磁耦合到所述第一和第二器件的第一磁性层。

2. 发明申请

US20100057813A1 PROGRAM ANCILLARY DATA PROCESSING DEVICE, SERVER DEVICE, PROGRAM INFORMATION DISPLAYING METHOD, AND RECORDING MEDIUM 有权
标题翻译：程序设备数据处理设备，服务器设备，程序信息显示方法和记录介质
公开(公告)号：US20100057813A1
公开(公告)日：2010-03-04
申请号：US12608033
申请日：2009-10-29
申请人： Keiko ABE , Noboru Yanagita , Takumi Yoshida , Norifumi Zushi
发明人： Keiko ABE , Noboru Yanagita , Takumi Yoshida , Norifumi Zushi
IPC分类号： G06F17/30 , H04N5/445
CPC分类号： H04H20/93 , G06Q30/02 , H04H60/31 , H04H60/48 , H04H60/49 , H04H60/63 , H04H60/73 , H04N5/44543 , H04N7/08 , H04N7/17318 , H04N21/2542 , H04N21/4622 , H04N21/47815 , H04N21/8352 , H04N21/84 , H04N21/8586
摘要： A program ancillary data processing apparatus is provided which includes a program ancillary data extraction unit for extracting program ancillary data pertinent to commodities or services appearing in each scene, from picture program data, and a display control unit for displaying, on a display picture, the information relevant to the commodities or services appearing in each scene, and the sum total of the number of times of scene-based access events by the audience to a database supervising the detailed information relevant to the commodities or services, based on the preset layout information.
摘要翻译：提供了一种程序辅助数据处理装置，其包括：程序辅助数据提取单元，用于从图像程序数据中提取与出现在每个场景中的商品或服务有关的程序辅助数据;以及显示控制单元，用于在显示图像上显示与每个场景中出现的商品或服务相关的信息，以及基于预设布局信息的观众到监视与商品或服务相关的详细信息的数据库的场景访问事件的次数的总和。

3. 发明申请

US20110216573A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20110216573A1
公开(公告)日：2011-09-08
申请号：US12884452
申请日：2010-09-17
申请人： Keiko ABE , Shinobu FUJITA
发明人： Keiko ABE , Shinobu FUJITA
IPC分类号： G11C11/15 , G11C11/21
CPC分类号： G11C14/009 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C11/21 , G11C14/0054 , G11C14/0081
摘要： According to one embodiment, a semiconductor integrated circuit includes first and second inverters, a first transistor which has a gate connected to a word line, a source connected to a first bit line, and a drain connected to an input terminal of the second inverter, a second transistor which has a gate connected to the word line, a source connected to a second bit line, and a drain connected to an input terminal of the first inverter, a first variable resistive element which has a first terminal connected to the drain of the first transistor, and a second terminal connected to an output terminal of the first inverter, and a second variable resistive element which has a first terminal connected to the drain of the second transistor, and a second terminal connected to an output terminal of the second inverter.
摘要翻译：根据一个实施例，半导体集成电路包括第一和第二反相器，具有连接到字线的栅极的第一晶体管，连接到第一位线的源极和连接到第二反相器的输入端子的漏极，第二晶体管，其具有连接到字线的栅极，连接到第二位线的源极和连接到第一反相器的输入端子的漏极;第一可变电阻元件，其具有连接到第一位线的漏极的第一端子第一晶体管和连接到第一反相器的输出端的第二端子，以及第二可变电阻元件，其具有连接到第二晶体管的漏极的第一端子，以及连接到第二晶体管的输出端子的第二端子逆变器。

4. 发明申请

US20110020926A1 NOVEL TASTE-MODIFYING POLYPEPTIDE NAS, DNA THEREOF AND USE THEREOF 有权
标题翻译：新型修饰多糖NAS，其DNA及其用途
公开(公告)号：US20110020926A1
公开(公告)日：2011-01-27
申请号：US12896676
申请日：2010-10-01
申请人： Keiko ABE , Tomiko Asakura , Hiroyuki Sorimachi , Tazuko Uenoyama , Kenichiro Nakajima , Katsuhiko Kitamoto , Junichi Maruyama , Mikiya Kishi
发明人： Keiko ABE , Tomiko Asakura , Hiroyuki Sorimachi , Tazuko Uenoyama , Kenichiro Nakajima , Katsuhiko Kitamoto , Junichi Maruyama , Mikiya Kishi
IPC分类号： C12N15/63 , C07H21/04
CPC分类号： C07K14/47 , A23L27/31
摘要： Disclosed is a polypeptide shown below in (A) or (B), a protein dimer neoculin comprising the polypeptide Neoculin Acidic Subunit (NAS) and the polypeptide Neoculin Basic Subunit (NBS) and having a taste-modifying activity: (A) a polypeptide comprising an amino acid sequence shown in SEQ ID NO.2 in the sequence listing; (B) a polypeptide comprising an amino acid sequence with the substitution, deletion, insertion, addition or inversion of one or several amino acids in the amino acid sequence shown in SEQ ID NO. 2 in the sequence listing, which polypeptide can form the neoculin dimer having a taste-modifying activity together with the polypeptide NBS.
摘要翻译：公开了下述（A）或（B）所示的多肽，其包含多肽新霉素酸性亚基（NAS）和多肽新霉素碱基亚基（NBS）并具有调味活性的蛋白质二聚体新霉素：（A）多肽包含序列表中SEQ ID NO：2所示的氨基酸序列; （B）包含SEQ ID NO：1所示的氨基酸序列中的一个或几个氨基酸的取代，缺失，插入，添加或倒位的氨基酸序列的多肽。 2，该多肽可以与多肽NBS一起形成具有调味活性的新霉素二聚体。

5. 发明申请

US20100080054A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND ITS READING METHOD 有权
标题翻译：非易失性半导体存储器件及其读取方法
公开(公告)号：US20100080054A1
公开(公告)日：2010-04-01
申请号：US12406498
申请日：2009-03-18
申请人： Keiko ABE
发明人： Keiko ABE
IPC分类号： G11C11/14 , G11C11/416 , G11C7/06
CPC分类号： H01L27/228 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A reading method includes: selecting the memory cell; performing a read operation on the selected memory cell to supply the read voltage, amplifying a first voltage read out from the selected memory element, outputting a second voltage obtained by amplifying the first voltage, and storing the second voltage as a first read state; performing a write operation on the selected memory cell to supply one of the first and second write voltages, regarding a third voltage appearing on the second line during the write operation as a second read state, comparing the first read state with the second read state, and deciding a state stored in the memory element before the read operation, as a read logic state on the basis of a result of the comparison; and writing the decided read logic state into the memory element if a logic state written in the write operation is different from the decided read logic state.
摘要翻译：读取方法包括：选择存储单元; 对所选择的存储单元执行读取操作以提供读取电压，放大从所选存储元件读出的第一电压，输出通过放大第一电压获得的第二电压，并将第二电压存储为第一读取状态; 对所选择的存储单元执行写入操作，以便在写入操作期间将出现在第二行上的第三电压提供第一和第二写入电压中的一个作为第二读取状态，将第一读取状态与第二读取状态进行比较，并且根据比较结果，将在读取操作之前存储在存储元件中的状态判定为读取逻辑状态; 以及如果在所述写入操作中写入的逻辑状态与所述决定的读取逻辑状态不同，则将所述决定的读取逻辑状态写入所述存储器元件。

6. 发明申请

US20130268795A1 CACHE SYSTEM AND INFORMATION-PROCESSING DEVICE 有权
标题翻译：缓存系统和信息处理设备
公开(公告)号：US20130268795A1
公开(公告)日：2013-10-10
申请号：US13729382
申请日：2012-12-28
申请人： Kumiko NOMURA , Shinobu FUJITA , Keiko ABE , Kazutaka IKEGAMI , Hiroki NOGUCHI
发明人： Kumiko NOMURA , Shinobu FUJITA , Keiko ABE , Kazutaka IKEGAMI , Hiroki NOGUCHI
IPC分类号： G06F1/32
CPC分类号： G06F1/3206 , G06F1/3225 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： According to one embodiment, a cache system includes a tag memory includes a volatile memory device, the tag memory includes ways and storing a tag for each line, a data memory includes a nonvolatile memory device including sense amplifiers for reading data, the data memory includes ways and storing data for each line, a comparison circuit configured to compare a tag included in an address supplied from an external with a tag read from the tag memory, and a controller configured to turn off a power of a sense amplifier for a way which is not accessed based on a comparison result of the comparison circuit.
摘要翻译：根据一个实施例，缓存系统包括标签存储器，其包括易失性存储器设备，标签存储器包括每条线路的方式和存储标签，数据存储器包括包括用于读取数据的读出放大器的非易失性存储器件，数据存储器包括方式和存储每行的数据，比较电路，被配置为将从外部提供的地址中包含的标签与从标签存储器读取的标签进行比较，以及控制器，被配置为关闭读出放大器的功率，基于比较电路的比较结果不被访问。

7. 发明申请

US20130040371A1 PROTEIN HAVING SWEETNESS 审中-公开
标题翻译：有蛋白质的蛋白质
公开(公告)号：US20130040371A1
公开(公告)日：2013-02-14
申请号：US13544675
申请日：2012-07-09
申请人： Keiko ABE , Kenichiro Nakajima , Tomiko Asakura , Takumi Misaka , Sho Ishii
发明人： Keiko ABE , Kenichiro Nakajima , Tomiko Asakura , Takumi Misaka , Sho Ishii
IPC分类号： C12N15/29 , C12N1/15 , C12N15/63
CPC分类号： C07K14/415 , A23L27/31 , C07K14/43
摘要： Provided are: an NAS variant characterized by having sweetness independent of pH in the case of combination with a polypeptide NBS variant by causing substitution mutation or deletion mutation in one or several amino acids out of the amino acid residues constituting a polypeptide NAS; an NBS variant characterized by having sweetness independent of pH in the case of combination with a polypeptide NAS variant by causing substitution mutation or deletion mutation in one or several amino acids out of the amino acid residues constituting a polypeptide NBS; a dimer comprising a combination of the NAS variant and the NBS variant; a recombinant vector containing a gene encoding the NAS variant and a gene encoding the NBS variant; and a transformant containing the vector.
摘要翻译：提供：NAS变体，其特征在于通过在构成多肽NAS的氨基酸残基中的一个或几个氨基酸中引起取代突变或缺失突变，在与多肽NBS变体组合的情况下具有与pH无关的甜度; 在通过在构成多肽NBS的氨基酸残基中的一个或几个氨基酸中引发取代突变或缺失突变而与多肽NAS变体组合的情况下，其特征在于具有独立于pH的甜度的NBS变体; 包含NAS变体和NBS变体的组合的二聚体; 包含编码NAS变体的基因和编码NBS变体的基因的重组载体; 和含有载体的转化体。

8. 发明申请

US20130028012A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND PROCESSOR 有权
标题翻译：半导体集成电路和处理器
公开(公告)号：US20130028012A1
公开(公告)日：2013-01-31
申请号：US13556431
申请日：2012-07-24
申请人： Shinobu FUJITA , Keiko ABE
发明人： Shinobu FUJITA , Keiko ABE
IPC分类号： G11C11/16
CPC分类号： G11C14/0054 , G11C11/16 , G11C14/0081
摘要： In one embodiment, there is provided a semiconductor integrated circuit that includes: a first inverter; a second inverter; a first transistor, wherein one end of the first transistor is connected to a first bit line and the other end of the first transistor is connected to a first input terminal of the first inverter; a first element group including second transistors, wherein one end of the first element group is connected to a first output terminal of the first inverter and the other end of the first element group is connected to a second bit line; and a second element group including third transistors and a magnetoresistive element whose magnetic resistance is varied. The second element group is disposed between the second output terminal of the second inverter and a first terminal or disposed between the first transistor and the first terminal.
摘要翻译：在一个实施例中，提供了一种半导体集成电路，其包括：第一反相器; 第二个逆变器; 第一晶体管，其中第一晶体管的一端连接到第一位线，第一晶体管的另一端连接到第一反相器的第一输入端; 包括第二晶体管的第一元件组，其中第一元件组的一端连接到第一反相器的第一输出端子，第一元件组的另一端连接到第二位线; 以及包括第三晶体管和磁阻变化的磁阻元件的第二元件组。第二元件组设置在第二反相器的第二输出端子与第一端子之间或者设置在第一晶体管和第一端子之间。

9. 发明申请

US20120246412A1 CACHE SYSTEM AND PROCESSING APPARATUS 有权
标题翻译：缓存系统和处理设备
公开(公告)号：US20120246412A1
公开(公告)日：2012-09-27
申请号：US13234837
申请日：2011-09-16
申请人： Kumiko NOMURA , Keiko ABE , Shinobu FUJITA
发明人： Kumiko NOMURA , Keiko ABE , Shinobu FUJITA
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/123 , G06F2212/225 , Y02D10/13
摘要： According to an embodiment, in a cache system, the sequence storage stores sequence data in association with each piece of data to be stored in the volatile cache memory in accordance with the number of pieces of data stored in the nonvolatile cache memory that have been unused for a longer period of time than the data stored in the volatile cache memory or the number of pieces of data stored in the nonvolatile cache memory that have been unused for a shorter period of time than the data stored in the volatile cache memory. The controller causes the first piece of data to be stored in the nonvolatile cache memory in a case where it can be determined that the first piece of data has been unused for a shorter period of time than any piece of the data stored in the nonvolatile cache memory.
摘要翻译：根据实施例，在高速缓存系统中，序列存储器根据存储在非易失性高速缓冲存储器中的数据的数量与已经被使用的非易失性高速缓冲存储器中存储的数据数量相关联地存储与要存储在易失性高速缓存存储器中的每条数据相关联比存储在易失性高速缓冲存储器中的数据或存储在非易失性高速缓冲存储器中的数据的时间长于存储在易失性高速缓冲存储器中的数据的时间长于较短时间段的更长时间段。在可以确定第一条数据已被使用的时间短于存储在非易失性高速缓冲存储器中的任何数据的时间段的情况下，控制器使得第一条数据被存储在非易失性高速缓冲存储器中记忆。

10. 发明申请

US20100073991A1 STORAGE APPARATUS 有权
标题翻译：存储设备
公开(公告)号：US20100073991A1
公开(公告)日：2010-03-25
申请号：US12404510
申请日：2009-03-16
申请人： Yutaka YAMADA , Tatsunori KANAI , Masaya TARUI , Keiko ABE
发明人： Yutaka YAMADA , Tatsunori KANAI , Masaya TARUI , Keiko ABE
IPC分类号： G11C11/00 , G11C7/10
CPC分类号： G11C13/00 , G11C11/1659 , G11C11/56 , G11C11/5607 , G11C11/5678 , G11C11/5685 , G11C13/0069 , G11C14/0081 , G11C2013/0073
摘要： According to one embodiment, a storage apparatus includes: a first inverter; a second inverter; a first storage element having a first state and a second state; and a second storage element having a third state and a fourth state, wherein the first storage element is brought into the first state when a current flows from the first storage element to the first storage element and is brought into the second state when the current flows from the first storage element to the first storage element, wherein the second storage element is brought into the fourth state when a current flows from the second storage element to the second storage element and is brought into the third state when the current flows from the second storage element to the second storage element.
摘要翻译：根据一个实施例，一种存储装置包括：第一反相器; 第二个逆变器; 具有第一状态和第二状态的第一存储元件; 以及具有第三状态和第四状态的第二存储元件，其中当电流从第一存储元件流向第一存储元件时，第一存储元件处于第一状态，并且当电流流动时处于第二状态从第一存储元件到第一存储元件，其中当电流从第二存储元件流到第二存储元件时，第二存储元件处于第四状态，并且当电流从第二存储元件存储元件到第二存储元件。

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