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1. 发明授权

US09846628B2 Indicating parallel operations with user-visible events 有权
公开(公告)号：US09846628B2
公开(公告)日：2017-12-19
申请号：US12816165
申请日：2010-06-15
申请人： Edward G. Essey , Igor Ostrovsky , Pooja Nagpal , Huseyin S. Yildiz , Hazim Shafi , William T. Colburn
发明人： Edward G. Essey , Igor Ostrovsky , Pooja Nagpal , Huseyin S. Yildiz , Hazim Shafi , William T. Colburn
IPC分类号： G06F9/44 , G06F3/048 , G06F11/32 , G06F11/34
CPC分类号： G06F11/323 , G06F11/3409 , G06F11/3476 , G06F2201/86
摘要： The present invention extends to methods, systems, and computer program products for indicating parallel operations with user-visible events. Event markers can be used to indicate an abstracted outer layer of execution as well as expose internal specifics of parallel processing systems, including systems that provide data parallelism. Event markers can be used to show a variety of execution characteristics including higher-level markers to indicate the beginning and end of an execution program (e.g., a query). Inside the execution program (query) individual fork/join operations can be indicated with sub-levels of markers to expose their operations. Additional decisions made by an execution engine, such as, for example, when elements initially yield, when queries overlap or nest, when the query is cancelled, when the query bails to sequential operation, when premature merging or re-partitioning are needed can also be exposed.

2. 发明申请

US20110307905A1 INDICATING PARALLEL OPERATIONS WITH USER-VISIBLE EVENTS 有权
标题翻译：用用户可见的事件指示平行操作
公开(公告)号：US20110307905A1
公开(公告)日：2011-12-15
申请号：US12816165
申请日：2010-06-15
申请人： Edward G. Essey , Igor Ostrovsky , Pooja Nagpal , Huseyin S. Yildiz , Hazim Shafi , William T. Colburn
发明人： Edward G. Essey , Igor Ostrovsky , Pooja Nagpal , Huseyin S. Yildiz , Hazim Shafi , William T. Colburn
IPC分类号： G06F9/44 , G06F3/048
CPC分类号： G06F11/323 , G06F11/3409 , G06F11/3476 , G06F2201/86
摘要： The present invention extends to methods, systems, and computer program products for indicating parallel operations with user-visible events. Event markers can be used to indicate an abstracted outer layer of execution as well as expose internal specifics of parallel processing systems, including systems that provide data parallelism. Event markers can be used to show a variety of execution characteristics including higher-level markers to indicate the beginning and end of an execution program (e.g., a query). Inside the execution program (query) individual fork/join operations can be indicated with sub-levels of markers to expose their operations. Additional decisions made by an execution engine, such as, for example, when elements initially yield, when queries overlap or nest, when the query is cancelled, when the query bails to sequential operation, when premature merging or re-partitioning are needed can also be exposed.
摘要翻译：本发明扩展到用于指示与用户可见事件并行操作的方法，系统和计算机程序产品。事件标记可用于指示抽象的外层执行，以及公开并行处理系统的内部细节，包括提供数据并行性的系统。事件标记可用于显示各种执行特征，包括用于指示执行程序（例如，查询）的开始和结束的更高级标记。在执行程序（查询）中，可以使用子级别的标记来显示单独的fork / join操作，以显示其操作。执行引擎做出的其他决定，例如当元素最初产生时，当查询重叠或嵌套时，当查询被取消时，当查询需要顺序操作时，当需要提前合并或重新分区时也可以被暴露

3. 发明授权

US09141507B2 Visualization of states of a process 有权
标题翻译：过程状态的可视化
公开(公告)号：US09141507B2
公开(公告)日：2015-09-22
申请号：US12646155
申请日：2009-12-23
申请人： Xinhua Ji , Alexander Dadiomov , Hazim Shafi , Eric Ledoux , William T. Colburn
发明人： Xinhua Ji , Alexander Dadiomov , Hazim Shafi , Eric Ledoux , William T. Colburn
IPC分类号： G06F3/00 , G06F11/32 , G06F3/01 , G06F11/36
CPC分类号： G06F11/323 , G06F11/3664
摘要： A method of providing a visualization of states of a process includes identifying a set of potential states that can occur during the process and a corresponding set of colors, with each color in the set of colors corresponding to one of the potential states. A fixed ordering is established for the set of colors. A timeline graph including a plurality of colored vertical bars is displayed. Each colored vertical bar corresponds to a time interval of the process and includes at least one color selected from the set of colors based on at least one state occurring during the time interval corresponding to the vertical bar. The plurality of colored vertical bars includes a set of multiple-color vertical bars that each include a plurality of colors appearing in a vertical order based on the fixed ordering.
摘要翻译：提供过程状态可视化的方法包括识别可在过程期间发生的一组潜在状态和相应的一组颜色，其中该组颜色中的每种颜色对应于潜在状态之一。为该组颜色建立固定的顺序。显示包括多个彩色垂直条的时间线图。每个彩色垂直条对应于处理的时间间隔，并且基于在对应于垂直条的时间间隔期间发生的至少一个状态，包括从该组颜色中选择的至少一种颜色。多个彩色垂直条包括一组多色垂直条，每一个垂直条都包含基于固定顺序以垂直顺序出现的多种颜色。

4. 发明申请

US20110154245A1 VISUALIZATION OF STATES OF A PROCESS 有权
标题翻译：过程状态的可视化
公开(公告)号：US20110154245A1
公开(公告)日：2011-06-23
申请号：US12646155
申请日：2009-12-23
申请人： Xinhua Ji , Alexander Dadiomov , Hazim Shafi , Eric Ledoux , William T. Colburn
发明人： Xinhua Ji , Alexander Dadiomov , Hazim Shafi , Eric Ledoux , William T. Colburn
IPC分类号： G06F3/048
CPC分类号： G06F11/323 , G06F11/3664
摘要： A method of providing a visualization of states of a process includes identifying a set of potential states that can occur during the process and a corresponding set of colors, with each color in the set of colors corresponding to one of the potential states. A fixed ordering is established for the set of colors. A timeline graph including a plurality of colored vertical bars is displayed. Each colored vertical bar corresponds to a time interval of the process and includes at least one color selected from the set of colors based on at least one state occurring during the time interval corresponding to the vertical bar. The plurality of colored vertical bars includes a set of multiple-color vertical bars that each include a plurality of colors appearing in a vertical order based on the fixed ordering.
摘要翻译：提供过程状态可视化的方法包括识别可在过程期间发生的一组潜在状态和相应的一组颜色，其中该组颜色中的每种颜色对应于潜在状态之一。为该组颜色建立固定的顺序。显示包括多个彩色垂直条的时间线图。每个彩色垂直条对应于处理的时间间隔，并且基于在对应于垂直条的时间间隔期间发生的至少一个状态，包括从该组颜色中选择的至少一种颜色。多个彩色垂直条包括一组多色垂直条，每一个垂直条都包含基于固定顺序以垂直顺序出现的多种颜色。

5. 发明授权

US09594656B2 Analysis and visualization of application concurrency and processor resource utilization 有权
标题翻译：应用程序并发和处理器资源利用的分析和可视化
公开(公告)号：US09594656B2
公开(公告)日：2017-03-14
申请号：US12605932
申请日：2009-10-26
申请人： Hazim Shafi
发明人： Hazim Shafi
IPC分类号： G06F9/46 , G06F11/30 , G06F11/32 , G06F11/36
CPC分类号： G06F11/3664 , G06F11/3017 , G06F11/302 , G06F11/3072 , G06F11/32 , G06F11/3419
摘要： An analysis and visualization depicts how an application is leveraging computer processor cores in time. The analysis and visualization enables a developer to readily identify the degree of concurrency exploited by an application at runtime. Information regarding processes or threads running on the processor cores over time is received, analyzed, and presented to indicate portions of processor cores that are used by the application, idle, or used by other processes in the system. The analysis and visualization can help a developer understand contention for processor resources, confirm the degree of concurrency, or identify serial regions of execution that might provide opportunities for exploiting parallelism.
摘要翻译：分析和可视化描述了应用程序如何及时利用计算机处理器内核。分析和可视化使开发人员能够在运行时轻松识别应用程序利用的并发程度。接收，分析和呈现关于在时间上在处理器核上运行的进程或线程的信息，以指示应用程序使用的处理器核心部分，空闲或由系统中的其他进程使用。分析和可视化可以帮助开发人员了解处理器资源的争用，确认并发程度，或确定可能提供利用并行性的机会的连续执行区域。

6. 发明授权

US08909871B2 Data processing system and method for reducing cache pollution by write stream memory access patterns 有权
标题翻译：用于通过写入流存储器访问模式减少高速缓存污染的数据处理系统和方法
公开(公告)号：US08909871B2
公开(公告)日：2014-12-09
申请号：US11462115
申请日：2006-08-03
申请人： Ravi K. Arimilli , Francis P. O'Connell , Hazim Shafi , Derek E. Williams , Lixin Zhang
发明人： Ravi K. Arimilli , Francis P. O'Connell , Hazim Shafi , Derek E. Williams , Lixin Zhang
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0888
摘要： A data processing system includes a system memory and a cache hierarchy that caches contents of the system memory. According to one method of data processing, a storage modifying operation having a cacheable target real memory address is received. A determination is made whether or not the storage modifying operation has an associated bypass indication. In response to determining that the storage modifying operation has an associated bypass indication, the cache hierarchy is bypassed, and an update indicated by the storage modifying operation is performed in the system memory. In response to determining that the storage modifying operation does not have an associated bypass indication, the update indicated by the storage modifying operation is performed in the cache hierarchy.
摘要翻译：数据处理系统包括缓存系统存储器的内容的系统存储器和高速缓存层级。根据一种数据处理方法，接收具有可缓存目标实际存储器地址的存储修改操作。确定存储修改操作是否具有相关的旁路指示。响应于确定存储修改操作具有相关联的旁路指示，忽略高速缓存层级，并且在系统存储器中执行由存储修改操作指示的更新。响应于确定存储修改操作没有相关联的旁路指示，在高速缓存层级中执行由存储修改操作指示的更新。

7. 发明授权

US08572581B2 Measurement and reporting of performance event rates 有权
标题翻译：绩效事件发生率的测量和报告
公开(公告)号：US08572581B2
公开(公告)日：2013-10-29
申请号：US12411435
申请日：2009-03-26
申请人： Hazim Shafi , Khaled S. Sedky
发明人： Hazim Shafi , Khaled S. Sedky
IPC分类号： G06F9/44
CPC分类号： G06F11/328 , G06F11/3466 , G06F11/3476 , G06F2201/835 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： Methods and systems are disclosed for measuring performance event rates at a computer and reporting the performance event rates using timelines. A particular method tracks, for a time period, the occurrences of a particular event at a computer. Event rates corresponding to different time segments within the time period are calculated, and the time segments are assigned colors based on their associated event rates. The event rates are used to display a colored timeline for the time period, including displaying a colored timeline portion for each time segment in its associated color.
摘要翻译：公开了用于测量计算机的性能事件发生率并使用时间表报告性能事件发生率的方法和系统。特定方法在一段时间内跟踪计算机上特定事件的发生。计算对应于该时间段内的不同时间段的事件速率，并且基于它们相关联的事件发生率来分配时间段的颜色。事件速率用于显示该时间段的彩色时间线，包括在其相关联的颜色中显示每个时间段的彩色时间线部分。

8. 发明申请

US20120198459A1 ASSIST THREAD FOR INJECTING CACHE MEMORY IN A MICROPROCESSOR 有权
标题翻译：在微处理器中注入高速缓存存储器的辅助螺纹
公开(公告)号：US20120198459A1
公开(公告)日：2012-08-02
申请号：US13434423
申请日：2012-03-29
申请人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
发明人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F9/46 , G06F12/08
CPC分类号： G06F9/383 , G06F9/3851 , G06F9/4881 , G06F12/0862
摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.
摘要翻译：数据处理系统包括具有访问多级缓存存储器的微处理器。微处理器执行从源代码对象编译的主线程。该系统包括用于执行也源自源代码对象的辅助线程的处理器。辅助线程包括主线程的存储器参考指令和仅解析存储器参考指令所需的算术指令。配置成与对应的执行线程一起调度辅助线程的调度器被配置为通过诸如主处理器周期的数量或代码指令的数量的可确定的阈值来执行执行线程之前的辅助线程。辅助线程可以在主处理器或专用辅助处理器中执行，该处理器直接对下一级高速缓冲存储器元件之一进行存储器访问。

9. 发明授权

US08230422B2 Assist thread for injecting cache memory in a microprocessor 有权
标题翻译：协助在微处理器中注入高速缓存的线程
公开(公告)号：US08230422B2
公开(公告)日：2012-07-24
申请号：US11034546
申请日：2005-01-13
申请人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
发明人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F9/46 , G06F9/40 , G06F13/28
CPC分类号： G06F9/383 , G06F9/3851 , G06F9/4881 , G06F12/0862
摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.
摘要翻译：数据处理系统包括具有访问多级缓存存储器的微处理器。微处理器执行从源代码对象编译的主线程。该系统包括用于执行也源自源代码对象的辅助线程的处理器。辅助线程包括主线程的存储器参考指令和仅解析存储器参考指令所需的算术指令。配置成与对应的执行线程一起调度辅助线程的调度器被配置为通过诸如主处理器周期的数量或代码指令的数量的可确定的阈值来执行执行线程之前的辅助线程。辅助线程可以在主处理器或专用辅助处理器中执行，该处理器直接对下一级高速缓冲存储器元件之一进行存储器访问。

10. 发明申请

US20100223600A1 THREAD EXECUTION ANALYZER 有权
标题翻译：螺纹执行分析仪
公开(公告)号：US20100223600A1
公开(公告)日：2010-09-02
申请号：US12394445
申请日：2009-02-27
申请人： Hazim Shafi , Brian Adelberg , Khaled S. Sedky
发明人： Hazim Shafi , Brian Adelberg , Khaled S. Sedky
IPC分类号： G06F9/44
CPC分类号： G06F11/3636
摘要： A thread execution analyzer analyzes blocking events of threads in a program using execution data and callstacks collected at the blocking events. The thread execution analyzer attempts to identify an application programming interface (API) responsible for each blocking event and provides blocking analysis information to a user. The blocking analysis information may be used by a developer of the program to understand the causes of blocking events that occur for threads of the program.
摘要翻译：线程执行分析器使用在阻塞事件处收集的执行数据和调用堆栈来分析程序中线程的阻塞事件。线程执行分析器尝试识别负责每个阻塞事件的应用程序编程接口（API），并向用户提供阻止分析信息。程序的开发人员可以使用阻止分析信息来了解程序线程发生的阻塞事件的原因。

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