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1. 发明授权

US6043696A Method for implementing a single phase edge-triggered dual-rail dynamic flip-flop 失效
标题翻译：用于实现单相边沿触发双轨动态触发器的方法
公开(公告)号：US6043696A
公开(公告)日：2000-03-28
申请号：US852167
申请日：1997-05-06
申请人： Edgardo F. Klass , Chaim NMI Amir
发明人： Edgardo F. Klass , Chaim NMI Amir
IPC分类号： H03K3/356 , H03K19/096
CPC分类号： H03K3/356139
摘要： A method of implementing a single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes receiving a data-input signal and a clock signal. During the precharge phase, an input stage provides an output signal that is the complement of the data input signal. When the data input signal is provided by a dynamic logic gate, the input stage output signal is precharged to a logic high level. During the evaluation phase, an output signal that either remains at a logic high level or else transitions from high-to-low is generated by the input stage. The output signal and the clock signal are received by the precharge stage from the input stage. During the precharge phase, a logic high level output signal is generated the precharge stage independently of the signal received from the input stage. However, the logic high level signal from the input stage turns on hard an n-channel transistor in the precharge stage, which minimizes the delay through the precharge stage during the evaluation phase. During the evaluation phase, the precharge stage outputs the complement of the output signal received from the input stage. The buffer is coupled to receive the output signal from the precharge stage. During both the precharge and evaluation phases, the buffer outputs the complement of the output signal received from the precharge stage.
摘要翻译：实现与动态逻辑门一起使用的单相边沿触发双轨动态触发器电路的方法包括接收数据输入信号和时钟信号。在预充电阶段期间，输入级提供作为数据输入信号的补码的输出信号。当数据输入信号由动态逻辑门提供时，输入级输出信号被预充电到逻辑高电平。在评估阶段期间，由输入级产生输出信号，其保持在逻辑高电平或者从高电平变为低电平。输出信号和时钟信号由预充电阶段从输入级接收。在预充电阶段期间，独立于从输入级接收到的信号，产生逻辑高电平输出信号的预充电级。然而，来自输入级的逻辑高电平信号在预充电阶段打开硬通道n沟道晶体管，这在评估阶段期间通过预充电阶段的延迟最小化。在评估阶段，预充电阶段输出从输入级接收的输出信号的补码。缓冲器被耦合以从预充电阶段接收输出信号。在预充电和评估阶段期间，缓冲器输出从预充电阶段接收的输出信号的补码。

2. 发明授权

US08947070B2 Apparatus and method for testing driver writeability strength on an integrated circuit 有权
标题翻译：在集成电路上测试驱动器可写性强度的装置和方法
公开(公告)号：US08947070B2
公开(公告)日：2015-02-03
申请号：US13351313
申请日：2012-01-17
申请人： Ashish R. Jain , Edgardo F. Klass
发明人： Ashish R. Jain , Edgardo F. Klass
IPC分类号： G11C8/00 , G01R31/3185 , G01R31/319
CPC分类号： G01R31/318572 , G01R31/31924
摘要： An apparatus and method for testing driver write-ability strength on an integrated circuit includes one or more drive detection units each including a number of drivers. At least some of the drivers may have a different drive strength and each may drive a voltage onto a respective driver output line. Each drive detection unit may include a number of keeper circuits, each coupled to a separate output line and configured to retain a given voltage on the output line to which it is coupled. Each detection unit may also include a number of detection circuits coupled to detect the drive voltage on each of the output lines. In one implementation, the drive voltage appearing at the output line of each driver may be indicative of that the driver was able to overdrive the voltage being retained on the output line to which it is coupled by the respective keeper circuits.
摘要翻译：用于在集成电路上测试驱动器写入能力强度的装置和方法包括一个或多个驱动器检测单元，每个驱动器检测单元包括多个驱动器。至少一些驱动器可能具有不同的驱动强度，并且每个驱动器可以将电压驱动到相应的驱动器输出线上。每个驱动器检测单元可以包括多个保持器电路，每个保持器电路分别耦合到单独的输出线并被配置为将给定电压保持在与其耦合的输出线上。每个检测单元还可以包括多个检测电路，其被耦合以检测每条输出线上的驱动电压。在一个实施方案中，出现在每个驱动器的输出线处的驱动电压可以指示驾驶员能够过度驱动保持在由相应保持器电路耦合到的输出线上的电压。

3. 发明授权

US08397199B2 Versatile method and tool for simulation of aged transistors 失效
标题翻译：用于老化晶体管仿真的多功能方法和工具
公开(公告)号：US08397199B2
公开(公告)日：2013-03-12
申请号：US12762861
申请日：2010-04-19
申请人： Apurva H. Soni , Antonietta Oliva , Edgardo F. Klass , Matthew J. T. Page , James E. Burnette, II
发明人： Apurva H. Soni , Antonietta Oliva , Edgardo F. Klass , Matthew J. T. Page , James E. Burnette, II
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In an embodiment, an aging analysis tool may be configured to identify transistors that are expected to experience aging effects according to worst case stress vectors and/or designer identified worst case conditions. The aging analysis tool may modify a representation of the circuit (e.g. a netlist), replacing the identified transistors with aged transistors (e.g. by modifying parameters of the transistors in the netlist). The aging analysis tool may process the modified netlist over a range of conditions at which the circuit is expected to operate, to ensure that the design meets specifications after aging. The process may be repeated until the aged design meets specifications (with circuit modifications made by the designer to improve the design).
摘要翻译：在一个实施例中，老化分析工具可以被配置为识别根据最坏情况的应力向量和/或设计者识别的最坏情况条件预期会经历老化效应的晶体管。老化分析工具可以修改电路的表示（例如网表），用老化的晶体管代替所识别的晶体管（例如通过修改网表中的晶体管的参数）。老化分析工具可以在电路预期运行的一系列条件下处理修改的网表，以确保设计在老化后符合规格。该过程可以重复，直到老化设计符合规格（由设计者进行的电路改进以改进设计）。

4. 发明授权

US08341578B2 Clock gater with test features and low setup time 有权
标题翻译：时钟门控器具有测试功能和低设置时间
公开(公告)号：US08341578B2
公开(公告)日：2012-12-25
申请号：US12836141
申请日：2010-07-14
申请人： Brian J. Campbell , Shaishav Desai , Edgardo F. Klass , Pradeep R. Trivedi , Sridhar Narayanan
发明人： Brian J. Campbell , Shaishav Desai , Edgardo F. Klass , Pradeep R. Trivedi , Sridhar Narayanan
IPC分类号： G06F17/50
CPC分类号： H03K19/0016 , G01R31/31922 , G06F1/10 , G06F1/3237 , H03K17/687 , Y02D10/128
摘要： A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circuit. In one embodiment, a first transistor of the plurality of transistors has a gate coupled to receive an enable input signal. A second transistor is connected in parallel with the first transistor, and has a gate controlled responsive to a test input signal to ensure that the output clock is generated even if the enable input signal is not in an enabled state. In another embodiment, the plurality of transistors comprises a first transistor having a gate controlled responsive to a clock input of the clock gater circuit and a second transistor having a gate controlled responsive to an output of a delay circuit. The delay circuit comprises at least one inverter, wherein an input of the delay circuit is the clock input, and wherein a first inverter of the delay circuit is coupled to receive a test input signal and is configured to force a first logical state on an output of the first inverter responsive to an assertion of the test input signal.
摘要翻译：时钟门电路包括多个具有在第一节点和供电节点之间形成堆叠的源极 - 漏极连接的晶体管。第一节点上的给定逻辑状态在时钟门控电路的输出时钟上引起相应的逻辑状态。在一个实施例中，多个晶体管中的第一晶体管具有耦合以接收使能输入信号的栅极。第二晶体管与第一晶体管并联连接，并且响应于测试输入信号具有控制门，以确保即使使能输入信号不处于使能状态也能产生输出时钟。在另一个实施例中，多个晶体管包括响应于时钟门电路电路的时钟输入的门控制的第一晶体管和响应于延迟电路的输出的具有门控制的第二晶体管。所述延迟电路包括至少一个逆变器，其中所述延迟电路的输入是所述时钟输入，并且其中所述延迟电路的第一反相器被耦合以接收测试输入信号，并且被配置为在输出端上强制第一逻辑状态所述第一逆变器响应于所述测试输入信号的断言。

5. 发明授权

US07373569B2 Pulsed flop with scan circuitry 有权
标题翻译：具有扫描电路的脉冲触发器
公开(公告)号：US07373569B2
公开(公告)日：2008-05-13
申请号：US11304854
申请日：2005-12-15
申请人： Edgardo F. Klass
发明人： Edgardo F. Klass
IPC分类号： G01R31/28
CPC分类号： G01R31/318533 , G01R31/318544 , G11C2029/3202
摘要： In one embodiment, a storage circuit comprises a first passgate having an input coupled to receive a signal representing a data input to the storage circuit and further having an output connected to a storage node in the storage circuit. The storage circuit also comprises a scan latch having an input connected to a scan data input to the storage circuit and further coupled to receive a scan enable input. The scan latch is configured to store the scan data input responsive to an assertion of the scan enable input, and also comprises a second passgate connected to the storage node and having an input coupled to receive the stored scan data. Each of the first passgate and the second passgate are coupled to receive respective pairs of control signals to control opening and closing of the passgates, wherein the scan enable signal controls which of the respective pairs of control signals are pulsed. In this manner, only one of the first passgate and the second passgate is opened in a given clock cycle of a clock signal from which the pulses are generated.
摘要翻译：在一个实施例中，存储电路包括第一通道门，其具有耦合以输入表示向存储电路输入的数据的信号的输入，并且还具有连接到存储电路中的存储节点的输出。存储电路还包括扫描锁存器，其具有连接到输入到存储电路的扫描数据的输入，并进一步耦合以接收扫描使能输入。扫描锁存器被配置为响应于扫描使能输入的断言来存储扫描数据输入，并且还包括连接到存储节点并具有耦合以接收所存储的扫描数据的输入的第二通道。第一通道和第二通道中的每一个被耦合以接收相应的控制信号对以控制通风门的打开和关闭，其中扫描使能信号控制相应的控制信号对中的哪一个是脉冲的。以这种方式，在产生脉冲的时钟信号的给定时钟周期中仅打开第一通道和第二通道中的一个。

6. 发明授权

US06222404B1 Edge-triggered dual-rail dynamic flip-flop with an enhanced self-shut-off mechanism 有权
标题翻译：边缘触发双轨动态触发器，具有增强的自我关闭机制
公开(公告)号：US06222404B1
公开(公告)日：2001-04-24
申请号：US09340745
申请日：1999-06-28
申请人： Anup S. Mehta , Chaim Amir , Edgardo F. Klass , Ashutosh K. Das
发明人： Anup S. Mehta , Chaim Amir , Edgardo F. Klass , Ashutosh K. Das
IPC分类号： H03K3037
CPC分类号： H03K3/0375
摘要： A shut-off circuit included in a dynamic flip-flop isolates output terminals of the dynamic flip-flop from circuitry within the flip-flop that could introduce noise on either output terminal during a portion of the evaluation phase. Since the output terminals are isolated from the input terminals during this portion of the evaluation phase, spurious input signals have no affect on the output signal levels. Similarly, charge within the dynamic flip-flop that is not completely dissipated in the transition from a precharge phase to the evaluation phase has no affect on the output signal levels during this portion of the evaluation phase.
摘要翻译：包括在动态触发器中的截止电路将触发器内的电路与电路中的电路隔离，以便在评估阶段的一部分期间在任一输出端子上引入噪声。由于在评估阶段的这一部分期间输出端子与输入端子隔离，寄生输入信号对输出信号电平没有影响。类似地，动态触发器中在从预充电阶段到评估阶段的转变中未完全消耗的电荷在评估阶段的该部分期间对输出信号电平没有影响。

7. 发明授权

US5920218A Single-phase edge-triggered dual-rail dynamic flip-flop 失效
标题翻译：单相边沿触发双轨动态触发器
公开(公告)号：US5920218A
公开(公告)日：1999-07-06
申请号：US710692
申请日：1996-09-19
申请人： Edgardo F. Klass , Chaim Amir
发明人： Edgardo F. Klass , Chaim Amir
IPC分类号： H03K3/356 , H03K3/37
CPC分类号： H03K3/356121
摘要： A single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes an input stage, precharge stage and buffer. The input stage is coupled to receive a data-input signal and a clock signal. During the precharge phase, the input stage provides an output signal that is the complement of the data input signal. When the data input signal is provided by a dynamic logic gate, the input stage output signal is precharged to a logic high level. During the evaluation phase, the input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low. The precharge stage receives the output signal from the input stage and the clock signal. During the precharge phase, the precharge stage generates a logic high level output signal independently of the signal received from the input stage. However, the logic high level signal from the input stage turns on hard a n-channel transistor in the precharge stage, which minimizes the delay through the precharge stage during the evaluation phase. During the evaluation phase, the precharge stage outputs the complement of the output signal received from the input stage. The buffer is coupled to receive the output signal from the precharge stage. During both the precharge and evaluation phases, the buffer outputs the complement of the output signal received from the precharge stage.
摘要翻译：用于动态逻辑门的单相边沿触发双轨动态触发器电路包括输入级，预充电级和缓冲器。输入级被耦合以接收数据输入信号和时钟信号。在预充电阶段期间，输入级提供作为数据输入信号的补码的输出信号。当数据输入信号由动态逻辑门提供时，输入级输出信号被预充电到逻辑高电平。在评估阶段期间，输入级产生一个输出信号，保持在逻辑高电平或从高到低转换。预充电阶段接收来自输入级的输出信号和时钟信号。在预充电阶段期间，预充电阶段独立于从输入级接收的信号产生逻辑高电平输出信号。然而，来自输入级的逻辑高电平信号在预充电阶段打开硬通道n沟道晶体管，这在评估阶段期间通过预充电阶段的延迟最小化。在评估阶段，预充电阶段输出从输入级接收的输出信号的补码。缓冲器被耦合以从预充电阶段接收输出信号。在预充电和评估阶段期间，缓冲器输出从预充电阶段接收的输出信号的补码。

8. 发明授权

US08712752B2 IR(voltage) drop analysis in integrated circuit timing 失效
标题翻译：集成电路定时中的IR（电压）下降分析
公开(公告)号：US08712752B2
公开(公告)日：2014-04-29
申请号：US13033433
申请日：2011-02-23
申请人： Betty Y. Lau , Edgardo F. Klass , Anup S. Mehta
发明人： Betty Y. Lau , Edgardo F. Klass , Anup S. Mehta
IPC分类号： G06G7/54 , G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036 , G06F2217/78 , G06F2217/84
摘要： In one embodiment, an IR drop analysis methodology may include characterizing standard cells without including power parasitic impedances, extracting the power parasitic impedances for the standard cells, and characterizing the standard cells with the power parasitic impedances. A set of timing parameters (such as minimum delays and maximum delays through the cells) may be generated from each characterization. The methodology may include comparing the timing parameters from each characterization, and identifying cells for which additional design effort should be expended to improve the power supply grid (e.g. to reduce the power parasitic impedances). For example, a margin may be budgeted for speed loss (delay increase) due to IR drop. If the difference in the timing parameters exceeds the margin, additional design effort may be warranted.
摘要翻译：在一个实施例中，IR滴分析方法可以包括表征标准单元而不包括功率寄生阻抗，提取标准单元的功率寄生阻抗，以及用功率寄生阻抗表征标准单元。可以从每个表征产生一组定时参数（诸如通过单元的最小延迟和最大延迟）。该方法可以包括比较来自每个表征的定时参数，以及识别应该花费额外的设计努力来改善电源网格（例如以减小功率寄生阻抗）的单元。例如，由于IR下降，可能会对速度损失（延迟增加）进行预算。如果定时参数的差异超过裕度，则可能需要额外的设计努力。

9. 发明授权

US08533645B2 Reducing narrow gate width effects in an integrated circuit design 失效
标题翻译：降低集成电路设计中的窄栅宽效应
公开(公告)号：US08533645B2
公开(公告)日：2013-09-10
申请号：US13097537
申请日：2011-04-29
申请人： Edgardo F. Klass
发明人： Edgardo F. Klass
IPC分类号： G06F17/50
CPC分类号： H03K19/00307 , G06F2217/78 , G06F2217/80 , G06F2217/84
摘要： A method for reducing narrow gate width effects in an integrated circuit includes finding the smallest transistor channel widths that are larger than the minimum width for the technology for library cells that produce logic blocks that meet timing constraints while using the least amount of power and have the smallest possible area. The method may include characterizing a device library while varying process, voltage and temperature parameters, and synthesizing an HDL representation of a functional logic block including cells from the device library. The method may also include determining whether timing, area, and power values of the functional logic block are within a predetermined range. In response to the timing, area, and power values not being within the predetermined range, iteratively increasing the channel width of at least a portion of the transistors of at least one of the cells in the device library.
摘要翻译：一种用于减小集成电路中的窄栅极宽度效应的方法包括找到最大的晶体管沟道宽度，该晶体管沟道宽度大于用于在使用最小量的功率时产生符合时序约束的逻辑块的库单元的技术的最小宽度，并且具有尽可能小的区域。该方法可以包括在改变过程，电压和温度参数的同时表征设备库，以及合成包括来自设备库的单元的功能逻辑块的HDL表示。该方法还可以包括确定功能逻辑块的定时，区域和功率值是否在预定范围内。响应于定时，面积和功率值不在预定范围内，迭代地增加设备库中至少一个单元的至少一部分晶体管的沟道宽度。

10. 发明授权

US08327310B1 Method and software tool for analyzing and reducing the failure rate of an integrated circuit 有权
标题翻译：用于分析和降低集成电路故障率的方法和软件工具
公开(公告)号：US08327310B1
公开(公告)日：2012-12-04
申请号：US13177916
申请日：2011-07-07
申请人： Antonietta Oliva , Gregory S. Scott , Edgardo F. Klass , Vincent R. von Kaenel
发明人： Antonietta Oliva , Gregory S. Scott , Edgardo F. Klass , Vincent R. von Kaenel
IPC分类号： G06F11/22 , G06F17/50 , G06F9/455
CPC分类号： G06F17/5036
摘要： A software tool and method for analyzing the reliability or failure rate of an integrated circuit (IC) are disclosed. The IC may include a plurality of circuit designs, and the software tool and method may aid a designer of the IC in determining a reliability rating of the IC based on reliability ratings of transistors or other circuit devices used in the circuit designs. In particular, the IC may include one or more circuit designs that have multiple instances within the IC (i.e., the same circuit design is instantiated multiple times), and the software tool and method may take into account the multiple instances when determining the reliability rating of the IC.
摘要翻译：公开了一种用于分析集成电路（IC）的可靠性或故障率的软件工具和方法。 IC可以包括多个电路设计，并且该软件工具和方法可以帮助IC的设计者基于在电路设计中使用的晶体管或其它电路器件的可靠性等级来确定IC的可靠性等级。特别地，IC可以包括在IC内具有多个实例的一个或多个电路设计（即，相同的电路设计被实例化多次），并且当确定可靠性等级时，软件工具和方法可以考虑多个实例的IC。

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