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1. 发明授权

US6043696A Method for implementing a single phase edge-triggered dual-rail dynamic flip-flop 失效
标题翻译：用于实现单相边沿触发双轨动态触发器的方法
公开(公告)号：US6043696A
公开(公告)日：2000-03-28
申请号：US852167
申请日：1997-05-06
申请人： Edgardo F. Klass , Chaim NMI Amir
发明人： Edgardo F. Klass , Chaim NMI Amir
IPC分类号： H03K3/356 , H03K19/096
CPC分类号： H03K3/356139
摘要： A method of implementing a single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes receiving a data-input signal and a clock signal. During the precharge phase, an input stage provides an output signal that is the complement of the data input signal. When the data input signal is provided by a dynamic logic gate, the input stage output signal is precharged to a logic high level. During the evaluation phase, an output signal that either remains at a logic high level or else transitions from high-to-low is generated by the input stage. The output signal and the clock signal are received by the precharge stage from the input stage. During the precharge phase, a logic high level output signal is generated the precharge stage independently of the signal received from the input stage. However, the logic high level signal from the input stage turns on hard an n-channel transistor in the precharge stage, which minimizes the delay through the precharge stage during the evaluation phase. During the evaluation phase, the precharge stage outputs the complement of the output signal received from the input stage. The buffer is coupled to receive the output signal from the precharge stage. During both the precharge and evaluation phases, the buffer outputs the complement of the output signal received from the precharge stage.
摘要翻译：实现与动态逻辑门一起使用的单相边沿触发双轨动态触发器电路的方法包括接收数据输入信号和时钟信号。在预充电阶段期间，输入级提供作为数据输入信号的补码的输出信号。当数据输入信号由动态逻辑门提供时，输入级输出信号被预充电到逻辑高电平。在评估阶段期间，由输入级产生输出信号，其保持在逻辑高电平或者从高电平变为低电平。输出信号和时钟信号由预充电阶段从输入级接收。在预充电阶段期间，独立于从输入级接收到的信号，产生逻辑高电平输出信号的预充电级。然而，来自输入级的逻辑高电平信号在预充电阶段打开硬通道n沟道晶体管，这在评估阶段期间通过预充电阶段的延迟最小化。在评估阶段，预充电阶段输出从输入级接收的输出信号的补码。缓冲器被耦合以从预充电阶段接收输出信号。在预充电和评估阶段期间，缓冲器输出从预充电阶段接收的输出信号的补码。

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