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1. 发明授权

US06433392B1 Electrostatic discharge device and method 有权
标题翻译：静电放电装置及方法
公开(公告)号：US06433392B1
公开(公告)日：2002-08-13
申请号：US09456036
申请日：1999-12-03
申请人： E. Ajith Amerasekera , Vikas Gupta , Stanton P. Ashburn
发明人： E. Ajith Amerasekera , Vikas Gupta , Stanton P. Ashburn
IPC分类号： H01L2362
CPC分类号： H01L27/0262 , H01L27/0266 , H01L29/87
摘要： The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.
摘要翻译：用于作为防止由于静电放电（ESD）事件引起的劣化的保护装置的横向npn晶体管的高电流能力通过调节集电极电流从雪崩pn结流到晶片的材料的电阻率来改进背面接触。如以第二阈值表示，报告了改进系数为4的因素。描述了两种植入序列，其应用局部掩蔽和标准植入条件以实现改进，而不增加工艺步骤的总数。 p阱工程原理扩展到采用SCR型器件的ESD保护器件。

2. 发明授权

US07456477B2 Electrostatic discharge device and method 有权
标题翻译：静电放电装置及方法
公开(公告)号：US07456477B2
公开(公告)日：2008-11-25
申请号：US10191902
申请日：2002-07-09
申请人： E. Ajith Amerasekera , Vikas Gupta , Stanton P. Ashburn
发明人： E. Ajith Amerasekera , Vikas Gupta , Stanton P. Ashburn
IPC分类号： H01L23/62
CPC分类号： H01L27/0262 , H01L27/0266 , H01L29/87
摘要： The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.
摘要翻译：用于作为防止由于静电放电（ESD）事件引起的劣化的保护装置的横向npn晶体管的高电流能力通过调节集电极电流从雪崩pn结流到晶片的材料的电阻率来改进背面接触。如以第二阈值表示，报告了改进系数为4的因素。描述了两种植入序列，其应用局部掩蔽和标准植入条件以实现改进，而不增加工艺步骤的总数。 p阱工程原理扩展到采用SCR型器件的ESD保护器件。

3. 发明授权

US06306690B1 Process flow to integrate high and low voltage peripheral transistors with a floating gate array 有权
标题翻译：将高电压和低电压外围晶体管与浮动栅极阵列集成的工艺流程
公开(公告)号：US06306690B1
公开(公告)日：2001-10-23
申请号：US09389144
申请日：1999-09-02
申请人： Cetin Kaya , Stanton P. Ashburn
发明人： Cetin Kaya , Stanton P. Ashburn
IPC分类号： H01L21332
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： The invention comprises an integrated circuit including integral high and low-voltage peripheral transistors and a method for making the integrated circuit. In one aspect of the invention, a method of integrating high and low voltage transistors into a floating gate memory array comprises the steps of forming a tunnel oxide layer outwardly from a semiconductor substrate, forming a floating gate layer disposed outwardly from the tunnel oxide layer and forming an insulator layer disposed outwardly from the floating gate layer to create a first intermediate structure. The method further includes the steps of masking a first region and a second region of the first intermediate structure leaving a third region unmasked, removing at least a portion of the insulator layer, the floating gate layer and the tunnel oxide layer from the third region and forming a first dielectric layer disposed outwardly from the substrate in a region approximately coextensive with the third region. The second region and the third region are masked, leaving the first region unmasked. Then, at least a portion of the insulator layer, the floating gate layer and the tunnel oxide layer is removed from the first region. A second dielectric layer is formed outwardly from the substrate and the first dielectric layer in a region approximately coextensive with the first region and the third regions, respectively.
摘要翻译：本发明包括集成电路，包括集成的高电压和低电压外围晶体管以及用于制造集成电路的方法。在本发明的一个方面，一种将高压和低压晶体管集成到浮动栅极存储器阵列中的方法包括以下步骤：从半导体衬底向外形成隧道氧化层，形成从隧道氧化物层向外设置的浮动栅层;以及形成从所述浮栅层向外设置以形成第一中间结构的绝缘体层。该方法还包括以下步骤：掩蔽第一中间结构的第一区域和第二区域，留下未被掩蔽的第三区域，从第三区域去除绝缘体层，浮动栅极层和隧道氧化物层的至少一部分，以及形成在与所述第三区域大致共同延伸的区域中从所述基板向外设置的第一介电层。第二个区域和第三个区域被掩盖，使第一个区域被隐藏。然后，从第一区域去除绝缘体层，浮栅和隧道氧化物层的至少一部分。在与第一区域和第三区域大致共同延伸的区域中，从基板和第一介电层向外形成第二电介质层。

4. 发明授权

US06326281B1 Integrated circuit isolation 有权
标题翻译：集成电路隔离
公开(公告)号：US06326281B1
公开(公告)日：2001-12-04
申请号：US09405278
申请日：1999-09-23
申请人： Katherine E. Violette , Rick L. Wise , Stanton P. Ashburn , Mahalingam Nandakumar , Douglas T. Grider
发明人： Katherine E. Violette , Rick L. Wise , Stanton P. Ashburn , Mahalingam Nandakumar , Douglas T. Grider
IPC分类号： H01L2136
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/31604 , H01L21/762
摘要： Silicon substrate isolation by epitaxial growth of silicon through windows in a mask made of silicon nitride (202) on silicon oxide (201) with the silicon oxide etched to undercut the silicon nitride; the mask is on a silicon substrate.
摘要翻译：通过在氧化硅（201）上由氮化硅（202）制成的掩模中的硅通过窗口外延生长硅氧化硅衬底，氧化硅被蚀刻以切割氮化硅; 掩模在硅衬底上。

5. 发明授权

US6030874A Doped polysilicon to retard boron diffusion into and through thin gate dielectrics 失效
标题翻译：掺杂的多晶硅以阻止硼扩散进入并通过薄栅极电介质
公开(公告)号：US6030874A
公开(公告)日：2000-02-29
申请号：US7060
申请日：1998-01-13
申请人： Douglas T. Grider , Stanton P. Ashburn , Katherine E. Violette , F. Scott Johnson
发明人： Douglas T. Grider , Stanton P. Ashburn , Katherine E. Violette , F. Scott Johnson
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/28035 , H01L21/2807 , H01L21/28176 , H01L21/32155 , H01L21/823842 , H01L29/4916 , H01L29/4966 , H01L21/28194 , H01L21/28202 , H01L29/518
摘要： An embodiment of the instant invention is a method of fabricating a semiconductor device which includes a dielectric layer situated between a conductive structure and a semiconductor substrate, the method comprising the steps of: forming the dielectric layer (layer 14) on the semiconductor substrate (substrate 12); forming the conductive structure (structure 18) on the dielectric layer; doping the conductive structure with boron; and doping the conductive structure with a dopant which inhibits the diffusion of boron. The semiconductor device may be a PMOS transistor or a capacitor. Preferably, the conductive structure is a gate structure. The dielectric layer is, preferably, comprised of a material selected from the group consisting of: an oxide, an oxide/oxide stack, an oxide/nitride stack, and an oxynitride. Preferably, the dopant which inhibits the diffusion of boron comprises at least one group III or group IV element. More specifically, it is preferably comprised of: carbon, germanium, and any combination thereof. Preferably, the steps of doping the conductive structure with boron and doping the conductive structure with a dopant which inhibits the diffusion of boron are accomplished substantially simultaneously, or the step of doping the conductive structure with boron is preformed prior to the step of doping the conductive structure with a dopant which inhibits the diffusion of boron are accomplished substantially simultaneously.
摘要翻译：本发明的实施例是一种制造半导体器件的方法，该半导体器件包括位于导电结构和半导体衬底之间的电介质层，该方法包括以下步骤：在半导体衬底（衬底）上形成介电层（层14） 12）; 在电介质层上形成导电结构（结构18）; 用硼掺杂导电结构; 并用抑制硼扩散的掺杂剂掺杂导电结构。半导体器件可以是PMOS晶体管或电容器。优选地，导电结构是栅极结构。电介质层优选由选自氧化物，氧化物/氧化物堆，氧化物/氮化物叠层和氧氮化物的材料组成。优选地，抑制硼扩散的掺杂剂包含至少一个III族或IV族元素。更具体地，其优选包括：碳，锗及其任何组合。优选地，用硼掺杂导电结构并用抑制硼的扩散的掺杂剂掺杂导电结构的步骤基本上同时实现，或者在掺杂导电的步骤之前预先形成用硼掺杂导电结构的步骤具有抑制硼扩散的掺杂剂的结构基本上同时完成。

6. 发明授权

US5336903A Selective deposition of doped silicon-germanium alloy on semiconductor substrate, and resulting structures 失效
标题翻译：掺杂硅 - 锗合金在半导体衬底上的选择性沉积，以及所得结构
公开(公告)号：US5336903A
公开(公告)日：1994-08-09
申请号：US69030
申请日：1993-05-28
申请人： Mehmet C. Ozturk , Douglas T. Grider , Mahesh K. Sanganeria , Stanton P. Ashburn , Jimmie J. Wortman
发明人： Mehmet C. Ozturk , Douglas T. Grider , Mahesh K. Sanganeria , Stanton P. Ashburn , Jimmie J. Wortman
IPC分类号： H01L21/225 , H01L21/285 , H01L21/336 , H01L21/60 , H01L23/48
CPC分类号： H01L21/76897 , H01L21/2254 , H01L21/28518 , H01L29/41783 , H01L29/66545 , H01L29/66575 , H01L2924/0002 , Y10S148/058 , Y10S148/059
摘要： Doped silicon-germanium alloy is selectively deposited on a semiconductor substrate, and the semiconductor substrate is then heated to diffuse at least some of the dopant from the silicon-germanium alloy into the semiconductor substrate to form a doped region at the face of the semiconductor substrate. The doped silicon-germanium alloy acts as a diffusion source for the dopant, so that shallow doped, regions may be formed at the face of the semiconductor substrate without ion implantation. A high performance contact to the doped region is also provided by forming a metal layer on the doped silicon-germanium alloy layer and heating to react at least part of the silicon-germanium alloy layer with at least part of the metal layer to form a layer of germanosilicide alloy over the doped regions. The method of the present invention is particularly suitable for forming shallow source and drain regions for a field effect transistor, and self-aligned source and drain contacts therefor.
摘要翻译：掺杂的硅 - 锗合金被选择性地沉积在半导体衬底上，然后加热半导体衬底以将至少一些掺杂剂从硅 - 锗合金扩散到半导体衬底中，以在半导体衬底的表面形成掺杂区域。掺杂的硅 - 锗合金充当掺杂剂的扩散源，使得可以在半导体衬底的表面处形成浅掺杂的区域而不进行离子注入。还通过在掺杂的硅 - 锗合金层上形成金属层并加热以使至少部分硅 - 锗合金层与至少一部分金属层反应形成层，从而提供与掺杂区的高性能接触的锗硅酸盐合金。本发明的方法特别适用于形成用于场效应晶体管的浅源极和漏极区域，以及用于其的自对准源极和漏极接触。

7. 发明授权

US5242847A Selective deposition of doped silion-germanium alloy on semiconductor substrate 失效
标题翻译：掺杂硅 - 锗合金在半导体衬底上的选择性沉积
公开(公告)号：US5242847A
公开(公告)日：1993-09-07
申请号：US919735
申请日：1992-07-27
申请人： Mehmet C. Ozturk , Douglas T. Grider , Mahesh K. Sanganeria , Stanton P. Ashburn
发明人： Mehmet C. Ozturk , Douglas T. Grider , Mahesh K. Sanganeria , Stanton P. Ashburn
IPC分类号： H01L21/225 , H01L21/285 , H01L21/336 , H01L21/60
CPC分类号： H01L21/76897 , H01L21/2254 , H01L21/28518 , H01L29/41783 , H01L29/66545 , H01L29/66575 , H01L2924/0002 , Y10S148/058 , Y10S148/059
摘要： Doped silicon-germanium alloy is selectively deposited on a semiconductor substrate, and the semiconductor substrate is then heated to diffuse at least some of the dopant from the silicon-germanium alloy into the semiconductor substrate to form a doped region at the face of the semiconductor substrate. The doped silicon-germanium alloy acts as a diffusion source for the dopant, so that shallow doped, regions may be formed at the face of the semiconductor substrate without ion implantation. A high performance contact to the doped region is also provided by forming a metal layer on the doped silicon-germanium alloy layer and heating to react at least part of the silicon-germanium alloy layer with at least part of the metal layer to form a layer of germanosilicide alloy over the doped regions. The method of the present invention is particularly suitable for forming shallow source and drain regions for a field effect transistor, and self-aligned source and drain contacts therefor.
摘要翻译：掺杂的硅 - 锗合金被选择性地沉积在半导体衬底上，然后加热半导体衬底以将至少一些掺杂剂从硅 - 锗合金扩散到半导体衬底中，以在半导体衬底的表面形成掺杂区域。掺杂的硅 - 锗合金充当掺杂剂的扩散源，使得可以在半导体衬底的表面处形成浅掺杂的区域而不进行离子注入。还通过在掺杂的硅 - 锗合金层上形成金属层并加热以使至少部分硅 - 锗合金层与至少一部分金属层反应形成层，从而提供与掺杂区的高性能接触的锗硅酸盐合金。本发明的方法特别适用于形成用于场效应晶体管的浅源极和漏极区域，以及用于其的自对准源极和漏极接触。

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