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1. 发明授权

US5336903A Selective deposition of doped silicon-germanium alloy on semiconductor substrate, and resulting structures 失效
标题翻译：掺杂硅 - 锗合金在半导体衬底上的选择性沉积，以及所得结构
公开(公告)号：US5336903A
公开(公告)日：1994-08-09
申请号：US69030
申请日：1993-05-28
申请人： Mehmet C. Ozturk , Douglas T. Grider , Mahesh K. Sanganeria , Stanton P. Ashburn , Jimmie J. Wortman
发明人： Mehmet C. Ozturk , Douglas T. Grider , Mahesh K. Sanganeria , Stanton P. Ashburn , Jimmie J. Wortman
IPC分类号： H01L21/225 , H01L21/285 , H01L21/336 , H01L21/60 , H01L23/48
CPC分类号： H01L21/76897 , H01L21/2254 , H01L21/28518 , H01L29/41783 , H01L29/66545 , H01L29/66575 , H01L2924/0002 , Y10S148/058 , Y10S148/059
摘要： Doped silicon-germanium alloy is selectively deposited on a semiconductor substrate, and the semiconductor substrate is then heated to diffuse at least some of the dopant from the silicon-germanium alloy into the semiconductor substrate to form a doped region at the face of the semiconductor substrate. The doped silicon-germanium alloy acts as a diffusion source for the dopant, so that shallow doped, regions may be formed at the face of the semiconductor substrate without ion implantation. A high performance contact to the doped region is also provided by forming a metal layer on the doped silicon-germanium alloy layer and heating to react at least part of the silicon-germanium alloy layer with at least part of the metal layer to form a layer of germanosilicide alloy over the doped regions. The method of the present invention is particularly suitable for forming shallow source and drain regions for a field effect transistor, and self-aligned source and drain contacts therefor.
摘要翻译：掺杂的硅 - 锗合金被选择性地沉积在半导体衬底上，然后加热半导体衬底以将至少一些掺杂剂从硅 - 锗合金扩散到半导体衬底中，以在半导体衬底的表面形成掺杂区域。掺杂的硅 - 锗合金充当掺杂剂的扩散源，使得可以在半导体衬底的表面处形成浅掺杂的区域而不进行离子注入。还通过在掺杂的硅 - 锗合金层上形成金属层并加热以使至少部分硅 - 锗合金层与至少一部分金属层反应形成层，从而提供与掺杂区的高性能接触的锗硅酸盐合金。本发明的方法特别适用于形成用于场效应晶体管的浅源极和漏极区域，以及用于其的自对准源极和漏极接触。

2. 发明授权

US5242847A Selective deposition of doped silion-germanium alloy on semiconductor substrate 失效
标题翻译：掺杂硅 - 锗合金在半导体衬底上的选择性沉积
公开(公告)号：US5242847A
公开(公告)日：1993-09-07
申请号：US919735
申请日：1992-07-27
申请人： Mehmet C. Ozturk , Douglas T. Grider , Mahesh K. Sanganeria , Stanton P. Ashburn
发明人： Mehmet C. Ozturk , Douglas T. Grider , Mahesh K. Sanganeria , Stanton P. Ashburn
IPC分类号： H01L21/225 , H01L21/285 , H01L21/336 , H01L21/60
CPC分类号： H01L21/76897 , H01L21/2254 , H01L21/28518 , H01L29/41783 , H01L29/66545 , H01L29/66575 , H01L2924/0002 , Y10S148/058 , Y10S148/059
摘要： Doped silicon-germanium alloy is selectively deposited on a semiconductor substrate, and the semiconductor substrate is then heated to diffuse at least some of the dopant from the silicon-germanium alloy into the semiconductor substrate to form a doped region at the face of the semiconductor substrate. The doped silicon-germanium alloy acts as a diffusion source for the dopant, so that shallow doped, regions may be formed at the face of the semiconductor substrate without ion implantation. A high performance contact to the doped region is also provided by forming a metal layer on the doped silicon-germanium alloy layer and heating to react at least part of the silicon-germanium alloy layer with at least part of the metal layer to form a layer of germanosilicide alloy over the doped regions. The method of the present invention is particularly suitable for forming shallow source and drain regions for a field effect transistor, and self-aligned source and drain contacts therefor.
摘要翻译：掺杂的硅 - 锗合金被选择性地沉积在半导体衬底上，然后加热半导体衬底以将至少一些掺杂剂从硅 - 锗合金扩散到半导体衬底中，以在半导体衬底的表面形成掺杂区域。掺杂的硅 - 锗合金充当掺杂剂的扩散源，使得可以在半导体衬底的表面处形成浅掺杂的区域而不进行离子注入。还通过在掺杂的硅 - 锗合金层上形成金属层并加热以使至少部分硅 - 锗合金层与至少一部分金属层反应形成层，从而提供与掺杂区的高性能接触的锗硅酸盐合金。本发明的方法特别适用于形成用于场效应晶体管的浅源极和漏极区域，以及用于其的自对准源极和漏极接触。

3. 发明授权

US06326281B1 Integrated circuit isolation 有权
标题翻译：集成电路隔离
公开(公告)号：US06326281B1
公开(公告)日：2001-12-04
申请号：US09405278
申请日：1999-09-23
申请人： Katherine E. Violette , Rick L. Wise , Stanton P. Ashburn , Mahalingam Nandakumar , Douglas T. Grider
发明人： Katherine E. Violette , Rick L. Wise , Stanton P. Ashburn , Mahalingam Nandakumar , Douglas T. Grider
IPC分类号： H01L2136
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/31604 , H01L21/762
摘要： Silicon substrate isolation by epitaxial growth of silicon through windows in a mask made of silicon nitride (202) on silicon oxide (201) with the silicon oxide etched to undercut the silicon nitride; the mask is on a silicon substrate.
摘要翻译：通过在氧化硅（201）上由氮化硅（202）制成的掩模中的硅通过窗口外延生长硅氧化硅衬底，氧化硅被蚀刻以切割氮化硅; 掩模在硅衬底上。

4. 发明授权

US6030874A Doped polysilicon to retard boron diffusion into and through thin gate dielectrics 失效
标题翻译：掺杂的多晶硅以阻止硼扩散进入并通过薄栅极电介质
公开(公告)号：US6030874A
公开(公告)日：2000-02-29
申请号：US7060
申请日：1998-01-13
申请人： Douglas T. Grider , Stanton P. Ashburn , Katherine E. Violette , F. Scott Johnson
发明人： Douglas T. Grider , Stanton P. Ashburn , Katherine E. Violette , F. Scott Johnson
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/28035 , H01L21/2807 , H01L21/28176 , H01L21/32155 , H01L21/823842 , H01L29/4916 , H01L29/4966 , H01L21/28194 , H01L21/28202 , H01L29/518
摘要： An embodiment of the instant invention is a method of fabricating a semiconductor device which includes a dielectric layer situated between a conductive structure and a semiconductor substrate, the method comprising the steps of: forming the dielectric layer (layer 14) on the semiconductor substrate (substrate 12); forming the conductive structure (structure 18) on the dielectric layer; doping the conductive structure with boron; and doping the conductive structure with a dopant which inhibits the diffusion of boron. The semiconductor device may be a PMOS transistor or a capacitor. Preferably, the conductive structure is a gate structure. The dielectric layer is, preferably, comprised of a material selected from the group consisting of: an oxide, an oxide/oxide stack, an oxide/nitride stack, and an oxynitride. Preferably, the dopant which inhibits the diffusion of boron comprises at least one group III or group IV element. More specifically, it is preferably comprised of: carbon, germanium, and any combination thereof. Preferably, the steps of doping the conductive structure with boron and doping the conductive structure with a dopant which inhibits the diffusion of boron are accomplished substantially simultaneously, or the step of doping the conductive structure with boron is preformed prior to the step of doping the conductive structure with a dopant which inhibits the diffusion of boron are accomplished substantially simultaneously.
摘要翻译：本发明的实施例是一种制造半导体器件的方法，该半导体器件包括位于导电结构和半导体衬底之间的电介质层，该方法包括以下步骤：在半导体衬底（衬底）上形成介电层（层14） 12）; 在电介质层上形成导电结构（结构18）; 用硼掺杂导电结构; 并用抑制硼扩散的掺杂剂掺杂导电结构。半导体器件可以是PMOS晶体管或电容器。优选地，导电结构是栅极结构。电介质层优选由选自氧化物，氧化物/氧化物堆，氧化物/氮化物叠层和氧氮化物的材料组成。优选地，抑制硼扩散的掺杂剂包含至少一个III族或IV族元素。更具体地，其优选包括：碳，锗及其任何组合。优选地，用硼掺杂导电结构并用抑制硼的扩散的掺杂剂掺杂导电结构的步骤基本上同时实现，或者在掺杂导电的步骤之前预先形成用硼掺杂导电结构的步骤具有抑制硼扩散的掺杂剂的结构基本上同时完成。

5. 发明授权

US07244654B2 Drive current improvement from recessed SiGe incorporation close to gate 有权
标题翻译：驱动目前从嵌入式SiGe并入门口的改进
公开(公告)号：US07244654B2
公开(公告)日：2007-07-17
申请号：US10901568
申请日：2004-07-29
申请人： Pr Chidambaram , Douglas T. Grider , Brian A. Smith , Haowen Bu , Lindsey Hall
发明人： Pr Chidambaram , Douglas T. Grider , Brian A. Smith , Haowen Bu , Lindsey Hall
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/7842 , H01L29/7848
摘要： A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.
摘要翻译：形成晶体管的方法（100）包括在半导体主体上形成栅极结构（106,108），并形成与半导体本体中的栅极结构基本对齐的凹槽（112）。然后在凹槽中外延生长硅（114），随后在栅极结构的横向边缘上形成侧壁间隔物（118）。该方法通过在形成侧壁间隔物之后将源区和漏区注入半导体本体（120）中来继续。在凹槽中形成的硅锗位于晶体管沟道附近，用于向通道提供压缩应力，从而有助于改善PMOS型晶体管器件的载流子迁移率。

6. 发明授权

US07192894B2 High performance CMOS transistors using PMD liner stress 有权
标题翻译：使用PMD衬垫应力的高性能CMOS晶体管
公开(公告)号：US07192894B2
公开(公告)日：2007-03-20
申请号：US10833419
申请日：2004-04-28
申请人： Haowen Bu , Rajesh Khamankar , Douglas T. Grider
发明人： Haowen Bu , Rajesh Khamankar , Douglas T. Grider
IPC分类号： H01L21/31
CPC分类号： H01L29/7842 , H01L29/665 , H01L29/6659 , H01L29/78 , H01L29/7843 , Y10S438/954
摘要： A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.
摘要翻译：氮化硅层（110）形成在晶体管栅极（40）和源极和漏极区域（70）之上。所形成的氮化硅层（110）包括第一拉伸应力和高氢浓度。将所形成的氮化硅层（110）进行热退火，将第一拉伸应力转换成大于第一拉伸应力的第二拉伸应力。在热退火之后，氮化硅层（110）中的氢浓度大于12原子％。

7. 发明授权

US6093659A Selective area halogen doping to achieve dual gate oxide thickness on a wafer 失效
标题翻译：选择性区域卤素掺杂以在晶片上实现双栅极氧化物厚度
公开(公告)号：US6093659A
公开(公告)日：2000-07-25
申请号：US47713
申请日：1998-03-25
申请人： Douglas T. Grider , Vincent M. McNeil
发明人： Douglas T. Grider , Vincent M. McNeil
IPC分类号： H01L21/265 , H01L21/8234 , H01L21/37 , H01L21/469
CPC分类号： H01L21/823462 , H01L21/26506
摘要： A method for forming an integrated circuit having multiple gate oxide thicknesses is disclosed herein. The circuit (10) is processed up to gate oxide formation. A pattern (36) is then formed exposing areas of the circuit where a thinner gate oxide (20) is desired. These areas are then implanted with a halogen species such as fluorine or chlorine, to retard oxidation. The pattern (36) is then removed and an oxidation step is performed. Oxidation is selectively retarded in areas (14) previously doped with the halogen species but not in the remaining areas (12). Thus, a single oxidation step may be used to form gate oxides (20,22) of different thicknesses.
摘要翻译：本文公开了一种用于形成具有多个栅极氧化物厚度的集成电路的方法。电路（10）被加工成栅极氧化物形成。然后形成图案（36），暴露需要更薄栅极氧化物（20）的电路的区域。然后用卤素物质如氟或氯注入这些区域以延缓氧化。然后去除图案（36），并进行氧化步骤。在先前掺杂卤素物质的区域（14）中选择性地延迟氧化，但在其余区域（12）中不会氧化。因此，可以使用单个氧化步骤来形成不同厚度的栅极氧化物（20,22）。

8. 发明授权

US5585286A Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS device 失效
标题翻译：将具有受控量的惰性气体离子的半导体衬底植入以减少随后注入到衬底中的硼掺杂物的沟道和/或扩散以形成PMOS器件的P-LDD区
公开(公告)号：US5585286A
公开(公告)日：1996-12-17
申请号：US521795
申请日：1995-08-31
申请人： Sheldon Aronowitz , James Kimball , Yu-Lam Ho , Gobi Padmanabhan , Douglas T. Grider , Chi-Yi Kao
发明人： Sheldon Aronowitz , James Kimball , Yu-Lam Ho , Gobi Padmanabhan , Douglas T. Grider , Chi-Yi Kao
IPC分类号： H01L21/265 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/26506
摘要： A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant,, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.13 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.
摘要翻译：描述了一种工艺和产生的产品，用于控制在诸如硅衬底的单晶半导体衬底中形成PMOS器件的轻掺杂漏极（LDD）区域的P区中的硼掺杂剂的沟道化和/或扩散。硼掺杂剂的通道和/或扩散通过在用硼掺杂剂注入之前用惰性气体离子（例如氩离子）注入该区域，剂量至少等于注入硼的后续剂量掺杂剂，但不超过与硅衬底中注入约3×1013氩离子/ cm 2相当的量，由此抑制随后注入的硼掺杂剂的通道化和扩散，而不会使半导体衬底非晶化。

9. 发明授权

US07670892B2 Nitrogen based implants for defect reduction in strained silicon 有权
标题翻译：用于应变硅缺陷还原的氮基植入物
公开(公告)号：US07670892B2
公开(公告)日：2010-03-02
申请号：US11268040
申请日：2005-11-07
申请人： Srinivasan Chakravarthi , Pr Chidambaram , Rajesh Khamankar , Haowen Bu , Douglas T. Grider
发明人： Srinivasan Chakravarthi , Pr Chidambaram , Rajesh Khamankar , Haowen Bu , Douglas T. Grider
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7833 , H01L21/26506 , H01L29/665 , H01L29/6659 , H01L29/7843
摘要： A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer.
摘要翻译：晶体管制造在半导体衬底上，其中衬底的屈服强度或弹性得到增强或适应。应变感应层形成在晶体管上以向其施加应变以改变晶体管工作特性，更具体地说，增强晶体管内的载流子迁移率。增强载流子迁移率允许晶体管尺寸减小，同时也允许晶体管根据需要进行操作。然而，与制造晶体管相关的高应变和温度导致有害的塑性变形。因此，硅衬底的屈服强度通过将氮掺入到衬底中，更具体地掺入晶体管的源极/漏极延伸区域和/或源极/漏极区域来适应。在晶体管制造期间，可以通过将其作为源极/漏极延伸区域形成和/或源极/漏极区域形成的一部分来添加来将氮容易地并入。由于应变诱导层，衬底的增强的屈服强度减轻了晶体管的塑性变形。

10. 发明授权

US06632718B1 Disposable spacer technology for reduced cost CMOS processing 有权
标题翻译：一次性间隔技术，可降低CMOS加工成本
公开(公告)号：US06632718B1
公开(公告)日：2003-10-14
申请号：US09339444
申请日：1999-06-24
申请人： Douglas T. Grider , Terence Breedijk
发明人： Douglas T. Grider , Terence Breedijk
IPC分类号： H01L21336
CPC分类号： H01L21/823864
摘要： A method of fabricating a CMOS transistor using a silicon germanium disposable spacer (114) for the source/drain implant. After gate etch, silicon germanium disposable spacers (114) are formed. A NMOS resist pattern (116) is formed exposing the NMOS regions (120) and the n-type source/drain implant is performed. The disposable spacers (114) in the NMOS regions are removed and, with the NMOS resist mask (116) still in place, the LDD/MDD implant is performed. The process may then be repeated for the PMOS regions (122).
摘要翻译：用于源极/漏极注入的制造使用硅锗一次性间隔物（ 114 ）的CMOS晶体管的方法。在栅极蚀刻之后，形成硅锗一次性间隔物（ 114 ）。形成暴露NMOS区域（ 120 ）的NMOS抗蚀剂图案（ 116 ）和n型源极/漏极进行植入。去除NMOS区域中的一次性间隔物（ 114 ）仍然存在于NMOS抗蚀剂掩模（ 116 ）位置，执行LDD / MDD植入。然后可以对PMOS区域重复该过程（ 122 ）。

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