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1. 发明申请

US20070122965A1 STRESS ENGINEERING USING DUAL PAD NITRIDE WITH SELECTIVE SOI DEVICE ARCHITECTURE 失效
公开(公告)号：US20070122965A1
公开(公告)日：2007-05-31
申请号：US11668790
申请日：2007-01-30
申请人： Dureseti Chidambarrao , William Henson , Kern Rim , William Wille
发明人： Dureseti Chidambarrao , William Henson , Kern Rim , William Wille
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/0653 , H01L29/7842
摘要： A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of stress are achieved when the method is applied to a selective SOI architecture.

2. 发明申请

US20070069294A1 STRESS ENGINEERING USING DUAL PAD NITRIDE WITH SELECTIVE SOI DEVICE ARCHITECTURE 有权
标题翻译：使用具有选择性SOI器件结构的双层氮化物的应力工程
公开(公告)号：US20070069294A1
公开(公告)日：2007-03-29
申请号：US11162953
申请日：2005-09-29
申请人： Dureseti Chidambarrao , William Henson , Kern Rim , William Wille
发明人： Dureseti Chidambarrao , William Henson , Kern Rim , William Wille
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/0653 , H01L29/7842
摘要： A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of stress are achieved when the method is applied to a selective SOI architecture.
摘要翻译：描述了一种使用高应力氮化物膜与选择性绝缘体上半导体（SOI）器件结构结合的在不同导电性的MOS晶体管的沟道中应力的方法。描述了在浅沟槽隔离（STI）工艺中使用压缩和拉伸氮化物膜的方法。当将该方法应用于选择性SOI结构时，实现高应力值。

3. 发明申请

US20070212861A1 LASER SURFACE ANNEALING OF ANTIMONY DOPED AMORPHIZED SEMICONDUCTOR REGION 审中-公开
标题翻译：激光表面抛光抗微生物聚合半导体器件领域
公开(公告)号：US20070212861A1
公开(公告)日：2007-09-13
申请号：US11308108
申请日：2006-03-07
申请人： Dureseti Chidambarrao , Sameer Jain , William Henson , Kern Rim
发明人： Dureseti Chidambarrao , Sameer Jain , William Henson , Kern Rim
IPC分类号： H01L21/425
CPC分类号： H01L21/26506 , H01L21/268 , H01L29/665 , H01L29/6659 , H01L29/66772 , H01L29/78621 , H01L29/78654
摘要： A sheet resistance stabilized recrystallized antimony doped region may be formed within a semiconductor substrate by annealing a corresponding antimony doped amorphized region at a temperature from about 1050° C. to about 1400° C. for a time period from about 0.1 to about 10 milliseconds. Preferably, a laser surface treatment is used. The laser surface treatment preferably uses a solid phase epitaxy. In addition, the antimony doped region may be co-doped with at least one of a phosphorus dopant and an arsenic dopant. The antimony dopant and the laser surface treatment lend sheet resistance stability that is otherwise absent when forming solely phosphorus and/or arsenic doped regions.
摘要翻译：通过在约1050℃至约1400℃的温度下退火相应的锑掺杂非晶化区域约0.1至约10毫秒的时间，可以在半导体衬底内形成薄片电阻稳定的再结晶锑掺杂区。优选地，使用激光表面处理。激光表面处理优选使用固相外延。此外，锑掺杂区域可以与磷掺杂剂和砷掺杂剂中的至少一种共掺杂。当仅形成磷和/或砷掺杂区域时，锑掺杂剂和激光表面处理提供了薄片电阻稳定性，否则不存在。

4. 发明申请

US20070254423A1 HIGH PERFORMANCE STRESS-ENHANCE MOSFET AND METHOD OF MANUFACTURE 有权
标题翻译：高性能应力增强MOSFET及其制造方法
公开(公告)号：US20070254423A1
公开(公告)日：2007-11-01
申请号：US11380689
申请日：2006-04-28
申请人： Dureseti Chidambarrao , Ricardo Donaton , William Henson , Kern Rim
发明人： Dureseti Chidambarrao , Ricardo Donaton , William Henson , Kern Rim
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807 , H01L27/1203 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.
摘要翻译：本发明涉及半导体结构和制造方法，更具体地说涉及一种CMOS器件，其具有嵌入在PFET的栅极和源极/漏极区域中以及PFET和NFET沟道的变化厚度的应力诱导材料。在一个实施例中，该结构通过改变相应于NFET或PFET的顶部硅层的厚度来增强器件性能。

5. 发明申请

US20070254422A1 HIGH PERFORMANCE STRESS-ENHANCE MOSFET AND METHOD OF MANUFACTURE 有权
标题翻译：高性能应力增强MOSFET及其制造方法
公开(公告)号：US20070254422A1
公开(公告)日：2007-11-01
申请号：US11380688
申请日：2006-04-28
申请人： Dureseti Chidambarrao , Ricardo Donaton , William Henson , Kern Rim
发明人： Dureseti Chidambarrao , Ricardo Donaton , William Henson , Kern Rim
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： A semiconductor structure and method of manufacturing and more particularly a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET. The PFET region and the NFET region having a different sized gate to vary the device performance of the NFET and the PFET.
摘要翻译：一种半导体结构和制造方法，更具体地说是具有嵌入在PFET的栅极和源极/漏极区域中的应力诱导材料的CMOS器件。 PFET区域和NFET区域具有不同尺寸的栅极，以改变NFET和PFET的器件性能。

6. 发明授权

US09059316B2 Structure and method for mobility enhanced MOSFETs with unalloyed silicide 有权
标题翻译：具有非合金化硅化物的迁移率增强型MOSFET的结构和方法
公开(公告)号：US09059316B2
公开(公告)日：2015-06-16
申请号：US13397860
申请日：2012-02-16
申请人： Yaocheng Liu , Dureseti Chidambarrao , Oleg Gluschenkov , Judson R. Holt , Renee T. Mo , Kern Rim
发明人： Yaocheng Liu , Dureseti Chidambarrao , Oleg Gluschenkov , Judson R. Holt , Renee T. Mo , Kern Rim
IPC分类号： H01L21/8238 , H01L21/768 , H01L21/84 , H01L27/12 , H01L29/66 , H01L29/78 , H01L27/32 , H01L29/165
CPC分类号： H01L21/823864 , H01L21/76886 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L27/3279 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
摘要翻译：虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是为了通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。本发明提供了在放置在半导体衬底上的这种硅合金表面上提供非合金硅化物的结构和方法。这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。

7. 发明申请

US20110147885A1 FORMATION OF IMPROVED SOI SUBSTRATES USING BULK SEMICONDUCTOR WAFERS 有权
标题翻译：使用块状半导体波形形成改进的SOI衬底
公开(公告)号：US20110147885A1
公开(公告)日：2011-06-23
申请号：US13037608
申请日：2011-03-01
申请人： William K. Henson , Dureseti Chidambarrao , Kern Rim , Hsingjen Wann , Hung Y. Ng
发明人： William K. Henson , Dureseti Chidambarrao , Kern Rim , Hsingjen Wann , Hung Y. Ng
IPC分类号： H01L23/58
CPC分类号： H01L21/764 , H01L21/76283
摘要： The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.
摘要翻译：本发明涉及具有一个或多个器件区域的绝缘体上半导体（SOI）衬底。每个器件区域至少包括基底半导体衬底层和其间设置有掩埋绝缘体层的半导体器件层，而半导体器件层由一个或多个垂直绝缘柱支撑。垂直绝缘柱各自优选地具有在基底半导体衬底层和半导体器件层之间延伸的凸缘。本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，半导体器件层通过气隙与基底半导体衬底层间隔开并由一个或多个垂直绝缘柱支撑。气隙优选通过选择性地去除位于基底半导体衬底层和半导体器件层之间的牺牲层来形成。

8. 发明授权

US07615418B2 High performance stress-enhance MOSFET and method of manufacture 有权
标题翻译：高性能应力增强型MOSFET及其制造方法
公开(公告)号：US07615418B2
公开(公告)日：2009-11-10
申请号：US11380688
申请日：2006-04-28
申请人： Dureseti Chidambarrao , Ricardo A. Donaton , William K. Henson , Kern Rim
发明人： Dureseti Chidambarrao , Ricardo A. Donaton , William K. Henson , Kern Rim
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： A semiconductor structure and method of manufacturing and more particularly a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET. The PFET region and the NFET region having a different sized gate to vary the device performance of the NFET and the PFET.
摘要翻译：一种半导体结构和制造方法，更具体地说是具有嵌入在PFET的栅极和源极/漏极区域中的应力诱导材料的CMOS器件。 PFET区域和NFET区域具有不同尺寸的栅极，以改变NFET和PFET的器件性能。

9. 发明申请

US20080283918A1 Ultra Thin Channel (UTC) MOSFET Structure Formed on BOX Regions Having Different Depths and Different Thicknesses Beneath the UTC and SourceDrain Regions and Method of Manufacture Thereof 有权
标题翻译：超薄通道（UTC）MOSFET结构形成在具有不同深度和不同厚度的BOX区域之下，UTC和SourceDrain区域及其制造方法
公开(公告)号：US20080283918A1
公开(公告)日：2008-11-20
申请号：US12166285
申请日：2008-07-01
申请人： Kangguo Cheng , Dureseti Chidambarrao , Brian Joseph Greene , Jack A. Mandelman , Kern Rim
发明人： Kangguo Cheng , Dureseti Chidambarrao , Brian Joseph Greene , Jack A. Mandelman , Kern Rim
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L21/2652 , H01L21/3003 , H01L29/1083 , H01L29/66545 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78603 , H01L29/78621 , H01L29/78696
摘要： A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. A UT SOI channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A BOX1 region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a BOX2 region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.
摘要翻译： MOSFET结构包括平面半导体衬底，栅极电介质和栅极。 UT SOI沟道延伸到衬底的顶表面下方的第一深度，并且与栅极自对准并且横向共延伸。源极 - 漏极区域延伸到大于顶部表面下方的第一深度的第二深度，并且与UT沟道区域自对准。 BOX 1区域跨越整个结构延伸，并且从第二深度垂直延伸到顶表面下方的第三深度。在UT通道区域下面的BOX 2区域的上部与栅极自对准并且与栅极横向共同延伸，并且从第一深度垂直延伸到顶表面下方的第三深度，并且其中第三深度大于第二个深度。

10. 发明授权

US07452784B2 Formation of improved SOI substrates using bulk semiconductor wafers 有权
标题翻译：使用块状半导体晶片形成改进的SOI衬底
公开(公告)号：US07452784B2
公开(公告)日：2008-11-18
申请号：US11420279
申请日：2006-05-25
申请人： William K. Henson , Dureseti Chidambarrao , Kern Rim , Hsingjen Wann , Hung Y. Ng
发明人： William K. Henson , Dureseti Chidambarrao , Kern Rim , Hsingjen Wann , Hung Y. Ng
IPC分类号： H01L21/76
CPC分类号： H01L21/764 , H01L21/76283
摘要： The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.
摘要翻译：本发明涉及具有一个或多个器件区域的绝缘体上半导体（SOI）衬底。每个器件区域至少包括基底半导体衬底层和其间设置有掩埋绝缘体层的半导体器件层，而半导体器件层由一个或多个垂直绝缘柱支撑。垂直绝缘柱各自优选地具有在基底半导体衬底层和半导体器件层之间延伸的凸缘。本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，半导体器件层通过气隙与基底半导体衬底层间隔开并由一个或多个垂直绝缘柱支撑。气隙优选通过选择性地去除位于基底半导体衬底层和半导体器件层之间的牺牲层来形成。

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