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1. 发明授权

US08445974B2 Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same 有权
标题翻译：包括倾斜阈值电压调节材料层的不对称FET及其制造方法
公开(公告)号：US08445974B2
公开(公告)日：2013-05-21
申请号：US12683602
申请日：2010-01-07
申请人： Dureseti Chidambarrao , Sunfei Fang , Yue Liang , Xiaojun Yu , Jun Yuan
发明人： Dureseti Chidambarrao , Sunfei Fang , Yue Liang , Xiaojun Yu , Jun Yuan
IPC分类号： H01L21/02
CPC分类号： H01L27/092 , H01L21/823857 , H01L29/42368 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66583 , H01L29/78
摘要： A semiconductor structure is provided that includes at least one asymmetric gate stack located on a surface of a semiconductor structure. The at least one asymmetric gate stack includes, from bottom to top, a high k gate dielectric, a sloped threshold voltage adjusting material layer and a gate conductor. A method of forming such a semiconductor structure is also provided in which a line of sight deposition process is used in forming the sloped threshold voltage adjusting material layer in which the deposition is tilted within respect to a horizontal surface of a semiconductor structure.
摘要翻译：提供一种半导体结构，其包括位于半导体结构的表面上的至少一个非对称栅极堆叠。所述至少一个非对称栅极堆叠包括从底部到顶部的高k栅极电介质，倾斜阈值电压调节材料层和栅极导体。还提供了一种形成这种半导体结构的方法，其中在形成相对于半导体结构的水平表面倾斜的沉积倾斜的阈值电压调节材料层中使用视线沉积工艺。

2. 发明授权

US08629022B2 Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same 有权
标题翻译：包括倾斜阈值电压调节材料层的不对称FET及其制造方法
公开(公告)号：US08629022B2
公开(公告)日：2014-01-14
申请号：US13420730
申请日：2012-03-15
申请人： Dureseti Chidambarrao , Sunfei Fang , Yue Liang , Xiaojun Yu , Jun Yuan
发明人： Dureseti Chidambarrao , Sunfei Fang , Yue Liang , Xiaojun Yu , Jun Yuan
IPC分类号： H01L21/8234
CPC分类号： H01L27/092 , H01L21/823857 , H01L29/42368 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66583 , H01L29/78
摘要： A method of forming a semiconductor structure is provided. The method includes providing a structure including at least one dummy gate region located on a surface of a semiconductor substrate and a dielectric material layer located on sidewalls of the at least one dummy gate region. Next, a portion of the dummy gate region is removed exposing an underlying high k gate dielectric. A sloped threshold voltage adjusting material layer is then formed on an upper surface of the high k gate dielectric, and thereafter a gate conductor is formed atop the sloped threshold voltage adjusting material layer.
摘要翻译：提供一种形成半导体结构的方法。该方法包括提供包括位于半导体衬底的表面上的至少一个伪栅极区域和位于至少一个虚拟栅极区域的侧壁上的介电材料层的结构。接下来，去除暴露下面的高k栅极电介质的虚拟栅极区域的一部分。然后在高k栅极电介质的上表面上形成倾斜的阈值电压调节材料层，然后在倾斜的阈值电压调节材料层的顶部形成栅极导体。

3. 发明申请

US20120171831A1 ASYMMETRIC FET INCLUDING SLOPED THRESHOLD VOLTAGE ADJUSTING MATERIAL LAYER AND METHOD OF FABRICATING SAME 有权
标题翻译：包括斜面电压调节材料层的不对称FET及其制造方法
公开(公告)号：US20120171831A1
公开(公告)日：2012-07-05
申请号：US13420730
申请日：2012-03-15
申请人： Dureseti Chidambarrao , Sunfei Fang , Yue Liang , Xiaojun Yu , Jun Yuan
发明人： Dureseti Chidambarrao , Sunfei Fang , Yue Liang , Xiaojun Yu , Jun Yuan
IPC分类号： H01L21/336 , H01L21/283
CPC分类号： H01L27/092 , H01L21/823857 , H01L29/42368 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66583 , H01L29/78
摘要： A method of forming a semiconductor structure is provided. The method includes providing a structure including at least one dummy gate region located on a surface of a semiconductor substrate and a dielectric material layer located on sidewalls of the at least one dummy gate region. Next, a portion of the dummy gate region is removed exposing an underlying high k gate dielectric. A sloped threshold voltage adjusting material layer is then formed on an upper surface of the high k gate dielectric, and thereafter a gate conductor is formed atop the sloped threshold voltage adjusting material layer.
摘要翻译：提供一种形成半导体结构的方法。该方法包括提供包括位于半导体衬底的表面上的至少一个伪栅极区域和位于该至少一个虚拟栅极区域的侧壁上的介电材料层的结构。接下来，去除暴露下面的高k栅极电介质的虚拟栅极区域的一部分。然后在高k栅极电介质的上表面上形成倾斜的阈值电压调节材料层，然后在倾斜的阈值电压调节材料层的顶部形成栅极导体。

4. 发明申请

US20110163385A1 ASYMMETRIC FET INCLUDING SLOPED THRESHOLD VOLTAGE ADJUSTING MATERIAL LAYER AND METHOD OF FABRICATING SAME 有权
标题翻译：包括斜面电压调节材料层的不对称FET及其制造方法
公开(公告)号：US20110163385A1
公开(公告)日：2011-07-07
申请号：US12683602
申请日：2010-01-07
申请人： Dureseti Chidambarrao , Sunfei Fang , Yue Liang , Xiaojun Yu , Jun Yuan
发明人： Dureseti Chidambarrao , Sunfei Fang , Yue Liang , Xiaojun Yu , Jun Yuan
IPC分类号： H01L27/092 , H01L29/78 , H01L27/088 , H01L21/28
CPC分类号： H01L27/092 , H01L21/823857 , H01L29/42368 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66583 , H01L29/78
摘要： A semiconductor structure is provided that includes at least one asymmetric gate stack located on a surface of a semiconductor structure. The at least one asymmetric gate stack includes, from bottom to top, a high k gate dielectric, a sloped threshold voltage adjusting material layer and a gate conductor. A method of forming such a semiconductor structure is also provided in which a line of sight deposition process is used in forming the sloped threshold voltage adjusting material layer in which the deposition is tilted within respect to a horizontal surface of a semiconductor structure.
摘要翻译：提供一种半导体结构，其包括位于半导体结构的表面上的至少一个非对称栅极堆叠。所述至少一个非对称栅极堆叠包括从底部到顶部的高k栅极电介质，倾斜阈值电压调节材料层和栅极导体。还提供了一种形成这种半导体结构的方法，其中在形成相对于半导体结构的水平表面倾斜的沉积倾斜的阈值电压调节材料层中使用视线沉积工艺。

5. 发明申请

US20100289085A1 Asymmetric Semiconductor Devices and Method of Fabricating 失效
标题翻译：不对称半导体器件及其制造方法
公开(公告)号：US20100289085A1
公开(公告)日：2010-11-18
申请号：US12465818
申请日：2009-05-14
申请人： Jun Yuan , Dureseti Chidambarrao , Sunfei Fang , Haizhou Yin , Yue Liang , Xiaojun Yu
发明人： Jun Yuan , Dureseti Chidambarrao , Sunfei Fang , Haizhou Yin , Yue Liang , Xiaojun Yu
IPC分类号： H01L27/092 , H01L29/78 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/28114 , H01L21/28132 , H01L29/42368 , H01L29/42376 , H01L29/513 , H01L29/6659 , H01L29/7835 , Y10S257/90
摘要： A semiconductor structure is provided that includes an asymmetric gate stack located on a surface of high k gate dielectric. The asymmetric gate stack includes a first portion and a second portion, wherein the first portion has a different threshold voltage than the second portion. The first portion of the inventive asymmetric gate stack includes, from bottom to top, a threshold voltage adjusting material and at least a first conductive spacer, while the second portion of the inventive asymmetric gate stack includes at least a second conductive spacer over the gate dielectric. In some embodiments, the second conductive spacer is in direct contact with the underlying high k gate dielectric, while in other embodiments, in which the first and second conductive spacers are comprised of different conductive materials, the base of the second conductive spacer is in direct contact with the threshold adjusting material.
摘要翻译：提供了一种半导体结构，其包括位于高k栅极电介质的表面上的非对称栅极堆叠。非对称栅极堆叠包括第一部分和第二部分，其中第一部分具有与第二部分不同的阈值电压。本发明的不对称栅极堆叠的第一部分包括从底部到顶部的阈值电压调节材料和至少第一导电间隔物，而本发明的不对称栅极堆叠的第二部分包括在栅极电介质上的至少第二导电间隔物。在一些实施例中，第二导电间隔物与下面的高k栅极电介质直接接触，而在其它实施例中，第一和第二导电间隔物由不同的导电材料构成，第二导电间隔物的基底直接接触阈值调节材料。

6. 发明授权

US07999332B2 Asymmetric semiconductor devices and method of fabricating 失效
标题翻译：非对称半导体器件及其制造方法
公开(公告)号：US07999332B2
公开(公告)日：2011-08-16
申请号：US12465818
申请日：2009-05-14
申请人： Jun Yuan , Dureseti Chidambarrao , Sunfei Fang , Yue Liang , Haizhou Yin , Xiaojun Yu
发明人： Jun Yuan , Dureseti Chidambarrao , Sunfei Fang , Yue Liang , Haizhou Yin , Xiaojun Yu
IPC分类号： H01L21/70
CPC分类号： H01L29/4983 , H01L21/28114 , H01L21/28132 , H01L29/42368 , H01L29/42376 , H01L29/513 , H01L29/6659 , H01L29/7835 , Y10S257/90
摘要： A semiconductor structure is provided that includes an asymmetric gate stack located on a surface of high k gate dielectric. The asymmetric gate stack includes a first portion and a second portion, wherein the first portion has a different threshold voltage than the second portion. The first portion of the inventive asymmetric gate stack includes, from bottom to top, a threshold voltage adjusting material and at least a first conductive spacer, while the second portion of the inventive asymmetric gate stack includes at least a second conductive spacer over the gate dielectric. In some embodiments, the second conductive spacer is in direct contact with the underlying high k gate dielectric, while in other embodiments, in which the first and second conductive spacers are comprised of different conductive materials, the base of the second conductive spacer is in direct contact with the threshold adjusting material.
摘要翻译：提供了一种半导体结构，其包括位于高k栅极电介质的表面上的非对称栅极堆叠。非对称栅极堆叠包括第一部分和第二部分，其中第一部分具有与第二部分不同的阈值电压。本发明的不对称栅极堆叠的第一部分包括从底部到顶部的阈值电压调节材料和至少第一导电间隔物，而本发明的不对称栅极堆叠的第二部分包括在栅极电介质上的至少第二导电间隔物。在一些实施例中，第二导电间隔物与下面的高k栅极电介质直接接触，而在其它实施例中，第一和第二导电间隔物由不同的导电材料构成，第二导电间隔物的基底直接接触阈值调节材料。

7. 发明申请

US20130168776A1 Complementary Metal Oxide Semiconductor (CMOS) Device Having Gate Structures Connected By A Metal Gate Conductor 有权
标题翻译：互补金属氧化物半导体（CMOS）器件，其栅极结构由金属栅极导体连接
公开(公告)号：US20130168776A1
公开(公告)日：2013-07-04
申请号：US13342435
申请日：2012-01-03
申请人： Yue Liang , Dureseti Chidambarrao , Brian J. Greene , William K. Henson , Unoh Kwon , Shreesh Narasimha , Xiaojun Yu
发明人： Yue Liang , Dureseti Chidambarrao , Brian J. Greene , William K. Henson , Unoh Kwon , Shreesh Narasimha , Xiaojun Yu
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823871 , H01L21/28079 , H01L21/30604 , H01L21/76224 , H01L21/823878 , H01L29/4958
摘要： A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.
摘要翻译：一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。

8. 发明申请

US20130126976A1 SELECTIVE PARTIAL GATE STACK FOR IMPROVED DEVICE ISOLATION 失效
标题翻译：用于改进设备隔离的选择性部分门锁
公开(公告)号：US20130126976A1
公开(公告)日：2013-05-23
申请号：US13298783
申请日：2011-11-17
申请人： Xiaojun Yu , Dureseti Chidambarrao , Brian J. Greene , Yue Liang
发明人： Xiaojun Yu , Dureseti Chidambarrao , Brian J. Greene , Yue Liang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823871 , H01L21/823842 , H01L21/823878 , H01L27/092
摘要： A complementary metal oxide semiconductor (CMOS) device that may include a substrate having a first active region and a second active region that are separated from one another by an isolation region. An n-type semiconductor device is present on the first active region that includes a first gate structure having a first gate dielectric layer and an n-type work function metal layer, wherein the n-type work function layer does not extend onto the isolation region. A p-type semiconductor device is present on the second active region that includes a second gate structure having a second gate dielectric layer and a p-type work function metal layer, wherein the p-type work function layer does not extend onto the isolation region. A connecting gate structure extends across the isolation region into direct contact with the first gate structure and the second gate structure.
摘要翻译：互补金属氧化物半导体（CMOS）器件，其可以包括具有通过隔离区彼此分离的第一有源区和第二有源区的衬底。在第一有源区上存在n型半导体器件，其包括具有第一栅极介电层和n型功函数金属层的第一栅极结构，其中n型功函数层不延伸到隔离区。 p型半导体器件存在于第二有源区，其包括具有第二栅极介电层和p型功函数金属层的第二栅极结构，其中p型功函数层不延伸到隔离区。连接栅极结构跨越隔离区域延伸成与第一栅极结构和第二栅极结构直接接触。

9. 发明授权

US08803243B2 Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor 有权
标题翻译：具有通过金属栅极导体连接的栅极结构的互补金属氧化物半导体（CMOS）器件
公开(公告)号：US08803243B2
公开(公告)日：2014-08-12
申请号：US13342435
申请日：2012-01-03
申请人： Yue Liang , Dureseti Chidambarrao , Brian J. Greene , William K. Henson , Unoh Kwon , Shreesh Narasimha , Xiaojun Yu
发明人： Yue Liang , Dureseti Chidambarrao , Brian J. Greene , William K. Henson , Unoh Kwon , Shreesh Narasimha , Xiaojun Yu
IPC分类号： H01L21/70
CPC分类号： H01L21/823871 , H01L21/28079 , H01L21/30604 , H01L21/76224 , H01L21/823878 , H01L29/4958
摘要： A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.
摘要翻译：一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。

10. 发明授权

US08476706B1 CMOS having a SiC/SiGe alloy stack 有权
标题翻译：具有SiC / SiGe合金叠层的CMOS
公开(公告)号：US08476706B1
公开(公告)日：2013-07-02
申请号：US13343472
申请日：2012-01-04
申请人： Dureseti Chidambarrao , Brian J. Greene , Yue Liang , Xiaojun Yu
发明人： Dureseti Chidambarrao , Brian J. Greene , Yue Liang , Xiaojun Yu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/8238 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66651
摘要： A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer.
摘要翻译：通过在硅表面上沉积硅碳合金层，在硅表面上提供硅的δ掺杂，硅表面可以是体硅衬底的水平表面，绝缘体上半导体衬底的顶部硅层的水平表面，或硅片的垂直表面。可以通过在PFET区域中而不是在NFET区域中选择性地沉积硅锗合金层来区分p型场效应晶体管（PFET）区域和n型场效应晶体管（NFET）区域。 PFET区域中的硅锗合金层可以覆盖或叠加在硅碳合金层上。普通材料堆叠可用于PFET和NFET的栅极电介质和栅电极。 PFET和NFET的每个沟道包括硅碳合金层，并且通过硅锗层的存在或不存在来区分。

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