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    • 10. 发明申请
    • SELECTIVE PARTIAL GATE STACK FOR IMPROVED DEVICE ISOLATION
    • 用于改进设备隔离的选择性部分门锁
    • US20130126976A1
    • 2013-05-23
    • US13298783
    • 2011-11-17
    • Xiaojun YuDureseti ChidambarraoBrian J. GreeneYue Liang
    • Xiaojun YuDureseti ChidambarraoBrian J. GreeneYue Liang
    • H01L27/092H01L21/8238
    • H01L21/823871H01L21/823842H01L21/823878H01L27/092
    • A complementary metal oxide semiconductor (CMOS) device that may include a substrate having a first active region and a second active region that are separated from one another by an isolation region. An n-type semiconductor device is present on the first active region that includes a first gate structure having a first gate dielectric layer and an n-type work function metal layer, wherein the n-type work function layer does not extend onto the isolation region. A p-type semiconductor device is present on the second active region that includes a second gate structure having a second gate dielectric layer and a p-type work function metal layer, wherein the p-type work function layer does not extend onto the isolation region. A connecting gate structure extends across the isolation region into direct contact with the first gate structure and the second gate structure.
    • 互补金属氧化物半导体(CMOS)器件,其可以包括具有通过隔离区彼此分离的第一有源区和第二有源区的衬底。 在第一有源区上存在n型半导体器件,其包括具有第一栅极介电层和n型功函数金属层的第一栅极结构,其中n型功函数层不延伸到隔离区 。 p型半导体器件存在于第二有源区,其包括具有第二栅极介电层和p型功函数金属层的第二栅极结构,其中p型功函数层不延伸到隔离区 。 连接栅极结构跨越隔离区域延伸成与第一栅极结构和第二栅极结构直接接触。