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1. 发明授权

US07256121B2 Contact resistance reduction by new barrier stack process 有权
标题翻译：通过新的阻挡层叠工艺降低接触电阻
公开(公告)号：US07256121B2
公开(公告)日：2007-08-14
申请号：US11002935
申请日：2004-12-02
申请人： Duofeng Yue , Stephan Grunow , Satyavolu S. Papa Rao , Noel M. Russell , Montray Leavy
发明人： Duofeng Yue , Stephan Grunow , Satyavolu S. Papa Rao , Noel M. Russell , Montray Leavy
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/2855 , H01L21/76844 , H01L21/76846 , H01L21/76862 , H01L21/76865
摘要： The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.
摘要翻译：本发明提供了一种在半导体衬底100上形成互连的方法。该方法包括在开口130的内表面上形成开口230，沉积物在开口130的顶部附近形成折入轮廓。势垒230的一部分被蚀刻，其移除阻挡物230的至少一部分以减少折返轮廓。蚀刻还去除了开口130底部的阻挡层230的至少一部分。

2. 发明申请

US20060121724A1 Contact resistance reduction by new barrier stack process 有权
标题翻译：通过新的阻挡层叠工艺降低接触电阻
公开(公告)号：US20060121724A1
公开(公告)日：2006-06-08
申请号：US11002935
申请日：2004-12-02
申请人： Duofeng Yue , Stephan Grunow , Satyavolu Papa Rao , Noel Russell , Montray Leavy
发明人： Duofeng Yue , Stephan Grunow , Satyavolu Papa Rao , Noel Russell , Montray Leavy
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/2855 , H01L21/76844 , H01L21/76846 , H01L21/76862 , H01L21/76865
摘要： The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.
摘要翻译：本发明提供了一种在半导体衬底100上形成互连的方法。该方法包括在开口130的内表面上形成开口230，沉积物在开口130的顶部附近形成折入轮廓。势垒230的一部分被蚀刻，其移除阻挡物230的至少一部分以减少折返轮廓。蚀刻还去除了开口130底部的阻挡物230层的至少一部分。

3. 发明申请

US20100032801A1 CAPACITOR FORMED IN INTERLEVEL DIELECTRIC LAYER 审中-公开
标题翻译：电容式电介质层形成电容器
公开(公告)号：US20100032801A1
公开(公告)日：2010-02-11
申请号：US12538735
申请日：2009-08-10
申请人： Jarvis Benjamin Jacobs , Max Walthour Lippitt , Scott Kelly Montgomery , Robert William Murto , Byron Lovell Williams , Duofeng Yue
发明人： Jarvis Benjamin Jacobs , Max Walthour Lippitt , Scott Kelly Montgomery , Robert William Murto , Byron Lovell Williams , Duofeng Yue
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/91 , H01L23/5223 , H01L27/0207 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2924/13091 , H01L2924/19105 , H01L2924/00014 , H01L2924/00
摘要： An capacitor is formed in an interlevel dielectric (ILD) layer of the integrated circuit (IC) by etching vertical trenches through the ILD and depositing conformal layers of a bottom electrode metal, a capacitor dielectric and a top electrode metal. The capacitor can attain a capacitance density of 20 nanofarads/mm2 in a 1 micron thick ILD, and is suitable for replacing external capacitors in a circuit containing the IC with external circuit elements. The disclosed fabrication methods are compatible with aluminum or copper interconnects.
摘要翻译：通过蚀刻通过ILD的垂直沟槽并沉积底部电极金属，电容器电介质和顶部电极金属的共形层，在集成电路（IC）的层间电介质（ILD）层中形成电容器。电容器可以在1微米厚的ILD中获得20纳法/ mm2的电容密度，并且适合于用包含外部电路元件的IC封装的电路中替换外部电容器。所公开的制造方法与铝或铜互连相兼容。

4. 发明授权

US07422968B2 Method for manufacturing a semiconductor device having silicided regions 有权
标题翻译：制造具有硅化物区域的半导体器件的方法
公开(公告)号：US07422968B2
公开(公告)日：2008-09-09
申请号：US10901756
申请日：2004-07-29
申请人： Jiong-Ping Lu , Clint Montgomery , Lindsey Hall , Donald Miles , Duofeng Yue , Thomas D. Bonifiield
发明人： Jiong-Ping Lu , Clint Montgomery , Lindsey Hall , Donald Miles , Duofeng Yue , Thomas D. Bonifiield
IPC分类号： H01L21/425
CPC分类号： H01L21/823835 , H01L21/02057 , H01L21/0206 , H01L21/02068 , H01L27/0629 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor devices. The method for manufacturing a semiconductor device (100) , among other steps, includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes subjecting the gate structure (120) and substrate (110) to a dry etch process and placing fluorine in the source/drain regions to form fluorinated source/drains (320) subsequent to subjecting the gate structure (120) and substrate (110) to the dry etch process. Thereafter, the method includes forming metal silicide regions (510, 520) in the gate structure (120) and the fluorinated source/drains (320).
摘要翻译：本发明提供一种半导体器件的制造方法以及包括该半导体器件的集成电路的制造方法。除了其他步骤之外，用于制造半导体器件（100）的方法包括在衬底（110）上形成栅极结构（120）并且在栅极结构（120）附近的衬底（110）中形成源极/漏极区域（190））。该方法还包括对栅极结构（120）和衬底（110）进行干蚀刻工艺，并且在将栅极结构（120）和衬底（120）经受栅极结构（120）和衬底（110）到干蚀刻工艺。此后，该方法包括在栅极结构（120）和氟化源极/漏极（320）中形成金属硅化物区域（510,520）。

5. 发明授权

US07397046B2 Method for implanter angle verification and calibration 有权
标题翻译：注塑机角度校验和校准方法
公开(公告)号：US07397046B2
公开(公告)日：2008-07-08
申请号：US11025474
申请日：2004-12-29
申请人： Duofeng Yue , Jeffrey Loewecke , JieJie Xu , Thomas Patrick Conroy
发明人： Duofeng Yue , Jeffrey Loewecke , JieJie Xu , Thomas Patrick Conroy
IPC分类号： G21K5/10 , H01J37/08 , A61N5/00
CPC分类号： H01L21/26513 , H01L22/14 , H01L22/20
摘要： Methods (300, 400) are described for calibrating the implantation angle of an ion implanter utilized in the manufacture of semiconductor products. One method (300) includes implanting (330) phosphorous ions into a pilot wafer held by a wafer platen held at a starting implantation angle in the ion implanter. The phosphorous implantation into a p-doped substrate of the pilot or blank wafer, for example, forms a semiconductive sheet. The method (300) then includes changing the implantation angle (340), and implanting another wafer (330) with phosphorous ions. The angle changing (340) and implanting (330) of other wafers continues in this manner until all wafers or angles are implanted (350) as desired. The phosphorous implanted wafers are then measured (360) with a four-point probe, for example, to obtain the sheet resistance of all the implanted wafers. The difference between the sheet resistances of the wafers at each corresponding implant angle is then obtained (370) to determine a functional relationship between the sheet resistance and the implantation angle. Finally, the functional relationship is then used to calibrate (380) the implantation angle of the implanter. For example, the lowest sheet resistance of the functional relationship may be determined, the relationship normalized to the lowest sheet resistance, then a zero degree implantation angle of the implanter is calibrated to to coincide with the lowest sheet resistance measurement.
摘要翻译：描述了用于校准在制造半导体产品中使用的离子注入机的注入角度的方法（300,400）。一种方法（300）包括将磷离子注入到由离子注入机中以起始注入角度保持的晶片压板保持的导向晶片中。例如，导入或空白晶片的p掺杂衬底中的磷注入形成半导体片。然后，方法（300）包括改变注入角度（340），以及用磷离子注入另一个晶片（330）。其他晶片的角度变化（340）和植入（330）以这种方式继续，直到根据需要植入所有晶片或角度（350）。然后用四点探针测量磷植入的晶片（360），以获得所有植入的晶片的薄层电阻。然后获得晶片在每个对应植入角度的薄层电阻之间的差异（370），以确定薄层电阻和注入角度之间的函数关系。最后，功能关系用于校准（380）植入器的植入角度。例如，可以确定功能关系的最低薄层电阻，将其与最低薄层电阻标准化的关系，然后将注入机的零度注入角度校准为与最低薄层电阻测量一致。

6. 发明授权

US07344985B2 Nickel alloy silicide including indium and a method of manufacture therefor 有权
标题翻译：包括铟的镍合金硅化物及其制造方法
公开(公告)号：US07344985B2
公开(公告)日：2008-03-18
申请号：US11551374
申请日：2006-10-20
申请人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
发明人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/26513 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.
摘要翻译：本发明提供一种半导体器件，一种制造方法以及一种用于制造包括该半导体器件的集成电路的方法。除了其他元件之外，半导体器件可以包括位于衬底上的栅极结构，栅极结构包括栅极电介质层和栅极电极层。该半导体器件还可以包括位于衬底中或栅极结构附近的源极/漏极区域和位于源极/漏极区域中的镍合金硅化物，所述镍合金硅化物具有位于其中的铟的量。

7. 发明申请

US20080128837A1 Nickel Alloy Silicide Including Indium and a Method of Manufacture Therefor 有权
标题翻译：包含铟的镍合金硅化物及其制造方法
公开(公告)号：US20080128837A1
公开(公告)日：2008-06-05
申请号：US12018313
申请日：2008-01-23
申请人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
发明人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
IPC分类号： H01L29/78
CPC分类号： H01L21/28518 , H01L21/26513 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.
摘要翻译：本发明提供一种半导体器件，一种制造方法以及一种用于制造包括该半导体器件的集成电路的方法。除了其他元件之外，半导体器件可以包括位于衬底上的栅极结构，栅极结构包括栅极电介质层和栅极电极层。该半导体器件还可以包括位于衬底中或栅极结构附近的源极/漏极区域和位于源极/漏极区域中的镍合金硅化物，所述镍合金硅化物具有位于其中的铟的量。

8. 发明授权

US07208409B2 Integrated circuit metal silicide method 有权
标题翻译：集成电路金属硅化物法
公开(公告)号：US07208409B2
公开(公告)日：2007-04-24
申请号：US11073982
申请日：2005-03-07
申请人： Jiong-Ping Lu , Duofeng Yue , Xiaozhan Liu , Donald S. Miles , Lance S. Robertson
发明人： Jiong-Ping Lu , Duofeng Yue , Xiaozhan Liu , Donald S. Miles , Lance S. Robertson
IPC分类号： H01L21/44 , H01L21/336 , H01L21/8234
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28518 , H01L29/7833
摘要： Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing regions (70) and the source and drain regions (60). The metal layer is reacted with the underlying fluorine containing regions to form a metal silicide.
摘要翻译：含氟区域（70）形成在MOS晶体管的源区和漏区（60）中。在含氟区域（70）和源极和漏极区域（60）之上形成金属层（90）。金属层与下面的含氟区域反应以形成金属硅化物。

9. 发明申请

US20070049022A1 NICKEL ALLOY SILICIDE INCLUDING INDIUM AND A METHOD OF MANUFACTURE THEREFOR 有权
标题翻译：镍合金硅胶包括其中的一种和其制造方法
公开(公告)号：US20070049022A1
公开(公告)日：2007-03-01
申请号：US11551374
申请日：2006-10-20
申请人： Peijun Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas Bonifield , Homi Mogul
发明人： Peijun Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas Bonifield , Homi Mogul
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/26513 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.
摘要翻译：本发明提供一种半导体器件，一种制造方法以及一种用于制造包括该半导体器件的集成电路的方法。除了其他元件之外，半导体器件可以包括位于衬底上的栅极结构，栅极结构包括栅极电介质层和栅极电极层。该半导体器件还可以包括位于衬底中或栅极结构附近的源极/漏极区域和位于源极/漏极区域中的镍合金硅化物，所述镍合金硅化物具有位于其中的铟的量。

10. 发明申请

US20050208764A1 Integrated circuit metal silicide method 有权
标题翻译：集成电路金属硅化物法
公开(公告)号：US20050208764A1
公开(公告)日：2005-09-22
申请号：US11073982
申请日：2005-03-07
申请人： Jiong-Ping Lu , Duofeng Yue , Xiaozhan Liu , Donald Miles , Lance Robertson
发明人： Jiong-Ping Lu , Duofeng Yue , Xiaozhan Liu , Donald Miles , Lance Robertson
IPC分类号： H01L21/265 , H01L21/285 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L29/78
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28518 , H01L29/7833
摘要： Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing regions (70) and the source and drain regions (60). The metal layer is reacted with the underlying fluorine containing regions to form a metal silicide.
摘要翻译：含氟区域（70）形成在MOS晶体管的源区和漏区（60）中。在含氟区域（70）和源极和漏极区域（60）之上形成金属层（90）。金属层与下面的含氟区域反应以形成金属硅化物。

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